)]}' { "log": [ { "commit": "ad55d5a4ea4bc82450b076fbf9faffc130a698bb", "tree": "6beb87c779785e2e3a823b171231c51c5c6f2602", "parents": [ "9bb8a322e991b899a6faff4ec14d2f4c6dba447d" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:32:16 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips\n\nAccording to their datasheets, ISSI IS25LP256 and IS25WP256 support\nboth 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended\naddress register. Flashrom will use 0xc5 by default if available,\nso adding the FEATURE_4BA_EAR_1716 flag makes no difference for now\n(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA\nset). It\u0027s better to have a comprehensive description of the chips,\nthough, in case somebody wants to use them in the future with a\nmaster that restricts available opcodes.\n\nChange-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70994\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d", "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35", "parents": [ "542b1f04869e7ac42b84800675f08f617ddf3f2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:07:34 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n instructions (and some programmers may be picky about which\n instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "542b1f04869e7ac42b84800675f08f617ddf3f2d", "tree": "9516bc3f06c3fc5d67203328e524b967b5d36901", "parents": [ "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 14:30:12 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Rename FEATURE_4BA_EXT_ADDR -\u003e _EAR_C5C8\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\nTo prepare for other instructions than the default 0xc5/0xc8, rename\nthe original feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70992\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c", "tree": "175824426d5d38363c842aa3bfd4267477d89073", "parents": [ "5215eab80aa6ce4682aaadac5b318cb6c6d1bd7b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 15:17:14 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Drop FOUR_BYTE_ADDR comments\n\n4BA support is implemented by now. So drop these obsolete comments.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I28c5d1de052c28735d5f07874874068ee744b77f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64600\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70991\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5215eab80aa6ce4682aaadac5b318cb6c6d1bd7b", "tree": "c927408b441b4e47102a46386176f27a14f2c3d6", "parents": [ "fffc48d247cef5102113d97538054066546b2297" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 15:13:07 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Split W25Q256.V\n\nThe W25Q256JV supports the full set of 4BA instructions, including two\nnative-4BA block erasers.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I1a68121ff40d2b1769632d8e5151c2cd972c23ef\nTicket: https://ticket.coreboot.org/issues/362\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64599\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70990\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fffc48d247cef5102113d97538054066546b2297", "tree": "cdb49567c3d7c2291fa33221989516afb1b03abf", "parents": [ "3f3c1f3238dcede30d0d15d36da6326b428b8b12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 14:26:06 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L\n\nThese chips seem to be rather regular, supporting 2.7V..3.6V, the\ncommon erase block sizes 4KiB, 32KiB, 64KiB and the usual block-\nprotection bits.\n\nStatus/configuration register naming differs from other vendors,\nthough. These chips have 2 status registers plus 3 configuration\nregisters. Configuration registers 1 \u0026 2 match status registers\n2 \u0026 3 of what we are used from other vendors. Read opcodes match\ntoo, however writes are always done through the WRSR instruction\nwhich can write up to 4 bytes (SR1, CR1, CR2, CR3).\n\nS25FL256L supports native 4BA commands and entering a 4BA mode.\nHowever, it uses an unusual opcode (0x53) for the 32KiB 4BA block\nerase.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I356df6649f29e50879a4da4183f1164a81cb0a09\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f3c1f3238dcede30d0d15d36da6326b428b8b12", "tree": "9adc4f207793fe401c9ffd28e2f7c60460766533", "parents": [ "478e179f2d5ecf6a8b82984444b9111913a8f50f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 16:48:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "spi25_statusreg: Allow WRSR_EXT for Status Register 3\n\nSpansion flash chips S25FL128L and S25FL256L use the WRSR instruction to\nwrite more than 2 registers. So align SR2 and SR3 support: The current\nFEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3\nis added. Also, WRSR3 needs a separate flag now.\n\nVerified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "478e179f2d5ecf6a8b82984444b9111913a8f50f", "tree": "a87192cf8ab508ce56cb441147d00d0658355e29", "parents": [ "1e6aabc39de5ca46a69ef1b164ce55a4288753c3" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Sat Jun 04 01:34:44 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "flashrom.c, flashcips.c: Test the order of erase functions\n\nAdd a check so that the erase functions for all flashchips are in\nincreasing order of their respective eraseblock sizes. This is required\nfor the implentation of the improved erasing algorithm. The patch uses\nthe count of eraseblocks in each erase function to determine the order\n(More eraseblocks means that the function has smaller eraseblock size).\nAlso fix the structs in flashchips.c which were found to be not\nconforming to this test.\n\nTested: make \u0026\u0026 ./flashrom\n\nChange-Id: I137cb40483fa690ecc6c7eaece2d9d3f7a851bb4\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64961\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70987\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Aarya \u003caarya.chaumal@gmail.com\u003e\n" }, { "commit": "1e6aabc39de5ca46a69ef1b164ce55a4288753c3", "tree": "103de40711dcff4b3e4332e879b1aae380183a82", "parents": [ "2502dbd627e595d2974b1419f5e54a2faa7406a1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 16:39:07 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "writeprotect: Add line-break after each `spew` message\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I3131ff0e3fa4f9e949ce2e8d2d0a9c862a15e1cd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64745\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70986\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2502dbd627e595d2974b1419f5e54a2faa7406a1", "tree": "139f05845f46312101c492dd4aefd75a75ade642", "parents": [ "8f5bd989971c97c9d160cf4f1aa2b91f72b152fe" ], "author": { "name": "Atul Dhudase", "email": "adhudase@codeaurora.org", "time": "Tue Sep 21 10:02:20 2021 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "Add W25Q512NW-IM ID to flashrom\n\nAdd Winbond W25Q512NW-IM chip ID and specs to flashrom.\n\nTested: flash W25Q512NW-IM using CCD.\n\nOriginal-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65\nOriginal-Signed-off-by: Atul Dhudase \u003cadhudase@codeaurora.org\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890\nOriginal-Reviewed-by: Shelley Chen \u003cshchen@chromium.org\u003e\nOriginal-Reviewed-by: Vadim Bendebury \u003cvbendeb@chromium.org\u003e\nOriginal-Tested-by: Shelley Chen \u003cshchen@chromium.org\u003e\nOriginal-Commit-Queue: Shelley Chen \u003cshchen@chromium.org\u003e\n(cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61)\n\nNote: this commit was cherry-picked from the cros tree but\nincludes corrections to errors in the original commit\u0027s 4BA\nfeature flags that were spotted by Angel Pons\n\nChange-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70985\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8f5bd989971c97c9d160cf4f1aa2b91f72b152fe", "tree": "2a3ead55a8311b9a917f4e6291c8e9e61291ea4a", "parents": [ "d1af307018bf73b1e585b6427a84b4a58e42c934" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Wed Aug 26 09:15:53 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "flashchips: Fix W25Q256.W\n\nThe JW is the only known variant. A W25Q256FW may have existed with\nless 4BA instructions supported, but it never showed up and no data-\nsheet is available.\n\nUsed the datasheet from here:\nhttps://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf\n\nChange-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTicket: https://ticket.coreboot.org/issues/362\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70984\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1af307018bf73b1e585b6427a84b4a58e42c934", "tree": "74e8bddd48fb391178abc188141c96bfc1625da1", "parents": [ "801fcd0123af9a253d68089e2728d0f51a64b749" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Nov 08 00:00:43 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "flashchips: enable write-protection for W25Q{64,128}.V\n\nConfiguration for W25Q64 was tested on hardware (W25Q64FV).\n\nEmulation of W25Q128 in dummyflasher will be extended to support WP.\nHaven\u0027t tested this one on hardware, but it\u0027s the same configuration as\nfor W25Q64 except that it has WPS.\n\nW25Q64JV chip was renamed to W25Q64JV-.M (those with QPI).\n\nW25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)\nand W25Q64JV-.Q (SR3 and WPS, but no QPI).\n\nflashrom-stable: FIXME added, W25Q128.V should probably be split.\n\nChange-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59071\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70982\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "801fcd0123af9a253d68089e2728d0f51a64b749", "tree": "71351110f1e02733565e415bf6ec322e11958d8d", "parents": [ "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Dec 19 18:45:16 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "writeprotect: add WPS bit and always set it to zero\n\nWPS bit controls use of individual block protection which is mutually\nexclusive with protection based on ranges. Proper support requires\nextension of the API as well as implementation, so here we\u0027re just\nmaking sure that range-based protection is enabled and our WP\nconfiguration is not ignored by the chip.\n\nChange-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60231\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70981\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf", "tree": "020dea176939135afa15e8f328088e808b6c812a", "parents": [ "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Dec 19 18:37:51 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "spi25_statusreg.c: add SR3 read/write support\n\nAdds support for reading and writing the third status register.\n\nFeature flag is not needed because it would never on its own control\nwhether SR3 access occurs. If added, it would be in one of three\npossible states: wrong, useless or redundant.\n\nChange-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70980\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21", "tree": "cd09884914e46f8641d59b95a68132d47c1daa13", "parents": [ "551664c6a7c447746503afcd6e303c9b21fff71c" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Oct 20 17:09:09 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "flashchips.c: mark IS25LP064 as TEST_OK_PREW\n\nTested \u0027-w\u0027, \u0027-E\u0027 and \u0027-r\u0027 successfully with\nmy FT2232H programmer.\n\nChange-Id: I2197ce0be9db7c3d74b24c7445dc06238584ffea\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58472\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70979\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "551664c6a7c447746503afcd6e303c9b21fff71c", "tree": "7d2044394629218ba5b58afad9dd8f68e5034f87", "parents": [ "ccae68ac91b00eb68adf11fa88e6d9a1aaa01b0b" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Mar 09 16:09:08 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "flashchips.c: Mark GD25Q40(B) as tested\n\nAs mentioned by Wolf Dieter Brandt in his mail from 07.Feb.22.\n\nChange-Id: Idec3d82efbdf095c3d57bfe5f0fd487007b554cb\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62712\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70978\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ccae68ac91b00eb68adf11fa88e6d9a1aaa01b0b", "tree": "3f1f0c9d24adb8b3034dd5414b84a06b15084637", "parents": [ "d32e18b0c03a0426f808477544f6ecec9ae10f66" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 08 01:07:01 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "writeprotect.c: refactor and fix wp_mode functions\n\nThis is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.\n\nUse a lookup table in get_wp_mode() and drop the srp_bit_present check,\nsince a chip without SRP is just FLASHROM_WP_MODE_DISABLED.\n\nAdd a srp_bit_present check to set_wp_mode() if the mode requires it.\n\nTested: flashrom --wp-{enable,disable,status} on AMD dut\n\nChange-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70977\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d32e18b0c03a0426f808477544f6ecec9ae10f66", "tree": "73e1e07c595028935a4183b628101b95c53fd660", "parents": [ "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Feb 15 18:06:55 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "flashchips.c: add writeprotect support for more chips\n\nChips I had available for testing were tested with all writeprotect\ncommands and an FT232H adapter. Chips I wasn\u0027t able to test were just\nchecked against the datasheets.\n\nChips used for testing (including chips added in previous patches) are\nlisted in the table below:\n\nFlashrom Chip name | Chip(s) tested\n---------------------------------+----------------------------\nAT25SL128A |\nEN25QH128 |\nGD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG\nGD25LQ64(B) | GD25LQ64CWIG\nGD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG\nGD25Q256D | GD25Q256DYIG\nGD25Q64(B) | GD25Q64CSIG\nW25Q128.JW.DTR |\nW25Q128.V..M |\nW25Q128.W |\nW25Q256JV_M |\nW25Q256.V |\nW25Q64.W |\nXM25QH128C |\nXM25QH256C |\n\nTested: flashrom --wp-{enable,disable,range,list,status}\n\nChange-Id: I7f3d4c4148056098a845b5c64308b0333ebda395\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70976\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb", "tree": "85191d34786a8297b7618919e50b64095fa2cee0", "parents": [ "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 28 16:18:28 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "spi25_statusreg: delete spi_read_status_register()\n\nDelete the spi_read_status_register() function because the generic\nspi_read_register() function can be used instead.\n\nThis patch also converts all call sites over to spi_read_register().\nA side effect is that error codes are now properly propagated and\nchecked.\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n Read SR1/SR2 with --wp-status and activated various WP ranges\n that toggled bits in both SR1 and SR2.\n\nChange-Id: I146b4b5439872e66c5d33e156451a729d248c7da\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70975\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3", "tree": "cbbb97227c2ae0e4cf45b9d222e22893118f0ec0", "parents": [ "9e1afb785efd0e6144a19d1faff012d4cbf5a668" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Nov 22 13:18:49 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:46 2022 +0100" }, "message": "spi25_statusreg: inline spi_write_register_flag()\n\nCreating the entire SPI command that should be sent to the chip in\nspi_write_register() is simpler than splitting it across two functions\nthat have to pass multiple parameters between them.\n\nAdditionally, having separate spi_write_register_flag() function\nprovided little benefit, as it was only ever called from\nspi_write_register().\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n Read SR1/SR2 with --wp-status and activated various WP ranges\n that toggled bits in both SR1 and SR2.\n\nChange-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70974\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9e1afb785efd0e6144a19d1faff012d4cbf5a668", "tree": "9a638ea81371e96b8dfe4740c536d5e04e7d8111", "parents": [ "b6112a53add4a9fc144066252be11099cecc496b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 02:29:22 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:46 2022 +0100" }, "message": "writeprotect: add {get,set}_wp_mode()\n\nTested: flashrom --wp-{enable,disable,status}\n\nChange-Id: I7b68e940f0e1359281806c98e1da119b4caf8405\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58483\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70973\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b6112a53add4a9fc144066252be11099cecc496b", "tree": "d31441efeee7633ff172e95551dbe4200e9f737a", "parents": [ "077c0d131a98f7b4fd19de3ff30e7dc9a558ce60" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 02:28:23 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:46 2022 +0100" }, "message": "writeprotect: add set_wp_range()\n\nTested: flashrom --wp-{status,range}\n\nChange-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58482\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70972\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "077c0d131a98f7b4fd19de3ff30e7dc9a558ce60", "tree": "c4281650f8f0d80d4de1d2b07de21b08c31f8a3b", "parents": [ "1234d110cf11e2b72ef96349920d5b79d3089f6c" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:50:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "libflashrom,writeprotect: add flashrom_wp_get_available_ranges()\n\nGenerate list of available ranges by enumerating all possible values\nthat range bits (BPx, TB, ...) can take and using the chip\u0027s range\ndecoding function to get the range that is selected by each one.\n\nTested: flashrom --wp-list\n\nChange-Id: Id51f038f03305c8536d80313e52f77d27835f34d\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58481\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70971\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1234d110cf11e2b72ef96349920d5b79d3089f6c", "tree": "89329957cf6bc237fd254dbb18795eec7cb0838e", "parents": [ "c9feb1bdfa96745a200b9a62dc4234446db8ddb6" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 02:28:23 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "writeprotect: add get_wp_range() for decoding ranges\n\nTested: flashrom --wp-{status,range} at end of patch series\n\nChange-Id: I5a1dfcf384166b1bac319d286306747e1dcaa000\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59183\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70970\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c9feb1bdfa96745a200b9a62dc4234446db8ddb6", "tree": "b532df293904cb48d7efa7b127a0072f48801835", "parents": [ "da1c834e9899e5094377a33d19daa53c0d88640b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:35:13 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "flashchips,writeprotect_ranges: add range decoding function\n\nAllow chips to specify functions that map status register bits to\nprotection ranges. These are used to enumerate available ranges and\ndetermine the protection state of chips. The patch also adds a range\ndecoding function for the example chips. Many other chips can also be\nhandled by it, though some will require different functions (e.g.\nMX25L6406 and related chips).\n\nAnother approach that has been tried in cros flashrom is maintaining\ntables of range data, but it quickly becomes error prone and hard to\nvalidate.\n\nUsing a function to interpret the ranges allows compact encoding with\nmost chips and is flexible enough to allow chips with less predictable\nranges to be handled as well.\n\nTested: dumped range tables, checked against datasheets\n\nChange-Id: Id163ed80938a946a502ed116e48e8236e36eb203\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70969\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "da1c834e9899e5094377a33d19daa53c0d88640b", "tree": "9fc9415b879ad477b8e6475bb94075b406b4180e", "parents": [ "e75127a19dc53c6c076fa634a647897f6a8c875f" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 00:58:12 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "libflashrom,writeprotect: add functions for reading/writing WP configs\n\nNew functions are exposed through the libflashrom API for\nreading/writing chip\u0027s WP settins: `flashrom_wp_{read,write}_cfg()`.\n\nThey read/write an opaque `struct flashrom_wp_cfg` instance, which\nincludes the flash protection range and status register protection mode.\n\nThis commit also adds `{read,write}_wp_bits()` helper functions that\nread/write chip-specific WP configuration bits.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58479\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70968\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e75127a19dc53c6c076fa634a647897f6a8c875f", "tree": "10cbe1cea1c4da8207fc7ddeeb7476cb0768d639", "parents": [ "c6c3f28c66e0ad792274ca05029a120925e21be6" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:12:39 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "writeprotect.h: add structure to represent chip wp configuration bits\n\nAdd `struct wp_bits` for representing values of all WP bits in a chip\u0027s\nstatus/config register(s).\n\nIt allows most WP code to store and manipulate a chip\u0027s configuration\nwithout knowing the exact layout of bits in the chip\u0027s status registers.\n\nSupporting other chips may require additional fields to be added to the\nstructure.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58478\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70967\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c6c3f28c66e0ad792274ca05029a120925e21be6", "tree": "0df6153a2d812235b3defe835f40b9ed08684c92", "parents": [ "9de3f8710d5c46d35cd9869018c85e5aa51483b0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 23:34:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "flash.h,flashchips.c: add writeprotect bit layout map to chips\n\nThis patch adds a register bit map `struct reg_bit_info`, with fields\nfor storing the register, bit index, and writability of each bit that\naffects the chip\u0027s write protection. This allows writeprotect code to be\nindependent of the register layout of any specific chip. The new fields\nhave been filled out for example chips.\n\nThe representation is centered around describing how bits can be\naccessed and modified, rather than the layout of registers. This is\ngenerally easier to work with in code that needs to access specific bits\nand typically requires specifying the locations of fewer bits overall.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70966\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0", "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df", "parents": [ "0167522794a2e66f00248347122c1bb8ce3b001d" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:32:25 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0167522794a2e66f00248347122c1bb8ce3b001d", "tree": "ac01ed9312b2946bdcdbe1abf1078b69f6117183", "parents": [ "236a38cc46ac810d0be679402bb21e83aebcb8b9" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:30:41 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "spi25_statusreg: make register read/write functions generic\n\nThis patch adds new spi_{read,write}_register() functions that take the\nsource/destination register as an argument. Currently they can only\naccess SR1, support for other registers will be added in another patch.\n\nSince we\u0027re refactoring things, this commit also makes\nspi_read_register() return an error code, making it possible to identify\nerror conditions that spi_read_status_register() concealed.\n\nThis also removes the initial 100ms delay between writing a register and\nthe first attempt to check the chip\u0027s status. An initial delay was added\nto avoid needing to read the status register multiple times, but that is\nunlikely to cause problems on modern flash chips.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70964\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "236a38cc46ac810d0be679402bb21e83aebcb8b9", "tree": "a460050e0a50e0cb37383709b1abfdbcbc7bbcbc", "parents": [ "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Fri Nov 05 11:48:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips: Add W25Q64JV\n\nI have successfully tested it with FT2232H-programmer.\n\nChange-Id: Ia9a32146b225eca66e9a6bfef45be5f2b24aef46\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58971\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70963\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6", "tree": "daf3ce9e6a6aa471eeeea5296904ff369d448f65", "parents": [ "571f6ad31f0047fdbf613448e04d9c7138ade662" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Sep 29 09:28:07 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips.c: mark EN25F10 as TEST_OK_PREW\n\nAs reported by Wolf Dieter Brandt in his e-mail from 09.Aug.2021.\n\nChange-Id: I0c19f84780e7fa3699fd706f8e105fc5937ba8bf\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58031\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70962\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "571f6ad31f0047fdbf613448e04d9c7138ade662", "tree": "a0926521de7d240eab415da54dc70ffa5712fd5a", "parents": [ "981a344f65c2125b7aba72c0a61760f33c508ec2" ], "author": { "name": "Tao Xia", "email": "xiatao5@huaqin.corp-partner.google.com", "time": "Wed Jul 21 16:41:53 2021 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12833F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nSigned-off-by: Tao Xia \u003cxiatao5@huaqin.corp-partner.google.com\u003e\nChange-Id: I14ab7e04f5209d2bcf34b0d2de9da2c01bf32d00\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56546\nOriginal-Reviewed-by: Weimin Wu \u003cwuweimin@huaqin.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70961\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "981a344f65c2125b7aba72c0a61760f33c508ec2", "tree": "79e38d75327c731023c3e4b5f2729eb5695b2484", "parents": [ "2649dde2be69f01f4c5bee4a7d21223bd25e322c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Tue Jun 22 11:16:55 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips.c: Add \u0027GD25LQ128E\u0027 to match C and D variants\n\nAs defined by gigadevice. C, D and E are all meant to\nbe the same.\n\nChange-Id: I3bef9386a185a0e8c54c125af5509b63540995aa\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55742\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70960\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2649dde2be69f01f4c5bee4a7d21223bd25e322c", "tree": "2232b470f8921c5b5cb9cddf8864536c5e9eec26", "parents": [ "3ba8315e134c3fc0f29b538abb22fd9e85a2361f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 03 13:47:39 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12873F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nChange-Id: I59c8067f15b5ceac5a2e2f8fe93431a465f17e23\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56054\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70959\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ba8315e134c3fc0f29b538abb22fd9e85a2361f", "tree": "315ee58cda0d2d9de74142d442d43bf31ba500e2", "parents": [ "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Tue Jun 08 10:52:19 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add support for Macronix MX66L1G45G\n\nTested on Dediprog SF600: Reading and writing works.\n\nChange-Id: I554e828c97d9ec77b08489573a34e176599d2518\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55353\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70958\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8", "tree": "67f1c17c4dd4fd6ab500a78c5aee1ce7db03d5d1", "parents": [ "5fa050515d2fff9679d38803a8594e4a8c5a407a" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Mon Feb 15 13:16:57 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: Mark MT25QL256 as tested\n\nAs mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020.\n\nChange-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70957\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5fa050515d2fff9679d38803a8594e4a8c5a407a", "tree": "59ba8caf8f49cbec055d2cb0b47052d3e54c65ab", "parents": [ "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri May 14 15:26:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips: change chip name from \u0027W25Q64JW\u0027 to \u0027W25Q64JW...M\u0027\n\nAccording to the W25Q64JW datasheet rev. E, only devices ending with the\nletter \u0027M\u0027 have a device ID of 8017h. There are other variants with\ndifferent device IDs. This patch makes the \u0027W25Q64JW...M\u0027 definition\nconsistent with the \u0027W25Q32JW...M\u0027 definition.\n\nThe device ID macro defined in flashchips.h has also been renamed from\nWINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.\n\nChange-Id: Ib0dc914da286a191d22e666332b1063b88db4251\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70956\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0", "tree": "0d12cf62cf976d9a3378fa48a245478c1caffab1", "parents": [ "b6683e0a5586537269524eaadee5619d1dec410b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Sat May 08 17:31:23 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: add support for W25Q32JW...M\n\nThe chip was added to cros flashrom in\n`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.\nQuoting from the commit message:\n\n\u003e We have varied the correct chip name is reported as well as\n\u003e write and read 16MBytes of random data and verified the checksum\u0027s match.\n\u003e Further, --wp-list appears to report the correct ranges.\n\u003e\n\u003e BUG\u003db:130199963\n\u003e BRANCH\u003dnone\n\u003e TEST\u003dRan flashrom with a Dediprog SF100, RW random data and checksum matched.\n\nChange-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70955\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b6683e0a5586537269524eaadee5619d1dec410b", "tree": "b2bdb49813421373adc4a5f8ede57b920b89e05c", "parents": [ "6e69e2b5f78104e5b54e83be889ae887702309ff" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:04:29 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add MX25L3233F\n\nOnly mattering difference to the MX25L3273E seems to be the voltage\nrange (starting at 2.65V instead of 2.7V). I don\u0027t think that would\njustify yet another entry.\n\nChange-Id: I73402dddedf360ab84caed4c019efe27b477d4c2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52570\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70954\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6e69e2b5f78104e5b54e83be889ae887702309ff", "tree": "78ea64917e28700796c57bba0d0f8602145360d0", "parents": [ "475a7eed6d6589c8a1e5267a1f4be3500fb245c4" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:03:13 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Correct OTP comment for MX25L3273E\n\nThe datasheet says 4K bits, maybe just a copy-paste error.\n\nChange-Id: I42b10aa09c969e5c5e7102b1e8ab496f52bd27bb\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52569\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70953\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "475a7eed6d6589c8a1e5267a1f4be3500fb245c4", "tree": "6a90aa1167acc44f0ddf92f0124d3eaa220bef33", "parents": [ "1ebda787f1c6bec8e63d06a01ba921c49c4e2187" ], "author": { "name": "Christian Kudera", "email": "coreboot@kudera.at", "time": "Tue Apr 20 22:50:01 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add support for Boya/BoHong Microelectronics B_25D16A\n\nRead tested on CH341A\n\nChange-Id: I25b776204affda94cc7e753e7671ef9d3d9508f1\nSigned-off-by: Christian Kudera \u003ccoreboot@kudera.at\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52555\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70952\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1ebda787f1c6bec8e63d06a01ba921c49c4e2187", "tree": "193cb9fe46cd8ca4887496c6fc63e6cc7e8fe7cc", "parents": [ "148254be920530d54d76d742b30a3fb61689cf07" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Apr 20 21:39:11 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips: Adapt IDs for Boya Microelectronics\n\nLooks like BoHong Microelectronics has the same vendor ID and makes very\nsimilar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have\nthe same specifications and their datasheets are mostly identical.\n\nChange-Id: I8d6951797daeeecca6af200c995297c0394adefd\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70951\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "148254be920530d54d76d742b30a3fb61689cf07", "tree": "ff3580e4dcd6726dc1dd97ce6fa2d01d5f1135f6", "parents": [ "e64ef6d72741c39cb9a5e866d9952f2b14366996" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:21:10 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark MX25U25635F as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit 419e32ae457cc36b03757b89471a7ce3770e9611`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dTested writes using Servo\n\nChange-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70950\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e64ef6d72741c39cb9a5e866d9952f2b14366996", "tree": "9ae607243716dcdab4d39e4e282d89412bf020af", "parents": [ "df889fa924154ffd1265971b05002c28651b8e83" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:15:40 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark GD25Q256D as TESTED_OK_PREW\n\nTested read/write/erase/verify with FT232H programmer.\n\nChange-Id: Ia7d52b69eb571113fe3c60ec9a139ee67180509b\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51735\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70949\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "df889fa924154ffd1265971b05002c28651b8e83", "tree": "068e75775d2d757e3cf1a264aa8e7f4d5c069c22", "parents": [ "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:10:45 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: mark EN25S64 as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dread and write BIOS on glimmer with Eon device.\n\nChange-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70948\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5", "tree": "e65d194cc42f67ab9caf8bcc6dbf400d5546b6f5", "parents": [ "c205487aede60d9926541159631a0e360abdc82d" ], "author": { "name": "Tim Chen", "email": "tim-chen@quanta.corp-partner.google.com", "time": "Mon Jul 06 14:59:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "CHROMIUM: flashrom: update .tested field for EN25QH128\n\nupdate .tested field from TEST_UNTESTED to TEST_OK_PREW\n\nTested: Flash Duffy bios\n pass on running `flashrom_tester /usr/sbin/flashrom host`\n\nOriginal-Change-Id: I9467588988c2cab0987737c53ace0832144ef169\nOriginal-Signed-off-by: Tim Chen \u003ctim-chen@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Commit-Queue: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n(cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff)\n\nChange-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70947\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c205487aede60d9926541159631a0e360abdc82d", "tree": "417b46539f418ddfc293d1041ad762d54207dec5", "parents": [ "813a7e2eef268f2e63b2cac2e9b60a2ed2365945" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 15 18:57:32 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips: Mark Macronix MX25L1635D as tested\n\nTested probe, read, erase and write with a FTDI FT2232H successfully.\n\nChange-Id: I7421b7e36e687ea2ffff494c00157976db73ac43\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49489\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70945\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "813a7e2eef268f2e63b2cac2e9b60a2ed2365945", "tree": "89eba409e95982a9507434721351671c52df042d", "parents": [ "721a4f390410debb77487562c8a47a20edb4d7f2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Jan 08 08:48:17 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW\n\nI have successfully probed/read/erased/written a GD25LQ128D, so marking\nthis entry as tested.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70944\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "721a4f390410debb77487562c8a47a20edb4d7f2", "tree": "cf842e10410c39de9bf712d547cdd23f40a5a19b", "parents": [ "ef88423928abf61fa894d2798a9d265fd001cd26" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Dec 14 07:39:02 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "spi25_statusreg.c: restore SR contents at flashrom exit\n\nregister_chip_restore() provides a general mechanism for restoring a chip\u0027s state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR\u0027s sector layout bits so that entire flash accessible.\n\nThis patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash.\n\nImported from cros flashrom at `b170dd4e1d5c33b169c5`\n\nChange-Id: If2f0e73518d40519b7569f627c90a34c364df47c\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70943\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ef88423928abf61fa894d2798a9d265fd001cd26", "tree": "8ceb8aa058cf63a0f39e4a9c8114733b0914af1c", "parents": [ "e0e8b2b8f99030962994b876353e3a69cb68af80" ], "author": { "name": "luke he", "email": "sixuerain@qq.com", "time": "Mon Dec 28 18:22:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips.c: Add support for XMC new SPI flash types\n\nAdds initial support for the follow SPI flash chips:\n\n XM25QU64C\n XM25QU128C\n XM25QU256C\n XM25QH64C\n XM25QH128C\n XM25QH256C\n\nflashrom-stable:\n* Added missing 4BA flags / erasers\n* Dropped wrong, superfluous comments\n* Sorted\n\nSigned-off-by: Luke He \u003csixuerain@qq.com\u003e\nChange-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70942\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e0e8b2b8f99030962994b876353e3a69cb68af80", "tree": "ff9e47bf8eba1954ad347a9ea8bab70bb7af2306", "parents": [ "4ad486465ccceedce372c498ad19ac84edbc0078" ], "author": { "name": "Zoltan HERPAI", "email": "wigyori@uid0.hu", "time": "Sat Aug 08 16:04:34 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips: Mark Intel 25F640S33B8 as TESTED_PREW\n\nTested with ch341a_spi from an Atheros AP81 reference board.\n\nChange-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef\nSigned-off-by: Zoltan HERPAI \u003cwigyori@uid0.hu\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44342\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70941\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4ad486465ccceedce372c498ad19ac84edbc0078", "tree": "b278a2499ed1ac3101b4e74f48a8a622640c15d3", "parents": [ "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Nov 05 13:54:27 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashrom.c: implement chip restore callback registration\n\nAllows drivers to register a callback function to reset the\nchip state once programming has finished. This is used by\nthe s25f driver added in a later patch, which needs to change\nthe chip\u0027s sector layout to be able to write to the entire flash.\n\nAdapted from cros flashrom at\n`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.\n\nChange-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70940\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e", "tree": "bb4d94a94cf593bae5592de6bdee9afe61eafeae", "parents": [ "0cf3e12fd5e420115551062a225b44e1782ba629" ], "author": { "name": "Jack Olsen", "email": "omegasec@tutanota.com", "time": "Sat Aug 08 21:12:13 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Boya Microelectronics BY25Q128AS\n\nTested on Buspirate.\n\nSigned-off-by: Jack Olsen \u003comegasec@tutanota.com\u003e\nChange-Id: I881ba86cfaa82e43c73360135d47c74d896cc191\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70939\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cf3e12fd5e420115551062a225b44e1782ba629", "tree": "917b704ffedd00099c9958126fe8698edc4ba89f", "parents": [ "3153260aecbec2e8719f8b093c0f17ec860e4b2c" ], "author": { "name": "Jakob Petersson", "email": "github@jakobpetersson.se", "time": "Mon Feb 18 01:55:43 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Fudan SPI flash chips\n\nflashrom-stable: Found additional info on Github:\n\nCode is taken from existing PATCH by Stefan Tauner stefan.tauner@alumni.tuwien.ac.at\nhttps://mail.coreboot.org/pipermail/flashrom/2016-June/014672.html\n\nWith the only change being the Manufacture ID being changed\nfrom 0x04h to 0xA1h.\n\nI have only tested it with FM25F005 and it seems to work.\n\nSigned-off-by: Jakob Petersson \u003cgithub@jakobpetersson.se\u003e\nChange-Id: I8045ecb8778fd6111fcccc075e69928f131a926a\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/46513\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70938\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3153260aecbec2e8719f8b093c0f17ec860e4b2c", "tree": "3edf5db4440c03b321b3ce5f74816c488f08bc1e", "parents": [ "7e6f3a7ccb8fb5206ceaddc9bb0c285f4264cabf" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Aug 16 17:14:56 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add W25Q256JW_DTR\n\nW25Q256JW currently has two variants, the W25Q256JW with device\nID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka\nW25Q256JW-IM) with device ID 0x8019 added by this patch.\n\nWinbond W25Q256-series chips have a few device IDs:\n0x4019: W25Q256FV\n0x6019: W25Q256JW\n0x7019: W25Q256JV\n0x8019: W25Q256JW_DTR\n\nHence we need to be more specific with naming than usual to avoid a\nfalse positive with wildcards.\n\nChange-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386\nOriginal-Reviewed-by: Simon Buhrow\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70937\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e6f3a7ccb8fb5206ceaddc9bb0c285f4264cabf", "tree": "7ded0eda3ea711bab56e644997601a1cc38ef40c", "parents": [ "ebbdc02ee860ee4e3baeecc6a0c220d138499c59" ], "author": { "name": "Steve Markgraf", "email": "steve@steve-m.de", "time": "Mon Jul 13 18:22:56 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add support for Macronix MX25L5121E\n\nTested with ch341a_spi.\n\nChange-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766\nSigned-off-by: Steve Markgraf \u003csteve@steve-m.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43416\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70936\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ebbdc02ee860ee4e3baeecc6a0c220d138499c59", "tree": "23a7947c060e0eddbfb60e6112eb5b5696057913", "parents": [ "0120985bd3ccc5d22906863b21902b29e87bc05b" ], "author": { "name": "Jacob Appelbaum", "email": "jacob@appelbaum.net", "time": "Mon Sep 02 09:10:43 2019 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "Add support for Winbond W25X05CL\n\nThis commit adds support for the Winbond W25X05CL SPI flash chip. The\nWinbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors.\nI have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL\nflash chip using a test clip. Reading, erasing, and writing all function\nas expected.\n\nChange-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc\nSigned-off-by: Jacob Appelbaum \u003cjacob@appelbaum.net\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70935\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0120985bd3ccc5d22906863b21902b29e87bc05b", "tree": "97ac99f76b39e88566e10b0b8e11b6ded21ba3e6", "parents": [ "5eca427ae64519b70d1c4ccfb427305ca9974ba0" ], "author": { "name": "el-coderon", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Apr 29 12:12:53 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add W25Q256.W\n\nNicklas Lennert wrote me via the flashrom mailing list that\nhe successfully ran read, write and verify cmd.\n\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nChange-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70934\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1bbc501f79319cc6c8d839bc44fa55e96afab33a", "tree": "930ed121151a82ddc0e157c3b2c1b50de99a6a77", "parents": [ "5543961c01fe6d6fb1ec7e68b8dcc766d0d272e3" ], "author": { "name": "Scott Chao", "email": "scott.chao@bitland.corp-partner.google.com", "time": "Wed Apr 08 22:10:50 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "flashchips: Add support for Winbond W25Q64JW\n\nTested: flash coreboot on kakadu and get successful result.\n\nChange-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967\nSigned-off-by: Scott Chao \u003cscott.chao@bitland.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nOriginal-Tested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70932\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5543961c01fe6d6fb1ec7e68b8dcc766d0d272e3", "tree": "945ad58063335ccf3b76d7dc02eded147c9b1b7f", "parents": [ "3214f58db8f8cceb40d4faa16130124446cc35fa" ], "author": { "name": "Joel Stanley", "email": "joel@jms.id.au", "time": "Sat Jul 27 19:25:35 2019 +0930" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "flashchips: Add W25Q512JV\n\nhttps://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf\n\nTested with dediprog SF100.\n\nChange-Id: I8d16f0918785795cc49500435a03641b87d706e9\nSigned-off-by: Joel Stanley \u003cjoel@jms.id.au\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595\nOriginal-Reviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70931\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3214f58db8f8cceb40d4faa16130124446cc35fa", "tree": "6b7d14da618a215fc619d786305bfad9387e5163", "parents": [ "f62623cff61d677609fbd92a71a5ad7875ad9b8a" ], "author": { "name": "Dino Li", "email": "Dino.Li@ite.com.tw", "time": "Wed Mar 25 17:39:53 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "flashchips: add support for GigaDevice GD25WQ80E\n\nSupport GD25WQ80E, which is the internal flash of IT81202.\n\nTested: Building flashrom and flashing FW image into IT81202 successfully.\n\nChange-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8\nSigned-off-by: Dino Li \u003cDino.Li@ite.com.tw\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70930\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f62623cff61d677609fbd92a71a5ad7875ad9b8a", "tree": "989cca84ef37d1878dca9b25220766fd2123cb49", "parents": [ "9245b889dde1dba76cd696d5d354ac89b84fca65" ], "author": { "name": "sibradzic", "email": "5964548+sibradzic@users.noreply.github.com", "time": "Sat Mar 14 17:21:34 2020 +0900" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "flashchips: Add Macronix MX25R3235F\n\n32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is\nsimilar to the already-supported MX25R6435F, but the total size is\nhalved.\n\nTested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed\nworking probe, read, erase and write.\n\nFixes: https://github.com/flashrom/flashrom/issues/43\n\nChange-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5\nSigned-off-by: Samir Ibradzic \u003csibradzic@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70929\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9245b889dde1dba76cd696d5d354ac89b84fca65", "tree": "51c45fbcf5514805f5bef6c3ae0386d38c3c0bce", "parents": [ "c0e1c4b2ec9d575e01e1e2733c6d6a2efaa226d0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Apr 18 20:50:32 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "Makefile: Turn x86-arch comments into `if`\n\nActually check what the comments suggest. Supposed to fix non-x86 on\nNetBSD and OpenBSD.\n\nChange-Id: I440919c12e54ca4371e21bc8d1b5ab64692fb4b8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52486\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70928\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c0e1c4b2ec9d575e01e1e2733c6d6a2efaa226d0", "tree": "32472efdd3255fdcafc3567be9e35f8096592df8", "parents": [ "e49c220fd06da92621ec9e59f902698bf96b7ebe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 13 21:55:22 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "Makefile: Use pciutils/pci.h only for older NetBSD packages\n\nFixes building on newer NetBSD.\n\nChange-Id: Ie049e485fa25f5da6a372e8ddf87783dd909c3fa\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70927\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e49c220fd06da92621ec9e59f902698bf96b7ebe", "tree": "2d9953bd9d2d278e3174951bd3be5d449a5b004f", "parents": [ "3ddd6034be8904b0c3ebf377cfac89efa563516f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:31:39 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "manibuilder: Update default tags, based on 1.2.x\n\nChange-Id: I7525e8cd3f97ce1c065df060e50ed63f824d8767\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70918\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ddd6034be8904b0c3ebf377cfac89efa563516f", "tree": "7758de0d11c5e00e34d4f25fe2c38d42ea3703f1", "parents": [ "76afdacfb72b7c713c738dedb3f56eb004d883fe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:23:22 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "manibuilder/anita: Move ARGS right before their usage\n\nThis makes it easier for docker to re-use image artifacts, e.g. the\nDebian installation part can be shared among all anita images now.\n\nChange-Id: I9d04c477b89b8e09b11e73c60e7a6cc03437d0ea\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70917\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "76afdacfb72b7c713c738dedb3f56eb004d883fe", "tree": "591e132403c8affa037293a983368e5f07fbad4c", "parents": [ "ea88f2196b8a550daa2e7332cdb854265dea3d3a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:22:19 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "manibuilder/anita: Install pkg-config\n\nChange-Id: Ia8153f7f241dd5f34904a3ea23bbd30f1f980e55\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70916\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ea88f2196b8a550daa2e7332cdb854265dea3d3a", "tree": "b4adc3d95ecea703661ac0a0b0b89e021f51cebe", "parents": [ "48b1fde6b91f211d22a45ef73e36f6d3b1359ef7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:19:36 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:31 2022 +0100" }, "message": "manibuilder/anita: Use QEMU\u0027s -drive option over -hdb\n\nCurrent QEMU wants us to specify the `raw` format explicitly and\nlimits write access otherwise. So use the more elaborate `-drive`\nsyntax.\n\nChange-Id: If5f74592736ec4e0ef971a9a55bbdeb534358dd4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70915\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48b1fde6b91f211d22a45ef73e36f6d3b1359ef7", "tree": "dc086c8f3a6fbf1b54c07b1a3005a424aac39c27", "parents": [ "d4fbbb48bc7c94b59f9065f942de567cb95c5e0a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:15:27 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:31 2022 +0100" }, "message": "manibuilder/anita: Enable KVM when running on x86_64\n\nThis requires us to use privileged containers. Although, the QEMU\ninside should still provide enough encapsulation, we might want to\ndisable this in automated environments.\n\nChange-Id: I767287649511b46cd25125bcbceea8a0446fc76b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70914\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d4fbbb48bc7c94b59f9065f942de567cb95c5e0a", "tree": "351f86ebad280d85913bc21a103c02006372d798", "parents": [ "725a19e090637c576a80901bfc7283ac268e6c84" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:02:57 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:31 2022 +0100" }, "message": "manibuilder: Let build tests fail with the original error code\n\nWe can still run all tests with `make -k`.\n\nChange-Id: Ib59b8863186e5f7ecbaa2aa65cdbd51913dcf8e7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70913\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "725a19e090637c576a80901bfc7283ac268e6c84", "tree": "48cc87a1bfd5a7cfdbb944b6d17822797df27642", "parents": [ "fb9c18a7aafb2f71b49f004f43800cf213ccb6cd" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 00:01:04 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Adapt TEST_REMOTE and TEST_REVISION defaults\n\nIf ${TEST_LOCAL} is set, adapt the default remote and revision\naccordingly. Now this variable is all that is needed to test\na local flashrom commit, e.g.\n\n $ make alpine:amd64-v3.7 TEST_LOCAL\u003d~/flashrom\n\nChange-Id: I435beb81fd05db25fa6b0a7b517d4c8b9b57ceea\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70912\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "fb9c18a7aafb2f71b49f004f43800cf213ccb6cd", "tree": "823e26022ad7981d5ab6d4b36110cd8c3d97edf5", "parents": [ "bfe6484b3bb66fcbfc986ec9bc43155a8c8ea61b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:59:19 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Add service container with local Git access\n\nAdd a new target `local-git` that spawns a service container with a\nlocal Git daemon. The variable ${TEST_LOCAL} needs to point to the\ndirectory of a local git repository.\n\nChange-Id: I9e465551d3398fdb8d173a0a8fbd169561241a74\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70911\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "bfe6484b3bb66fcbfc986ec9bc43155a8c8ea61b", "tree": "8f4979e8d829f33dc37d368ba9dad39194b75881", "parents": [ "aa359a73420bf8c731f2f9733eb2f146f559825c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:54:24 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Automatically create `manibuilder` network bridge\n\nCreate a network bridge for all manibuilder containers. We\u0027ll add a\nservice container with access to a local Git repository later.\n\nChange-Id: Idb03c21dbd12bef59a2c683e169015e286c04d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70910\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aa359a73420bf8c731f2f9733eb2f146f559825c", "tree": "2cd6f9600d25001f868b6c73f851e2cd8ed21603", "parents": [ "34846e46a08dd743e8419d9e9ade00e3d3da0c5f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:52:46 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Make Git remote overridable\n\nChange-Id: Idfc1272f5a7370d3a183835ddf4052db374d6a26\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70909\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "34846e46a08dd743e8419d9e9ade00e3d3da0c5f", "tree": "bf228bd4dd70b83e1101565f3e6ca338fe980a08", "parents": [ "f4a1b5d2e8c74f4ad24764aca8b7d3ad53c1e176" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:45:38 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "manibuilder: Set $(TEST_REVISION) default in make\n\nChange-Id: I8320110a19c434b6d464d8036cc2a99fff41f63e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70908\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f4a1b5d2e8c74f4ad24764aca8b7d3ad53c1e176", "tree": "7dc5040c99ed99390ef540bdb4770ca673f72370", "parents": [ "c0b52db332ce95ca3227b35b3263c858882e0b5d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 27 14:02:36 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "manibuilder: Add list of 1.2.x targets\n\nWe didn\u0027t maintain a list at the 1.2 release. Maybe didn\u0027t even run\nmanibuilder. Let\u0027s start one with distributions available at the\n1.2 release and those available today.\n\nChange-Id: Ia6266ecfba5e9acb37acc41cc305f2f713de7a24\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70907\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c0b52db332ce95ca3227b35b3263c858882e0b5d", "tree": "945d00d92a9a9056e1a5f9927fca4647cb0644b6", "parents": [ "7cb43957c5fe405cd82584f0a54428f2d2d286ff" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 15 12:42:32 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "Import manibuilder from flashrom master\n\nReferences to the upstream repository have been changed to\n`flashrom-stable.git`. The directory `flashrom` is kept,\nthough, so existing containers can be used for both projects.\n\nChange-Id: I8ba148e30602e8e03e3858f7c1eb6789230654d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70906\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7cb43957c5fe405cd82584f0a54428f2d2d286ff", "tree": "9981905ba97c0509e8686782855d97cffe77d80e", "parents": [ "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Mar 16 20:40:42 2022 +0530" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Sun Oct 30 09:43:35 2022 +0000" }, "message": "ichspi: Unify timeouts across all SPI operations to 30s\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\n`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument\nin favor of a fixed timeout of `30 seconds` for any given SPI operation\nas recommended by the SPI programming guide.\n\nDocument: Alder Lake-P Client Platform SPI Programming Guide\n Rev 1.30 (supporting document for multi-master accessing the\n SPI Flash device.)\n\nRefer to below section to understand the problem in more detail and SPI\noperation timeout recommendation from Intel in multi-master\nscenarios.\n\nOn Intel Chipsets that support multi-mastering access of the SPI flash\nmay run into a timeout failure when the operation initiated from a\nsingle master just follows the SPI operational timeout recommendation\nas per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR\nspecification, table 9.7).\n\nIn the multi-master SPI accessing scenario using hardware sequencing\noperation, it\u0027s impossible to know the actual status of the SPI bus\nprior to individual master starting the operation (SPI Cycle In Progress\na.k.a SCIP bit represents the status of SPI operation on individual\nmaster).\n\nThus, any SPI operation triggered in multi-master environment might need\nto account a worst case scenario where the most time consuming operation\nmight have occupied the SPI bus from a master and an operation initiated\nby another master just timed out.\n\nHere is the timeout calculation for any hardware sequencing operation:\n Worst Case Operational Delay \u003d\n (Maximum Time consumed by a SPI operation + Any marginal\n\t adjustment)\n\n Timeout Recommendation for Hardware Sequencing Operation \u003d\n ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +\n Current Operational latency)\n\nAssume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC,\nGbE and other reserved etc, hence, the Timeout Calculation for SPI\nerase Operation would look like as below:\n\n Maximum Time consumed by a SPI Operation \u003d 5 seconds\n\n Worst Case Operational Delay \u003d 5 seconds\n\n Timeout Recommendation for Hardware Seq Operation \u003d\n 5 seconds * (6 - 1) + 5 seconds \u003d 30 seconds\n\nBUG\u003db:223630977\nTEST\u003dAble to perform read/write/erase operation on PCH 600 series\nchipset (board name: Brya).\n\nOriginal-Signed-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867\nOriginal-Tested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nChange-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68691\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\n" }, { "commit": "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32", "tree": "fbe81e1f039bd7813b2973db04fc2c3ac4f82b1a", "parents": [ "1900e1d5d39d91b762c9a02ef2445868b323ca87" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Jul 22 23:23:28 2022 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:03:11 2022 +0000" }, "message": "Makefile: Fix dependencies for developerbox_spi\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\nThe developerbox_spi programmer depends on bitbang SPI support. Thus,\nfix that.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: Ic0fe589ffdccede0fbf6360c2bebe58a36654f10\nReviewed-on: https://review.coreboot.org/c/flashrom/+/66096\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68064\n" }, { "commit": "1900e1d5d39d91b762c9a02ef2445868b323ca87", "tree": "a95c01537af1a6a2a643f696c5e33df886471619", "parents": [ "87aa19314523d1cffdef57fbdf65d8328824026c" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 02 12:42:23 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:00:37 2022 +0000" }, "message": "Replace freenode references\n\nThe flashrom project no longer uses freenode. To avoid having outdated\nman pages in the future, the contact methods are now listed in the wiki.\n\nChange-Id: I75e8f43c50dc4c3feede0250334a877cdaac8103\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/56031\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68063\n" }, { "commit": "87aa19314523d1cffdef57fbdf65d8328824026c", "tree": "bee9fc52eca9b27172ae3d060701a4cbcafc1d06", "parents": [ "89cc73bda5fd181e9fcab2eadf5f80759379c1b3" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 02 12:48:10 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:00:32 2022 +0000" }, "message": "print_wiki.c: Update mailing list reference\n\nChange-Id: I5c67b5b3be2f306132d8565539bbf10477222026\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/56030\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68062\n" }, { "commit": "89cc73bda5fd181e9fcab2eadf5f80759379c1b3", "tree": "b1ddf34a7d13413887257ae0347109a336c54ce5", "parents": [ "380090faffcbe3cbdc20af9c75979fdafaa5a834" ], "author": { "name": "Pyry Kontio", "email": "pyry.kontio@drasa.eu", "time": "Mon Jul 06 12:57:35 2020 +0900" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:35:30 2022 +0000" }, "message": "Makefile: Fix building on AArch64 NixOS\n\nThe parsing of the output of archtest.c produced an unexpected\nvalue on AArch64 NixOS. For example, the make variable ARCH was set to:\n\n```\nbit outside of fd_set selected\narm\n```\n\nThis made the arch and OS checks fail.\n\nThis commit simplifies the parsing, making it more robust.\n\nThe C files archtest.c, endiantest.c and os.h used to set the\nTARGET_OS, ARCH and ENDIAN variables, respectively, output\nthe result of the test as the final line, so just extracting\nthe final line and removing double quoting is enough.\n\nThis commit also fixes a bug with debug_shell lacking escaping\nsingle quotes, which prevented using the single quote in the\ndebug_shell calls. It used to work by accident before this fix;\nthe line in the call happened to contain a balanced pair of double\nquotes and lacked other characters that needed escaping, which\ndidn\u0027t break the debug_shell, but this was accidental and very\nbrittle.\n\nSigned-off-by: Pyry Kontio \u003cpyry.kontio@drasa.eu\u003e\nChange-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510\nReviewed-on: https://review.coreboot.org/c/flashrom/+/43140\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67902\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "380090faffcbe3cbdc20af9c75979fdafaa5a834", "tree": "d6dac3cefcc91f4451b73b0bf8da60473ca6c34c", "parents": [ "298ac33bc495bba371629951dce8ea67e5e0ca78" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 01:45:11 2022 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:21 2022 +0000" }, "message": "pcidev: Always fetch ident info\n\nAs discovered earlier[1], the `vendor_id` and `device_id` fields are not\nalways automatically set. However, we use these fields throughout flash-\nrom. To not lose track when we actually fetched them, let\u0027s always call\npci_fill_info(PCI_FILL_IDENT) before returning a `pci_dev` handle.\n\n[1] Commit ca2e3bce0 (pcidev.c: populate IDs with pci_fill_info())\n\nBackported to older versions where pcidev handling was much more\nscattered.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iae2511178bec44343cbe902722fdca9eda036059\nTicket: https://ticket.coreboot.org/issues/367\nReviewed-on: https://review.coreboot.org/c/flashrom/+/64573\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67877\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "298ac33bc495bba371629951dce8ea67e5e0ca78", "tree": "9387c285a1af5bc95ca9c698b3d98f05f1f141df", "parents": [ "245e540ecbe8e0daa8db747dcc6d470fa6f79938" ], "author": { "name": "Daniel Verkamp", "email": "dverkamp@chromium.org", "time": "Mon Oct 12 12:55:56 2020 -0700" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:13 2022 +0000" }, "message": "pcidev.c: populate IDs with pci_fill_info()\n\nWith pciutils 3.7.0, flashrom is unable to match any PCI devices by\nvendor/device ID because the vendor_id and device_id fields of struct\npci_dev are not filled in.\n\nCall pci_fill_info() to request these identifiers before trying to match\nthem against the supported device list.\n\nThe pciutils ChangeLog for 3.7.0 mentions that the documentation and\nback-end behavior for pci_fill_info() was updated; it seems that a call\nto pci_fill_info() was always intended to be required, but some backends\n(such as the sysfs one used on Linux) would fill the identifier fields\neven when not requested by the user. The pci_fill_info() function and\nthe PCI_FILL_IDENT flag have been available for all versions of pciutils\nsince at least 2.0 from 1999, so it should be safe to add without any\nversion checks.\n\nWith this change, reading/writing a nicintel_spi boot ROM is successful.\n\nSigned-off-by: Daniel Verkamp \u003cdverkamp@chromium.org\u003e\nChange-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46310\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67876\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "245e540ecbe8e0daa8db747dcc6d470fa6f79938", "tree": "b8bfd72696a54c0adb7f3e3d06afaedcf9b36c48", "parents": [ "04fce478cb9aba339439d1955c3355a075445ec1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 06 00:21:52 2022 +0100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:09 2022 +0000" }, "message": "dmi: Correctly check for ERROR_PTR\n\nFor the physmap*() functions, NULL is considered valid return value.\nFixes a segmentation fault when DMI tables can\u0027t be mapped.\n\nTested on intel/eblake board with broken coreboot.\n\nChange-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/62611\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67875\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "04fce478cb9aba339439d1955c3355a075445ec1", "tree": "8c6342749297f623f282aea64c84082dbb8835e2", "parents": [ "96cc5d3ea84e7e7e3a6029cf728cef061ccae45f" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Jan 11 18:26:48 2022 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:03 2022 +0000" }, "message": "linux_mtd: check ioctl() return value properly\n\nMake the linux_mtd driver treat any negative return value from the\nMEMERASE ioctl as an error. Previously it only treated -1 as an error.\n\nBUG\u003db:213561594,b:210973586,b:182223106\nBRANCH\u003dnone\nTEST\u003dbuilds\n\nChange-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/60996\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67874\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "96cc5d3ea84e7e7e3a6029cf728cef061ccae45f", "tree": "3072b945e3be60c09c945c47adf5fb47fcdacc7b", "parents": [ "a8c0b68199c5f76073a8b9c2ecf2d3694086591e" ], "author": { "name": "Michael Niewöhner", "email": "foss@mniewoehner.de", "time": "Tue Sep 21 17:37:32 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:56 2022 +0000" }, "message": "flashrom.8: add missing entry for `--flash-contents`\n\nChange-Id: I64a8200a86329bd26a2069c5dc39430de9f8ba09\nSigned-off-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/57807\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67873\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "a8c0b68199c5f76073a8b9c2ecf2d3694086591e", "tree": "2e77e4b73a0b42227f08ad5879750498eb84aba4", "parents": [ "595c5d017402fb20bef14e4d2c399251470c95fe" ], "author": { "name": "Marc Schink", "email": "dev@zapb.de", "time": "Sat Aug 22 11:29:22 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:49 2022 +0000" }, "message": "jlink_spi: Reduce transfer size\n\nThe maximum transfer size is too large for some devices and\nresults in an USB timeout.\n\nChange-Id: If2c00b1524ec56740bdfe290096c3546cf375d73\nSigned-off-by: Marc Schink \u003cdev@zapb.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48379\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67872\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "595c5d017402fb20bef14e4d2c399251470c95fe", "tree": "49b5163834504c40ffdb373be4360426ba99204e", "parents": [ "5feb8cdb6ff497e45cda73839dacafc240bf83bb" ], "author": { "name": "Douglas Anderson", "email": "dianders@chromium.org", "time": "Fri Jan 29 16:35:24 2021 -0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:43 2022 +0000" }, "message": "linux_mtd: Disable buffering on the mtd device\n\nWe open the device node for the MTD device with this:\n dev_fp \u003d fopen(dev_path, \"r+\")\n\nIn C fopen() is allowed to provide _buffered_ access to the file.\nThat means that the standard library is allowed to read ahead and/or\nreturn cached data. That\u0027s really not what we want for something like\nthis. Let\u0027s turn it off.\n\nThis fixes a problem where flashrom would sometimes fail to \"verify\"\nthat it erased the flash. The error message would look something like\nthis:\n\nErasing and writing flash chip... FAILED at 0x0000e220! Expected\u003d0xff, Found\u003d0xe9, failed byte count from 0x0000e200-0x0000e2ff: 0xdc\n failed byte count from 0x0000e000-0x0000efff: 0xffffffff\n ERASE_FAILED\nFAILED!\nUh oh. Erase/write failed. Checking if anything changed.\n\nAfter the failure I could read the flash device with a new invocation\nof flashrom and I would see that, indeed, the erase had worked.\n\nTracing in the kernel showed that when the failure happened we saw a\npattern that looked like this:\n* Read 0x0b00 bytes starting at 0x0000d000\n* Read 0x1000 bytes starting at 0x0000db00\n* Erase 0x1000 bytes starting at 0x0000e000\n\n...and then there was _not_ a read after the erase. It can be assumed\nthat, since userspace had already read 0xdb00 - 0xeaff that it was\nlooking at old buffered data after the erase.\n\nSigned-off-by: Douglas Anderson \u003cdianders@chromium.org\u003e\nChange-Id: I989afd83a33013b2756a0090d6b08245613215c6\nReviewed-on: https://review.coreboot.org/c/flashrom/+/50155\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67871\nReviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "5feb8cdb6ff497e45cda73839dacafc240bf83bb", "tree": "fd3c99ccf093d56e957068e763d9c83d774ca2c7", "parents": [ "b822ce85aaed8c6dfa8f5e1e2354db5c9db50509" ], "author": { "name": "Xiang Wang", "email": "merle@hardenedlinux.org", "time": "Wed Jan 20 17:31:19 2021 +0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:38 2022 +0000" }, "message": "helpers.c: Fix undefined behavior in strndup()\n\nUsing strlen() or strdup() inside strndup() is problematic: if the\ninput string is not null-terminated, these functions can read past the\nend of the buffer, which triggers undefined behavior. Rewrite the\nfunction to never read past the provided `maxlen` bound.\n\nChange-Id: Id34127024085879228626fbad59af03268ec5255\nSigned-off-by: Xiang Wang \u003cmerle@hardenedliux.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/49741\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67870\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b822ce85aaed8c6dfa8f5e1e2354db5c9db50509", "tree": "2c7f7e02cb143b306995128b1f52e5ee6b7a4f88", "parents": [ "2e3e10669d719545968ddec3b44b8a9363f4b432" ], "author": { "name": "Medicine Yeh", "email": "medicinehy@gmail.com", "time": "Thu Dec 17 15:40:42 2020 +0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:31 2022 +0000" }, "message": "dediprog: Fix segmentation fault on no device found\n\nlibusb_exit() call is done by dediprog_open() under the\nret \u003d\u003d 1 condition. Removing this line has no impact on\nany flow and side effect of the program.\n\nChange-Id: I38b3f3ee3f9d46845df1404791f4a4782320aa7c\nSigned-off-by: Medicine Yeh \u003cmedicinehy@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48688\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67869\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "2e3e10669d719545968ddec3b44b8a9363f4b432", "tree": "95f7807b9ec68fdc9d21590fc7c174ee0f391fca", "parents": [ "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Dec 02 13:17:46 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:24 2022 +0000" }, "message": "chipset_enable.c: Validate physmap() return rcrb value\n\nValidate the physical mapping in enable_flash_silvermont().\n\nChange-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67868\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d", "tree": "5541efefb64efc6611a315e12936608c37803c3c", "parents": [ "d92dd50bcac6b2d0dfffa9f983712f7400990f3d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Thu Oct 15 19:19:05 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:15 2022 +0000" }, "message": "chipset_enable.c: check return value from rphysmap() call\n\nPort from the ChromiumOS fork of flashrom.\n\nChange-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46444\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67867\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "d92dd50bcac6b2d0dfffa9f983712f7400990f3d", "tree": "957fbc3c081425b31aeba3fb9c44451397323e94", "parents": [ "4af3609828a980bad9ecaf99365f99305d4180f8" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Oct 19 14:20:36 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:10 2022 +0000" }, "message": "it87spi.c: Prevent use-after-free bug\n\nThe memory for the `param` string is aliased by `dualbiosindex_suffix`.\nMoreover, `errno` could have been modified by the call to `free()`.\nTherefore, only free the former when there are no more uses of either.\n\nChange-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67866\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "4af3609828a980bad9ecaf99365f99305d4180f8", "tree": "2fca2548be1d41c2e48164e3c4f2683ac1862837", "parents": [ "355a1df1837e36075f2b6e59ec1f7db1db95f02a" ], "author": { "name": "Yuji Sasaki", "email": "sasakiy@chromium.org", "time": "Fri Mar 22 10:59:50 2019 -0700" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:05 2022 +0000" }, "message": "spi25: Debug flashrom crash when Write Protect is ON\n\nWhen hardware write protect is applied, flashrom crashed and\ngenerate coredump. spi_disable_blockprotect_generic() calls\nflash-\u003echip-\u003eprintlock() method when disable was failed,\nbut this method is optional, can be NULL depends on type of\nflashrom chip. NULL pointer check before call is added to\navoid crash.\n\nBRANCH\u003dnone\nBUG\u003db:129083894\nTEST\u003dRun on Mistral P2\n(On CR50 console, run \"wp disable\")\nflashrom --wp-range 0 0x400000\nflashrom --wp-enable\n(On CR50 console, run \"wp enable\")\nflashrom -r /tmp/test.bin\nVerify \"Block protection could not be disabled!\" is shown,\nbut flash read completes.\nSigned-off-by: Yuji Sasaki \u003csasakiy@chromium.org\u003e\n\nChange-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e\nReviewed-on: https://chromium-review.googlesource.com/1535140\nCommit-Ready: ChromeOS CL Exonerator Bot \u003cchromiumos-cl-exonerator@appspot.gserviceaccount.com\u003e\nTested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nReviewed-by: SANTHOSH JANARDHANA HASSAN \u003csahassan@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40468\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67865\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "355a1df1837e36075f2b6e59ec1f7db1db95f02a", "tree": "c8293d39eff36cc6929242ffe642ba8f4e2a13bb", "parents": [ "399a4dd721a64a1d22e2f8028cc39d6496515ed6" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Thu Apr 23 09:36:12 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:00 2022 +0000" }, "message": "stlinkv3_spi: Avoid division by zero\n\nChange-Id: I08c0612f3fea59add9bde2fb3cc5c4b5c3756516\nFound-by: Coverity Scan #1412744\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40653\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67864\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "399a4dd721a64a1d22e2f8028cc39d6496515ed6", "tree": "6a40ff5ca048148294b209d8cb99ab9558fdc44f", "parents": [ "b57f48f77f367c43cd83878d92aa55de151c0798" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 15 12:59:42 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:53 2022 +0000" }, "message": "chipset_enable.c: Disable SPI on ICH7 if booted from LPC\n\nCommit 92d6a86 (\"Refactor Intel Chipset Enables\") eliminated a check\nto disable SPI when ICH7 has booted from LPC, as the hardware does not\nsupport it. Therefore, when flashrom probes the SPI bus, it times out\nwaiting for the hardware to react, for each and every SPI flash chip.\nThis results in very long delays and countless instances of the error:\n\n Error: SCIP never cleared!\n\nTo prevent this, bring back part of the lost check. Probing for LPC and\nFWH when booted from SPI does not seem to cause any problems on desktop\nmainboards with ICH7, so don\u0027t disable LPC nor FWH if that is the case.\n\nTested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.\n\nChange-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40401\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67863\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b57f48f77f367c43cd83878d92aa55de151c0798", "tree": "d2b42aa861392afb20d841ec86a1c860abd90a05", "parents": [ "b428c319ed629bef50e7e154c472635f68ea8edc" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Sat May 02 16:07:11 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:47 2022 +0000" }, "message": "spi95: Check for success before using send_command\u0027s returned data\n\nIf the transfer failed, the data might be invalid.\n\nChange-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880\nFound-By: Coverity Scan #1405870\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40970\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67862\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" } ], "next": "b428c319ed629bef50e7e154c472635f68ea8edc" }