)]}' { "log": [ { "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0", "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df", "parents": [ "0167522794a2e66f00248347122c1bb8ce3b001d" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:32:25 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0167522794a2e66f00248347122c1bb8ce3b001d", "tree": "ac01ed9312b2946bdcdbe1abf1078b69f6117183", "parents": [ "236a38cc46ac810d0be679402bb21e83aebcb8b9" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:30:41 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "spi25_statusreg: make register read/write functions generic\n\nThis patch adds new spi_{read,write}_register() functions that take the\nsource/destination register as an argument. Currently they can only\naccess SR1, support for other registers will be added in another patch.\n\nSince we\u0027re refactoring things, this commit also makes\nspi_read_register() return an error code, making it possible to identify\nerror conditions that spi_read_status_register() concealed.\n\nThis also removes the initial 100ms delay between writing a register and\nthe first attempt to check the chip\u0027s status. An initial delay was added\nto avoid needing to read the status register multiple times, but that is\nunlikely to cause problems on modern flash chips.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70964\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "236a38cc46ac810d0be679402bb21e83aebcb8b9", "tree": "a460050e0a50e0cb37383709b1abfdbcbc7bbcbc", "parents": [ "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Fri Nov 05 11:48:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips: Add W25Q64JV\n\nI have successfully tested it with FT2232H-programmer.\n\nChange-Id: Ia9a32146b225eca66e9a6bfef45be5f2b24aef46\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58971\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70963\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6", "tree": "daf3ce9e6a6aa471eeeea5296904ff369d448f65", "parents": [ "571f6ad31f0047fdbf613448e04d9c7138ade662" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Sep 29 09:28:07 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips.c: mark EN25F10 as TEST_OK_PREW\n\nAs reported by Wolf Dieter Brandt in his e-mail from 09.Aug.2021.\n\nChange-Id: I0c19f84780e7fa3699fd706f8e105fc5937ba8bf\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58031\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70962\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "571f6ad31f0047fdbf613448e04d9c7138ade662", "tree": "a0926521de7d240eab415da54dc70ffa5712fd5a", "parents": [ "981a344f65c2125b7aba72c0a61760f33c508ec2" ], "author": { "name": "Tao Xia", "email": "xiatao5@huaqin.corp-partner.google.com", "time": "Wed Jul 21 16:41:53 2021 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12833F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nSigned-off-by: Tao Xia \u003cxiatao5@huaqin.corp-partner.google.com\u003e\nChange-Id: I14ab7e04f5209d2bcf34b0d2de9da2c01bf32d00\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56546\nOriginal-Reviewed-by: Weimin Wu \u003cwuweimin@huaqin.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70961\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "981a344f65c2125b7aba72c0a61760f33c508ec2", "tree": "79e38d75327c731023c3e4b5f2729eb5695b2484", "parents": [ "2649dde2be69f01f4c5bee4a7d21223bd25e322c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Tue Jun 22 11:16:55 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips.c: Add \u0027GD25LQ128E\u0027 to match C and D variants\n\nAs defined by gigadevice. C, D and E are all meant to\nbe the same.\n\nChange-Id: I3bef9386a185a0e8c54c125af5509b63540995aa\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55742\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70960\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2649dde2be69f01f4c5bee4a7d21223bd25e322c", "tree": "2232b470f8921c5b5cb9cddf8864536c5e9eec26", "parents": [ "3ba8315e134c3fc0f29b538abb22fd9e85a2361f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 03 13:47:39 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12873F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nChange-Id: I59c8067f15b5ceac5a2e2f8fe93431a465f17e23\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56054\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70959\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ba8315e134c3fc0f29b538abb22fd9e85a2361f", "tree": "315ee58cda0d2d9de74142d442d43bf31ba500e2", "parents": [ "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Tue Jun 08 10:52:19 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add support for Macronix MX66L1G45G\n\nTested on Dediprog SF600: Reading and writing works.\n\nChange-Id: I554e828c97d9ec77b08489573a34e176599d2518\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55353\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70958\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8", "tree": "67f1c17c4dd4fd6ab500a78c5aee1ce7db03d5d1", "parents": [ "5fa050515d2fff9679d38803a8594e4a8c5a407a" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Mon Feb 15 13:16:57 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: Mark MT25QL256 as tested\n\nAs mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020.\n\nChange-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70957\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5fa050515d2fff9679d38803a8594e4a8c5a407a", "tree": "59ba8caf8f49cbec055d2cb0b47052d3e54c65ab", "parents": [ "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri May 14 15:26:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips: change chip name from \u0027W25Q64JW\u0027 to \u0027W25Q64JW...M\u0027\n\nAccording to the W25Q64JW datasheet rev. E, only devices ending with the\nletter \u0027M\u0027 have a device ID of 8017h. There are other variants with\ndifferent device IDs. This patch makes the \u0027W25Q64JW...M\u0027 definition\nconsistent with the \u0027W25Q32JW...M\u0027 definition.\n\nThe device ID macro defined in flashchips.h has also been renamed from\nWINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.\n\nChange-Id: Ib0dc914da286a191d22e666332b1063b88db4251\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70956\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0", "tree": "0d12cf62cf976d9a3378fa48a245478c1caffab1", "parents": [ "b6683e0a5586537269524eaadee5619d1dec410b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Sat May 08 17:31:23 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: add support for W25Q32JW...M\n\nThe chip was added to cros flashrom in\n`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.\nQuoting from the commit message:\n\n\u003e We have varied the correct chip name is reported as well as\n\u003e write and read 16MBytes of random data and verified the checksum\u0027s match.\n\u003e Further, --wp-list appears to report the correct ranges.\n\u003e\n\u003e BUG\u003db:130199963\n\u003e BRANCH\u003dnone\n\u003e TEST\u003dRan flashrom with a Dediprog SF100, RW random data and checksum matched.\n\nChange-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70955\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b6683e0a5586537269524eaadee5619d1dec410b", "tree": "b2bdb49813421373adc4a5f8ede57b920b89e05c", "parents": [ "6e69e2b5f78104e5b54e83be889ae887702309ff" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:04:29 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add MX25L3233F\n\nOnly mattering difference to the MX25L3273E seems to be the voltage\nrange (starting at 2.65V instead of 2.7V). I don\u0027t think that would\njustify yet another entry.\n\nChange-Id: I73402dddedf360ab84caed4c019efe27b477d4c2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52570\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70954\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6e69e2b5f78104e5b54e83be889ae887702309ff", "tree": "78ea64917e28700796c57bba0d0f8602145360d0", "parents": [ "475a7eed6d6589c8a1e5267a1f4be3500fb245c4" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:03:13 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Correct OTP comment for MX25L3273E\n\nThe datasheet says 4K bits, maybe just a copy-paste error.\n\nChange-Id: I42b10aa09c969e5c5e7102b1e8ab496f52bd27bb\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52569\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70953\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "475a7eed6d6589c8a1e5267a1f4be3500fb245c4", "tree": "6a90aa1167acc44f0ddf92f0124d3eaa220bef33", "parents": [ "1ebda787f1c6bec8e63d06a01ba921c49c4e2187" ], "author": { "name": "Christian Kudera", "email": "coreboot@kudera.at", "time": "Tue Apr 20 22:50:01 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add support for Boya/BoHong Microelectronics B_25D16A\n\nRead tested on CH341A\n\nChange-Id: I25b776204affda94cc7e753e7671ef9d3d9508f1\nSigned-off-by: Christian Kudera \u003ccoreboot@kudera.at\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52555\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70952\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1ebda787f1c6bec8e63d06a01ba921c49c4e2187", "tree": "193cb9fe46cd8ca4887496c6fc63e6cc7e8fe7cc", "parents": [ "148254be920530d54d76d742b30a3fb61689cf07" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Apr 20 21:39:11 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips: Adapt IDs for Boya Microelectronics\n\nLooks like BoHong Microelectronics has the same vendor ID and makes very\nsimilar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have\nthe same specifications and their datasheets are mostly identical.\n\nChange-Id: I8d6951797daeeecca6af200c995297c0394adefd\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70951\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "148254be920530d54d76d742b30a3fb61689cf07", "tree": "ff3580e4dcd6726dc1dd97ce6fa2d01d5f1135f6", "parents": [ "e64ef6d72741c39cb9a5e866d9952f2b14366996" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:21:10 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark MX25U25635F as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit 419e32ae457cc36b03757b89471a7ce3770e9611`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dTested writes using Servo\n\nChange-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70950\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e64ef6d72741c39cb9a5e866d9952f2b14366996", "tree": "9ae607243716dcdab4d39e4e282d89412bf020af", "parents": [ "df889fa924154ffd1265971b05002c28651b8e83" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:15:40 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark GD25Q256D as TESTED_OK_PREW\n\nTested read/write/erase/verify with FT232H programmer.\n\nChange-Id: Ia7d52b69eb571113fe3c60ec9a139ee67180509b\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51735\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70949\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "df889fa924154ffd1265971b05002c28651b8e83", "tree": "068e75775d2d757e3cf1a264aa8e7f4d5c069c22", "parents": [ "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:10:45 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: mark EN25S64 as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dread and write BIOS on glimmer with Eon device.\n\nChange-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70948\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5", "tree": "e65d194cc42f67ab9caf8bcc6dbf400d5546b6f5", "parents": [ "c205487aede60d9926541159631a0e360abdc82d" ], "author": { "name": "Tim Chen", "email": "tim-chen@quanta.corp-partner.google.com", "time": "Mon Jul 06 14:59:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "CHROMIUM: flashrom: update .tested field for EN25QH128\n\nupdate .tested field from TEST_UNTESTED to TEST_OK_PREW\n\nTested: Flash Duffy bios\n pass on running `flashrom_tester /usr/sbin/flashrom host`\n\nOriginal-Change-Id: I9467588988c2cab0987737c53ace0832144ef169\nOriginal-Signed-off-by: Tim Chen \u003ctim-chen@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Commit-Queue: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n(cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff)\n\nChange-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70947\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c205487aede60d9926541159631a0e360abdc82d", "tree": "417b46539f418ddfc293d1041ad762d54207dec5", "parents": [ "813a7e2eef268f2e63b2cac2e9b60a2ed2365945" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 15 18:57:32 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips: Mark Macronix MX25L1635D as tested\n\nTested probe, read, erase and write with a FTDI FT2232H successfully.\n\nChange-Id: I7421b7e36e687ea2ffff494c00157976db73ac43\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49489\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70945\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "813a7e2eef268f2e63b2cac2e9b60a2ed2365945", "tree": "89eba409e95982a9507434721351671c52df042d", "parents": [ "721a4f390410debb77487562c8a47a20edb4d7f2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Jan 08 08:48:17 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW\n\nI have successfully probed/read/erased/written a GD25LQ128D, so marking\nthis entry as tested.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70944\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "721a4f390410debb77487562c8a47a20edb4d7f2", "tree": "cf842e10410c39de9bf712d547cdd23f40a5a19b", "parents": [ "ef88423928abf61fa894d2798a9d265fd001cd26" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Dec 14 07:39:02 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "spi25_statusreg.c: restore SR contents at flashrom exit\n\nregister_chip_restore() provides a general mechanism for restoring a chip\u0027s state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR\u0027s sector layout bits so that entire flash accessible.\n\nThis patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash.\n\nImported from cros flashrom at `b170dd4e1d5c33b169c5`\n\nChange-Id: If2f0e73518d40519b7569f627c90a34c364df47c\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70943\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ef88423928abf61fa894d2798a9d265fd001cd26", "tree": "8ceb8aa058cf63a0f39e4a9c8114733b0914af1c", "parents": [ "e0e8b2b8f99030962994b876353e3a69cb68af80" ], "author": { "name": "luke he", "email": "sixuerain@qq.com", "time": "Mon Dec 28 18:22:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips.c: Add support for XMC new SPI flash types\n\nAdds initial support for the follow SPI flash chips:\n\n XM25QU64C\n XM25QU128C\n XM25QU256C\n XM25QH64C\n XM25QH128C\n XM25QH256C\n\nflashrom-stable:\n* Added missing 4BA flags / erasers\n* Dropped wrong, superfluous comments\n* Sorted\n\nSigned-off-by: Luke He \u003csixuerain@qq.com\u003e\nChange-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70942\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e0e8b2b8f99030962994b876353e3a69cb68af80", "tree": "ff9e47bf8eba1954ad347a9ea8bab70bb7af2306", "parents": [ "4ad486465ccceedce372c498ad19ac84edbc0078" ], "author": { "name": "Zoltan HERPAI", "email": "wigyori@uid0.hu", "time": "Sat Aug 08 16:04:34 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips: Mark Intel 25F640S33B8 as TESTED_PREW\n\nTested with ch341a_spi from an Atheros AP81 reference board.\n\nChange-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef\nSigned-off-by: Zoltan HERPAI \u003cwigyori@uid0.hu\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44342\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70941\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4ad486465ccceedce372c498ad19ac84edbc0078", "tree": "b278a2499ed1ac3101b4e74f48a8a622640c15d3", "parents": [ "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Nov 05 13:54:27 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashrom.c: implement chip restore callback registration\n\nAllows drivers to register a callback function to reset the\nchip state once programming has finished. This is used by\nthe s25f driver added in a later patch, which needs to change\nthe chip\u0027s sector layout to be able to write to the entire flash.\n\nAdapted from cros flashrom at\n`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.\n\nChange-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70940\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e", "tree": "bb4d94a94cf593bae5592de6bdee9afe61eafeae", "parents": [ "0cf3e12fd5e420115551062a225b44e1782ba629" ], "author": { "name": "Jack Olsen", "email": "omegasec@tutanota.com", "time": "Sat Aug 08 21:12:13 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Boya Microelectronics BY25Q128AS\n\nTested on Buspirate.\n\nSigned-off-by: Jack Olsen \u003comegasec@tutanota.com\u003e\nChange-Id: I881ba86cfaa82e43c73360135d47c74d896cc191\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70939\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cf3e12fd5e420115551062a225b44e1782ba629", "tree": "917b704ffedd00099c9958126fe8698edc4ba89f", "parents": [ "3153260aecbec2e8719f8b093c0f17ec860e4b2c" ], "author": { "name": "Jakob Petersson", "email": "github@jakobpetersson.se", "time": "Mon Feb 18 01:55:43 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Fudan SPI flash chips\n\nflashrom-stable: Found additional info on Github:\n\nCode is taken from existing PATCH by Stefan Tauner stefan.tauner@alumni.tuwien.ac.at\nhttps://mail.coreboot.org/pipermail/flashrom/2016-June/014672.html\n\nWith the only change being the Manufacture ID being changed\nfrom 0x04h to 0xA1h.\n\nI have only tested it with FM25F005 and it seems to work.\n\nSigned-off-by: Jakob Petersson \u003cgithub@jakobpetersson.se\u003e\nChange-Id: I8045ecb8778fd6111fcccc075e69928f131a926a\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/46513\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70938\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3153260aecbec2e8719f8b093c0f17ec860e4b2c", "tree": "3edf5db4440c03b321b3ce5f74816c488f08bc1e", "parents": [ "7e6f3a7ccb8fb5206ceaddc9bb0c285f4264cabf" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Aug 16 17:14:56 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add W25Q256JW_DTR\n\nW25Q256JW currently has two variants, the W25Q256JW with device\nID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka\nW25Q256JW-IM) with device ID 0x8019 added by this patch.\n\nWinbond W25Q256-series chips have a few device IDs:\n0x4019: W25Q256FV\n0x6019: W25Q256JW\n0x7019: W25Q256JV\n0x8019: W25Q256JW_DTR\n\nHence we need to be more specific with naming than usual to avoid a\nfalse positive with wildcards.\n\nChange-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386\nOriginal-Reviewed-by: Simon Buhrow\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70937\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e6f3a7ccb8fb5206ceaddc9bb0c285f4264cabf", "tree": "7ded0eda3ea711bab56e644997601a1cc38ef40c", "parents": [ "ebbdc02ee860ee4e3baeecc6a0c220d138499c59" ], "author": { "name": "Steve Markgraf", "email": "steve@steve-m.de", "time": "Mon Jul 13 18:22:56 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add support for Macronix MX25L5121E\n\nTested with ch341a_spi.\n\nChange-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766\nSigned-off-by: Steve Markgraf \u003csteve@steve-m.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43416\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70936\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ebbdc02ee860ee4e3baeecc6a0c220d138499c59", "tree": "23a7947c060e0eddbfb60e6112eb5b5696057913", "parents": [ "0120985bd3ccc5d22906863b21902b29e87bc05b" ], "author": { "name": "Jacob Appelbaum", "email": "jacob@appelbaum.net", "time": "Mon Sep 02 09:10:43 2019 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "Add support for Winbond W25X05CL\n\nThis commit adds support for the Winbond W25X05CL SPI flash chip. The\nWinbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors.\nI have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL\nflash chip using a test clip. Reading, erasing, and writing all function\nas expected.\n\nChange-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc\nSigned-off-by: Jacob Appelbaum \u003cjacob@appelbaum.net\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70935\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0120985bd3ccc5d22906863b21902b29e87bc05b", "tree": "97ac99f76b39e88566e10b0b8e11b6ded21ba3e6", "parents": [ "5eca427ae64519b70d1c4ccfb427305ca9974ba0" ], "author": { "name": "el-coderon", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Apr 29 12:12:53 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add W25Q256.W\n\nNicklas Lennert wrote me via the flashrom mailing list that\nhe successfully ran read, write and verify cmd.\n\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nChange-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70934\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1bbc501f79319cc6c8d839bc44fa55e96afab33a", "tree": "930ed121151a82ddc0e157c3b2c1b50de99a6a77", "parents": [ "5543961c01fe6d6fb1ec7e68b8dcc766d0d272e3" ], "author": { "name": "Scott Chao", "email": "scott.chao@bitland.corp-partner.google.com", "time": "Wed Apr 08 22:10:50 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "flashchips: Add support for Winbond W25Q64JW\n\nTested: flash coreboot on kakadu and get successful result.\n\nChange-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967\nSigned-off-by: Scott Chao \u003cscott.chao@bitland.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nOriginal-Tested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70932\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5543961c01fe6d6fb1ec7e68b8dcc766d0d272e3", "tree": "945ad58063335ccf3b76d7dc02eded147c9b1b7f", "parents": [ "3214f58db8f8cceb40d4faa16130124446cc35fa" ], "author": { "name": "Joel Stanley", "email": "joel@jms.id.au", "time": "Sat Jul 27 19:25:35 2019 +0930" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "flashchips: Add W25Q512JV\n\nhttps://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf\n\nTested with dediprog SF100.\n\nChange-Id: I8d16f0918785795cc49500435a03641b87d706e9\nSigned-off-by: Joel Stanley \u003cjoel@jms.id.au\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595\nOriginal-Reviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70931\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3214f58db8f8cceb40d4faa16130124446cc35fa", "tree": "6b7d14da618a215fc619d786305bfad9387e5163", "parents": [ "f62623cff61d677609fbd92a71a5ad7875ad9b8a" ], "author": { "name": "Dino Li", "email": "Dino.Li@ite.com.tw", "time": "Wed Mar 25 17:39:53 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "flashchips: add support for GigaDevice GD25WQ80E\n\nSupport GD25WQ80E, which is the internal flash of IT81202.\n\nTested: Building flashrom and flashing FW image into IT81202 successfully.\n\nChange-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8\nSigned-off-by: Dino Li \u003cDino.Li@ite.com.tw\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70930\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f62623cff61d677609fbd92a71a5ad7875ad9b8a", "tree": "989cca84ef37d1878dca9b25220766fd2123cb49", "parents": [ "9245b889dde1dba76cd696d5d354ac89b84fca65" ], "author": { "name": "sibradzic", "email": "5964548+sibradzic@users.noreply.github.com", "time": "Sat Mar 14 17:21:34 2020 +0900" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "flashchips: Add Macronix MX25R3235F\n\n32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is\nsimilar to the already-supported MX25R6435F, but the total size is\nhalved.\n\nTested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed\nworking probe, read, erase and write.\n\nFixes: https://github.com/flashrom/flashrom/issues/43\n\nChange-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5\nSigned-off-by: Samir Ibradzic \u003csibradzic@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70929\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9245b889dde1dba76cd696d5d354ac89b84fca65", "tree": "51c45fbcf5514805f5bef6c3ae0386d38c3c0bce", "parents": [ "c0e1c4b2ec9d575e01e1e2733c6d6a2efaa226d0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Apr 18 20:50:32 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "Makefile: Turn x86-arch comments into `if`\n\nActually check what the comments suggest. Supposed to fix non-x86 on\nNetBSD and OpenBSD.\n\nChange-Id: I440919c12e54ca4371e21bc8d1b5ab64692fb4b8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52486\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70928\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c0e1c4b2ec9d575e01e1e2733c6d6a2efaa226d0", "tree": "32472efdd3255fdcafc3567be9e35f8096592df8", "parents": [ "e49c220fd06da92621ec9e59f902698bf96b7ebe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 13 21:55:22 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "Makefile: Use pciutils/pci.h only for older NetBSD packages\n\nFixes building on newer NetBSD.\n\nChange-Id: Ie049e485fa25f5da6a372e8ddf87783dd909c3fa\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70927\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e49c220fd06da92621ec9e59f902698bf96b7ebe", "tree": "2d9953bd9d2d278e3174951bd3be5d449a5b004f", "parents": [ "3ddd6034be8904b0c3ebf377cfac89efa563516f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:31:39 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "manibuilder: Update default tags, based on 1.2.x\n\nChange-Id: I7525e8cd3f97ce1c065df060e50ed63f824d8767\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70918\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ddd6034be8904b0c3ebf377cfac89efa563516f", "tree": "7758de0d11c5e00e34d4f25fe2c38d42ea3703f1", "parents": [ "76afdacfb72b7c713c738dedb3f56eb004d883fe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:23:22 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "manibuilder/anita: Move ARGS right before their usage\n\nThis makes it easier for docker to re-use image artifacts, e.g. the\nDebian installation part can be shared among all anita images now.\n\nChange-Id: I9d04c477b89b8e09b11e73c60e7a6cc03437d0ea\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70917\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "76afdacfb72b7c713c738dedb3f56eb004d883fe", "tree": "591e132403c8affa037293a983368e5f07fbad4c", "parents": [ "ea88f2196b8a550daa2e7332cdb854265dea3d3a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:22:19 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:32 2022 +0100" }, "message": "manibuilder/anita: Install pkg-config\n\nChange-Id: Ia8153f7f241dd5f34904a3ea23bbd30f1f980e55\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70916\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ea88f2196b8a550daa2e7332cdb854265dea3d3a", "tree": "b4adc3d95ecea703661ac0a0b0b89e021f51cebe", "parents": [ "48b1fde6b91f211d22a45ef73e36f6d3b1359ef7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:19:36 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:31 2022 +0100" }, "message": "manibuilder/anita: Use QEMU\u0027s -drive option over -hdb\n\nCurrent QEMU wants us to specify the `raw` format explicitly and\nlimits write access otherwise. So use the more elaborate `-drive`\nsyntax.\n\nChange-Id: If5f74592736ec4e0ef971a9a55bbdeb534358dd4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70915\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48b1fde6b91f211d22a45ef73e36f6d3b1359ef7", "tree": "dc086c8f3a6fbf1b54c07b1a3005a424aac39c27", "parents": [ "d4fbbb48bc7c94b59f9065f942de567cb95c5e0a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:15:27 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:31 2022 +0100" }, "message": "manibuilder/anita: Enable KVM when running on x86_64\n\nThis requires us to use privileged containers. Although, the QEMU\ninside should still provide enough encapsulation, we might want to\ndisable this in automated environments.\n\nChange-Id: I767287649511b46cd25125bcbceea8a0446fc76b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70914\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d4fbbb48bc7c94b59f9065f942de567cb95c5e0a", "tree": "351f86ebad280d85913bc21a103c02006372d798", "parents": [ "725a19e090637c576a80901bfc7283ac268e6c84" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 17:02:57 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:31 2022 +0100" }, "message": "manibuilder: Let build tests fail with the original error code\n\nWe can still run all tests with `make -k`.\n\nChange-Id: Ib59b8863186e5f7ecbaa2aa65cdbd51913dcf8e7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70913\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "725a19e090637c576a80901bfc7283ac268e6c84", "tree": "48cc87a1bfd5a7cfdbb944b6d17822797df27642", "parents": [ "fb9c18a7aafb2f71b49f004f43800cf213ccb6cd" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 11 00:01:04 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Adapt TEST_REMOTE and TEST_REVISION defaults\n\nIf ${TEST_LOCAL} is set, adapt the default remote and revision\naccordingly. Now this variable is all that is needed to test\na local flashrom commit, e.g.\n\n $ make alpine:amd64-v3.7 TEST_LOCAL\u003d~/flashrom\n\nChange-Id: I435beb81fd05db25fa6b0a7b517d4c8b9b57ceea\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70912\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "fb9c18a7aafb2f71b49f004f43800cf213ccb6cd", "tree": "823e26022ad7981d5ab6d4b36110cd8c3d97edf5", "parents": [ "bfe6484b3bb66fcbfc986ec9bc43155a8c8ea61b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:59:19 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Add service container with local Git access\n\nAdd a new target `local-git` that spawns a service container with a\nlocal Git daemon. The variable ${TEST_LOCAL} needs to point to the\ndirectory of a local git repository.\n\nChange-Id: I9e465551d3398fdb8d173a0a8fbd169561241a74\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70911\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "bfe6484b3bb66fcbfc986ec9bc43155a8c8ea61b", "tree": "8f4979e8d829f33dc37d368ba9dad39194b75881", "parents": [ "aa359a73420bf8c731f2f9733eb2f146f559825c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:54:24 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Automatically create `manibuilder` network bridge\n\nCreate a network bridge for all manibuilder containers. We\u0027ll add a\nservice container with access to a local Git repository later.\n\nChange-Id: Idb03c21dbd12bef59a2c683e169015e286c04d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70910\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aa359a73420bf8c731f2f9733eb2f146f559825c", "tree": "2cd6f9600d25001f868b6c73f851e2cd8ed21603", "parents": [ "34846e46a08dd743e8419d9e9ade00e3d3da0c5f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:52:46 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:30 2022 +0100" }, "message": "manibuilder: Make Git remote overridable\n\nChange-Id: Idfc1272f5a7370d3a183835ddf4052db374d6a26\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70909\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "34846e46a08dd743e8419d9e9ade00e3d3da0c5f", "tree": "bf228bd4dd70b83e1101565f3e6ca338fe980a08", "parents": [ "f4a1b5d2e8c74f4ad24764aca8b7d3ad53c1e176" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 10 23:45:38 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "manibuilder: Set $(TEST_REVISION) default in make\n\nChange-Id: I8320110a19c434b6d464d8036cc2a99fff41f63e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70908\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f4a1b5d2e8c74f4ad24764aca8b7d3ad53c1e176", "tree": "7dc5040c99ed99390ef540bdb4770ca673f72370", "parents": [ "c0b52db332ce95ca3227b35b3263c858882e0b5d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 27 14:02:36 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "manibuilder: Add list of 1.2.x targets\n\nWe didn\u0027t maintain a list at the 1.2 release. Maybe didn\u0027t even run\nmanibuilder. Let\u0027s start one with distributions available at the\n1.2 release and those available today.\n\nChange-Id: Ia6266ecfba5e9acb37acc41cc305f2f713de7a24\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70907\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c0b52db332ce95ca3227b35b3263c858882e0b5d", "tree": "945d00d92a9a9056e1a5f9927fca4647cb0644b6", "parents": [ "7cb43957c5fe405cd82584f0a54428f2d2d286ff" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 15 12:42:32 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:29 2022 +0100" }, "message": "Import manibuilder from flashrom master\n\nReferences to the upstream repository have been changed to\n`flashrom-stable.git`. The directory `flashrom` is kept,\nthough, so existing containers can be used for both projects.\n\nChange-Id: I8ba148e30602e8e03e3858f7c1eb6789230654d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70906\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7cb43957c5fe405cd82584f0a54428f2d2d286ff", "tree": "9981905ba97c0509e8686782855d97cffe77d80e", "parents": [ "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Mar 16 20:40:42 2022 +0530" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Sun Oct 30 09:43:35 2022 +0000" }, "message": "ichspi: Unify timeouts across all SPI operations to 30s\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\n`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument\nin favor of a fixed timeout of `30 seconds` for any given SPI operation\nas recommended by the SPI programming guide.\n\nDocument: Alder Lake-P Client Platform SPI Programming Guide\n Rev 1.30 (supporting document for multi-master accessing the\n SPI Flash device.)\n\nRefer to below section to understand the problem in more detail and SPI\noperation timeout recommendation from Intel in multi-master\nscenarios.\n\nOn Intel Chipsets that support multi-mastering access of the SPI flash\nmay run into a timeout failure when the operation initiated from a\nsingle master just follows the SPI operational timeout recommendation\nas per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR\nspecification, table 9.7).\n\nIn the multi-master SPI accessing scenario using hardware sequencing\noperation, it\u0027s impossible to know the actual status of the SPI bus\nprior to individual master starting the operation (SPI Cycle In Progress\na.k.a SCIP bit represents the status of SPI operation on individual\nmaster).\n\nThus, any SPI operation triggered in multi-master environment might need\nto account a worst case scenario where the most time consuming operation\nmight have occupied the SPI bus from a master and an operation initiated\nby another master just timed out.\n\nHere is the timeout calculation for any hardware sequencing operation:\n Worst Case Operational Delay \u003d\n (Maximum Time consumed by a SPI operation + Any marginal\n\t adjustment)\n\n Timeout Recommendation for Hardware Sequencing Operation \u003d\n ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +\n Current Operational latency)\n\nAssume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC,\nGbE and other reserved etc, hence, the Timeout Calculation for SPI\nerase Operation would look like as below:\n\n Maximum Time consumed by a SPI Operation \u003d 5 seconds\n\n Worst Case Operational Delay \u003d 5 seconds\n\n Timeout Recommendation for Hardware Seq Operation \u003d\n 5 seconds * (6 - 1) + 5 seconds \u003d 30 seconds\n\nBUG\u003db:223630977\nTEST\u003dAble to perform read/write/erase operation on PCH 600 series\nchipset (board name: Brya).\n\nOriginal-Signed-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867\nOriginal-Tested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nChange-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68691\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\n" }, { "commit": "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32", "tree": "fbe81e1f039bd7813b2973db04fc2c3ac4f82b1a", "parents": [ "1900e1d5d39d91b762c9a02ef2445868b323ca87" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Jul 22 23:23:28 2022 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:03:11 2022 +0000" }, "message": "Makefile: Fix dependencies for developerbox_spi\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\nThe developerbox_spi programmer depends on bitbang SPI support. Thus,\nfix that.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: Ic0fe589ffdccede0fbf6360c2bebe58a36654f10\nReviewed-on: https://review.coreboot.org/c/flashrom/+/66096\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68064\n" }, { "commit": "1900e1d5d39d91b762c9a02ef2445868b323ca87", "tree": "a95c01537af1a6a2a643f696c5e33df886471619", "parents": [ "87aa19314523d1cffdef57fbdf65d8328824026c" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 02 12:42:23 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:00:37 2022 +0000" }, "message": "Replace freenode references\n\nThe flashrom project no longer uses freenode. To avoid having outdated\nman pages in the future, the contact methods are now listed in the wiki.\n\nChange-Id: I75e8f43c50dc4c3feede0250334a877cdaac8103\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/56031\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68063\n" }, { "commit": "87aa19314523d1cffdef57fbdf65d8328824026c", "tree": "bee9fc52eca9b27172ae3d060701a4cbcafc1d06", "parents": [ "89cc73bda5fd181e9fcab2eadf5f80759379c1b3" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 02 12:48:10 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Oct 06 01:00:32 2022 +0000" }, "message": "print_wiki.c: Update mailing list reference\n\nChange-Id: I5c67b5b3be2f306132d8565539bbf10477222026\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/56030\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68062\n" }, { "commit": "89cc73bda5fd181e9fcab2eadf5f80759379c1b3", "tree": "b1ddf34a7d13413887257ae0347109a336c54ce5", "parents": [ "380090faffcbe3cbdc20af9c75979fdafaa5a834" ], "author": { "name": "Pyry Kontio", "email": "pyry.kontio@drasa.eu", "time": "Mon Jul 06 12:57:35 2020 +0900" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:35:30 2022 +0000" }, "message": "Makefile: Fix building on AArch64 NixOS\n\nThe parsing of the output of archtest.c produced an unexpected\nvalue on AArch64 NixOS. For example, the make variable ARCH was set to:\n\n```\nbit outside of fd_set selected\narm\n```\n\nThis made the arch and OS checks fail.\n\nThis commit simplifies the parsing, making it more robust.\n\nThe C files archtest.c, endiantest.c and os.h used to set the\nTARGET_OS, ARCH and ENDIAN variables, respectively, output\nthe result of the test as the final line, so just extracting\nthe final line and removing double quoting is enough.\n\nThis commit also fixes a bug with debug_shell lacking escaping\nsingle quotes, which prevented using the single quote in the\ndebug_shell calls. It used to work by accident before this fix;\nthe line in the call happened to contain a balanced pair of double\nquotes and lacked other characters that needed escaping, which\ndidn\u0027t break the debug_shell, but this was accidental and very\nbrittle.\n\nSigned-off-by: Pyry Kontio \u003cpyry.kontio@drasa.eu\u003e\nChange-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510\nReviewed-on: https://review.coreboot.org/c/flashrom/+/43140\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67902\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "380090faffcbe3cbdc20af9c75979fdafaa5a834", "tree": "d6dac3cefcc91f4451b73b0bf8da60473ca6c34c", "parents": [ "298ac33bc495bba371629951dce8ea67e5e0ca78" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 01:45:11 2022 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:21 2022 +0000" }, "message": "pcidev: Always fetch ident info\n\nAs discovered earlier[1], the `vendor_id` and `device_id` fields are not\nalways automatically set. However, we use these fields throughout flash-\nrom. To not lose track when we actually fetched them, let\u0027s always call\npci_fill_info(PCI_FILL_IDENT) before returning a `pci_dev` handle.\n\n[1] Commit ca2e3bce0 (pcidev.c: populate IDs with pci_fill_info())\n\nBackported to older versions where pcidev handling was much more\nscattered.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iae2511178bec44343cbe902722fdca9eda036059\nTicket: https://ticket.coreboot.org/issues/367\nReviewed-on: https://review.coreboot.org/c/flashrom/+/64573\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67877\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "298ac33bc495bba371629951dce8ea67e5e0ca78", "tree": "9387c285a1af5bc95ca9c698b3d98f05f1f141df", "parents": [ "245e540ecbe8e0daa8db747dcc6d470fa6f79938" ], "author": { "name": "Daniel Verkamp", "email": "dverkamp@chromium.org", "time": "Mon Oct 12 12:55:56 2020 -0700" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:13 2022 +0000" }, "message": "pcidev.c: populate IDs with pci_fill_info()\n\nWith pciutils 3.7.0, flashrom is unable to match any PCI devices by\nvendor/device ID because the vendor_id and device_id fields of struct\npci_dev are not filled in.\n\nCall pci_fill_info() to request these identifiers before trying to match\nthem against the supported device list.\n\nThe pciutils ChangeLog for 3.7.0 mentions that the documentation and\nback-end behavior for pci_fill_info() was updated; it seems that a call\nto pci_fill_info() was always intended to be required, but some backends\n(such as the sysfs one used on Linux) would fill the identifier fields\neven when not requested by the user. The pci_fill_info() function and\nthe PCI_FILL_IDENT flag have been available for all versions of pciutils\nsince at least 2.0 from 1999, so it should be safe to add without any\nversion checks.\n\nWith this change, reading/writing a nicintel_spi boot ROM is successful.\n\nSigned-off-by: Daniel Verkamp \u003cdverkamp@chromium.org\u003e\nChange-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46310\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67876\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "245e540ecbe8e0daa8db747dcc6d470fa6f79938", "tree": "b8bfd72696a54c0adb7f3e3d06afaedcf9b36c48", "parents": [ "04fce478cb9aba339439d1955c3355a075445ec1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 06 00:21:52 2022 +0100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:09 2022 +0000" }, "message": "dmi: Correctly check for ERROR_PTR\n\nFor the physmap*() functions, NULL is considered valid return value.\nFixes a segmentation fault when DMI tables can\u0027t be mapped.\n\nTested on intel/eblake board with broken coreboot.\n\nChange-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/62611\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67875\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "04fce478cb9aba339439d1955c3355a075445ec1", "tree": "8c6342749297f623f282aea64c84082dbb8835e2", "parents": [ "96cc5d3ea84e7e7e3a6029cf728cef061ccae45f" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Jan 11 18:26:48 2022 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:06:03 2022 +0000" }, "message": "linux_mtd: check ioctl() return value properly\n\nMake the linux_mtd driver treat any negative return value from the\nMEMERASE ioctl as an error. Previously it only treated -1 as an error.\n\nBUG\u003db:213561594,b:210973586,b:182223106\nBRANCH\u003dnone\nTEST\u003dbuilds\n\nChange-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/60996\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67874\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "96cc5d3ea84e7e7e3a6029cf728cef061ccae45f", "tree": "3072b945e3be60c09c945c47adf5fb47fcdacc7b", "parents": [ "a8c0b68199c5f76073a8b9c2ecf2d3694086591e" ], "author": { "name": "Michael Niewöhner", "email": "foss@mniewoehner.de", "time": "Tue Sep 21 17:37:32 2021 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:56 2022 +0000" }, "message": "flashrom.8: add missing entry for `--flash-contents`\n\nChange-Id: I64a8200a86329bd26a2069c5dc39430de9f8ba09\nSigned-off-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/57807\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67873\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "a8c0b68199c5f76073a8b9c2ecf2d3694086591e", "tree": "2e77e4b73a0b42227f08ad5879750498eb84aba4", "parents": [ "595c5d017402fb20bef14e4d2c399251470c95fe" ], "author": { "name": "Marc Schink", "email": "dev@zapb.de", "time": "Sat Aug 22 11:29:22 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:49 2022 +0000" }, "message": "jlink_spi: Reduce transfer size\n\nThe maximum transfer size is too large for some devices and\nresults in an USB timeout.\n\nChange-Id: If2c00b1524ec56740bdfe290096c3546cf375d73\nSigned-off-by: Marc Schink \u003cdev@zapb.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48379\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67872\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "595c5d017402fb20bef14e4d2c399251470c95fe", "tree": "49b5163834504c40ffdb373be4360426ba99204e", "parents": [ "5feb8cdb6ff497e45cda73839dacafc240bf83bb" ], "author": { "name": "Douglas Anderson", "email": "dianders@chromium.org", "time": "Fri Jan 29 16:35:24 2021 -0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:43 2022 +0000" }, "message": "linux_mtd: Disable buffering on the mtd device\n\nWe open the device node for the MTD device with this:\n dev_fp \u003d fopen(dev_path, \"r+\")\n\nIn C fopen() is allowed to provide _buffered_ access to the file.\nThat means that the standard library is allowed to read ahead and/or\nreturn cached data. That\u0027s really not what we want for something like\nthis. Let\u0027s turn it off.\n\nThis fixes a problem where flashrom would sometimes fail to \"verify\"\nthat it erased the flash. The error message would look something like\nthis:\n\nErasing and writing flash chip... FAILED at 0x0000e220! Expected\u003d0xff, Found\u003d0xe9, failed byte count from 0x0000e200-0x0000e2ff: 0xdc\n failed byte count from 0x0000e000-0x0000efff: 0xffffffff\n ERASE_FAILED\nFAILED!\nUh oh. Erase/write failed. Checking if anything changed.\n\nAfter the failure I could read the flash device with a new invocation\nof flashrom and I would see that, indeed, the erase had worked.\n\nTracing in the kernel showed that when the failure happened we saw a\npattern that looked like this:\n* Read 0x0b00 bytes starting at 0x0000d000\n* Read 0x1000 bytes starting at 0x0000db00\n* Erase 0x1000 bytes starting at 0x0000e000\n\n...and then there was _not_ a read after the erase. It can be assumed\nthat, since userspace had already read 0xdb00 - 0xeaff that it was\nlooking at old buffered data after the erase.\n\nSigned-off-by: Douglas Anderson \u003cdianders@chromium.org\u003e\nChange-Id: I989afd83a33013b2756a0090d6b08245613215c6\nReviewed-on: https://review.coreboot.org/c/flashrom/+/50155\nReviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67871\nReviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "5feb8cdb6ff497e45cda73839dacafc240bf83bb", "tree": "fd3c99ccf093d56e957068e763d9c83d774ca2c7", "parents": [ "b822ce85aaed8c6dfa8f5e1e2354db5c9db50509" ], "author": { "name": "Xiang Wang", "email": "merle@hardenedlinux.org", "time": "Wed Jan 20 17:31:19 2021 +0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:38 2022 +0000" }, "message": "helpers.c: Fix undefined behavior in strndup()\n\nUsing strlen() or strdup() inside strndup() is problematic: if the\ninput string is not null-terminated, these functions can read past the\nend of the buffer, which triggers undefined behavior. Rewrite the\nfunction to never read past the provided `maxlen` bound.\n\nChange-Id: Id34127024085879228626fbad59af03268ec5255\nSigned-off-by: Xiang Wang \u003cmerle@hardenedliux.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/49741\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67870\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b822ce85aaed8c6dfa8f5e1e2354db5c9db50509", "tree": "2c7f7e02cb143b306995128b1f52e5ee6b7a4f88", "parents": [ "2e3e10669d719545968ddec3b44b8a9363f4b432" ], "author": { "name": "Medicine Yeh", "email": "medicinehy@gmail.com", "time": "Thu Dec 17 15:40:42 2020 +0800" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:31 2022 +0000" }, "message": "dediprog: Fix segmentation fault on no device found\n\nlibusb_exit() call is done by dediprog_open() under the\nret \u003d\u003d 1 condition. Removing this line has no impact on\nany flow and side effect of the program.\n\nChange-Id: I38b3f3ee3f9d46845df1404791f4a4782320aa7c\nSigned-off-by: Medicine Yeh \u003cmedicinehy@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48688\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67869\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "2e3e10669d719545968ddec3b44b8a9363f4b432", "tree": "95f7807b9ec68fdc9d21590fc7c174ee0f391fca", "parents": [ "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Dec 02 13:17:46 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:24 2022 +0000" }, "message": "chipset_enable.c: Validate physmap() return rcrb value\n\nValidate the physical mapping in enable_flash_silvermont().\n\nChange-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67868\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d", "tree": "5541efefb64efc6611a315e12936608c37803c3c", "parents": [ "d92dd50bcac6b2d0dfffa9f983712f7400990f3d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Thu Oct 15 19:19:05 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:15 2022 +0000" }, "message": "chipset_enable.c: check return value from rphysmap() call\n\nPort from the ChromiumOS fork of flashrom.\n\nChange-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46444\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67867\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "d92dd50bcac6b2d0dfffa9f983712f7400990f3d", "tree": "957fbc3c081425b31aeba3fb9c44451397323e94", "parents": [ "4af3609828a980bad9ecaf99365f99305d4180f8" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Oct 19 14:20:36 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:10 2022 +0000" }, "message": "it87spi.c: Prevent use-after-free bug\n\nThe memory for the `param` string is aliased by `dualbiosindex_suffix`.\nMoreover, `errno` could have been modified by the call to `free()`.\nTherefore, only free the former when there are no more uses of either.\n\nChange-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67866\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "4af3609828a980bad9ecaf99365f99305d4180f8", "tree": "2fca2548be1d41c2e48164e3c4f2683ac1862837", "parents": [ "355a1df1837e36075f2b6e59ec1f7db1db95f02a" ], "author": { "name": "Yuji Sasaki", "email": "sasakiy@chromium.org", "time": "Fri Mar 22 10:59:50 2019 -0700" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:05 2022 +0000" }, "message": "spi25: Debug flashrom crash when Write Protect is ON\n\nWhen hardware write protect is applied, flashrom crashed and\ngenerate coredump. spi_disable_blockprotect_generic() calls\nflash-\u003echip-\u003eprintlock() method when disable was failed,\nbut this method is optional, can be NULL depends on type of\nflashrom chip. NULL pointer check before call is added to\navoid crash.\n\nBRANCH\u003dnone\nBUG\u003db:129083894\nTEST\u003dRun on Mistral P2\n(On CR50 console, run \"wp disable\")\nflashrom --wp-range 0 0x400000\nflashrom --wp-enable\n(On CR50 console, run \"wp enable\")\nflashrom -r /tmp/test.bin\nVerify \"Block protection could not be disabled!\" is shown,\nbut flash read completes.\nSigned-off-by: Yuji Sasaki \u003csasakiy@chromium.org\u003e\n\nChange-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e\nReviewed-on: https://chromium-review.googlesource.com/1535140\nCommit-Ready: ChromeOS CL Exonerator Bot \u003cchromiumos-cl-exonerator@appspot.gserviceaccount.com\u003e\nTested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Stefan Reinauer \u003creinauer@google.com\u003e\nReviewed-by: SANTHOSH JANARDHANA HASSAN \u003csahassan@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40468\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67865\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "355a1df1837e36075f2b6e59ec1f7db1db95f02a", "tree": "c8293d39eff36cc6929242ffe642ba8f4e2a13bb", "parents": [ "399a4dd721a64a1d22e2f8028cc39d6496515ed6" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Thu Apr 23 09:36:12 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:00 2022 +0000" }, "message": "stlinkv3_spi: Avoid division by zero\n\nChange-Id: I08c0612f3fea59add9bde2fb3cc5c4b5c3756516\nFound-by: Coverity Scan #1412744\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40653\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67864\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "399a4dd721a64a1d22e2f8028cc39d6496515ed6", "tree": "6a40ff5ca048148294b209d8cb99ab9558fdc44f", "parents": [ "b57f48f77f367c43cd83878d92aa55de151c0798" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 15 12:59:42 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:53 2022 +0000" }, "message": "chipset_enable.c: Disable SPI on ICH7 if booted from LPC\n\nCommit 92d6a86 (\"Refactor Intel Chipset Enables\") eliminated a check\nto disable SPI when ICH7 has booted from LPC, as the hardware does not\nsupport it. Therefore, when flashrom probes the SPI bus, it times out\nwaiting for the hardware to react, for each and every SPI flash chip.\nThis results in very long delays and countless instances of the error:\n\n Error: SCIP never cleared!\n\nTo prevent this, bring back part of the lost check. Probing for LPC and\nFWH when booted from SPI does not seem to cause any problems on desktop\nmainboards with ICH7, so don\u0027t disable LPC nor FWH if that is the case.\n\nTested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.\n\nChange-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40401\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67863\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b57f48f77f367c43cd83878d92aa55de151c0798", "tree": "d2b42aa861392afb20d841ec86a1c860abd90a05", "parents": [ "b428c319ed629bef50e7e154c472635f68ea8edc" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Sat May 02 16:07:11 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:47 2022 +0000" }, "message": "spi95: Check for success before using send_command\u0027s returned data\n\nIf the transfer failed, the data might be invalid.\n\nChange-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880\nFound-By: Coverity Scan #1405870\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40970\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67862\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b428c319ed629bef50e7e154c472635f68ea8edc", "tree": "f0ef56e854f7f1a7e37a722ef5404724e03ab3e0", "parents": [ "5ac6a637b07ea05a363ede3643ff627913378a2a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed May 27 12:15:51 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:40 2022 +0000" }, "message": "libflashrom.c: Use casts on enum conversions\n\nThis allows flashrom to build with GCC 10.\n\nChange-Id: I2166cdf3681452631ef8e980face2924e9a6c81a\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/41775\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67861\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\n" }, { "commit": "5ac6a637b07ea05a363ede3643ff627913378a2a", "tree": "814e336db7b38ecdf8a1fd6602203c75438a6a2a", "parents": [ "05c629be2964bcee368c03d805747da15281856d" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Wed Oct 28 17:29:38 2020 +0100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:34 2022 +0000" }, "message": "test_build.sh: Move build test procedure to repository\n\nInstead of hard coding the test procedure on qa.coreboot.org, allow\nrunning a script in the repo instead. The server is already adapted\nto do that, so once there\u0027s a test_build.sh file in the toplevel\ndirectory, it\u0027s run in place of the default operation.\n\nThe content of this change mirrors the default operation exactly so\nshould serve as a good starting point.\n\nThe script is executed in an encapsulate[0] context with the workspace,\n/tmp and $HOME/.ccache writable, everything else read-only and\nnetwork disabled.\n\nIt should return 0 on success, anything else on failure, as is normal\nfor UNIX processes.\n\n[0] https://review.coreboot.org/cgit/encapsulate.git\n\n(Backported minus the Meson support)\n\nChange-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46894\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/62617\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67860\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "05c629be2964bcee368c03d805747da15281856d", "tree": "ffe6f7df4ee0ba5a76e58f739200cc6b3e0383e2", "parents": [ "b5433b782ff7cbde14ebd91aeac27efaec83e9d0" ], "author": { "name": "Bernhard Urban-Forster", "email": "lewurm@gmail.com", "time": "Sun Feb 02 21:29:48 2020 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:21:46 2020 +0000" }, "message": "flashchips: Add Spansion S25FL512S\n\nAs found on the Tesla AP2.5 board.\n\nBased on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html\n\nTested with:\n flashrom -p linux_spi:dev\u003d/dev/spidev0.0,spispeed\u003d512 -r content.bin\n\nSigned-off-by: Bernhard Urban-Forster \u003clewurm@gmail.com\u003e\nChange-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38596\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "b5433b782ff7cbde14ebd91aeac27efaec83e9d0", "tree": "facd5500f80682ce09fe7135362df5f4e7a87609", "parents": [ "3eae69531936cc41f227a532efea4cc3598d0f68" ], "author": { "name": "Johanna Schander", "email": "git@mimoja.de", "time": "Sun Dec 29 15:16:14 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:00:51 2020 +0000" }, "message": "chipset_enable.c: Add Ice Lake U to known and tested systems\n\nIntel Ice Lake systems use an 495 Series Chipset\nthat behaves compatible to pch300 chips but chip names\nare undocumented at this point.\n\nThis change was tested in read/write/erase on the Razer\nBlade Stealth (late 2019) with intel 1065G7 CPU and\n\"Ice Lake U Premium PCH\".\n\nChange-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15\nSigned-off-by: Johanna Schander \u003cgit@mimoja.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37987\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Christoph Pomaska \u003cgithub@slrie.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3eae69531936cc41f227a532efea4cc3598d0f68", "tree": "ba6a15846f4d3776eb8806eb21971721adf7e25c", "parents": [ "3799a1cc1adda28bb8bd4464020a7bbadd3960f1" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 31 10:53:47 2020 +0100" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Feb 01 17:36:22 2020 +0000" }, "message": "Fix building with meson, again\n\nChange-Id: Iea40da587729f3975a8901d3933e7567805242c5\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38659\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Frans Hendriks \u003cfhendriks@eltan.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "3799a1cc1adda28bb8bd4464020a7bbadd3960f1", "tree": "d654267ccdf97429733da5e0c07560be27a9d6f1", "parents": [ "e4c2b48f39902c7ff49a6a9e29525bdd3092c412" ], "author": { "name": "Wim Vervoorn", "email": "wvervoorn@eltan.com", "time": "Mon Jan 20 15:01:54 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 22 14:15:33 2020 +0000" }, "message": "chipset_enable: Add Kaby Lake U Prem. to known and tested systems\n\nIntel Kaby Lake U (with the 9d4e device id) support is available but\nmarked not tested.\n\nTested reading, writing and erasing both internal flash chips on the\nFacebook Monolith system with the Intel i3 7100U SoC. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall follow\nsuit as well.\n\nSigned-off-by: Wim Vervoorn \u003cwvervoorn@eltan.com\u003e\nChange-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38481\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e4c2b48f39902c7ff49a6a9e29525bdd3092c412", "tree": "58008ef76cc0d8540ab5bf4cce80973e9fa05a59", "parents": [ "67710afe4e34f63a6e7b28d5493753caa8e79a52" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Jan 20 11:22:41 2020 +0100" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Mon Jan 20 13:02:48 2020 +0000" }, "message": "Fix typos\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nChange-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38477\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "67710afe4e34f63a6e7b28d5493753caa8e79a52", "tree": "0edfe8de4e07350a7e89115d1532a24f130f6072", "parents": [ "370a9f3eea20a575f32ebf6ecead7ccf7562a2c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 18 18:23:22 2020 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 19 23:48:48 2020 +0000" }, "message": "Revert \"pcidev.c: Factor out pcidev_validate() into pure fn\"\n\nThis reverts commit e28d75ed7204d7fac2c0fac13978098530b0574e.\n\nThis is broken in multiple ways, e.g. pcidev_init() can only return\nNULL.\n\nChange-Id: I06242147ba9d3a062d442f645eb0800ef51af19f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nReported-by: Michael Bishop \u003ccleverca22@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38319\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "370a9f3eea20a575f32ebf6ecead7ccf7562a2c0", "tree": "859c8e755786dad4b6e08f4343a2129efad3f01b", "parents": [ "324929c3d725ce264b2390525dbc9070f6029cc4" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 31 18:22:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 02 16:15:10 2020 +0000" }, "message": "stlinkv3_spi: Move a declaration out of for-loop head\n\nGCC 4.8 wants an explicit `-std\u003dc99` or something for this to work. It\nseems easier to keep the common declaration style.\n\nChange-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38034\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\n" }, { "commit": "324929c3d725ce264b2390525dbc9070f6029cc4", "tree": "73ee656c8bc1933329e4239214e4b0eaaadb36f8", "parents": [ "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Thu Aug 01 19:14:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 31 17:25:41 2019 +0000" }, "message": "Add support for STLINK V3 debugger/programmer via its SPI bridge\n\nChange-Id: Icffab87ac8f2c570187ed753ec70f054541873a4\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34661\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53", "tree": "8df82988b92b7b091358e72570671d908016a08a", "parents": [ "a9d6d1a817ce20e834fe7c354629976e3e5f1108" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Dec 18 00:26:15 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 21 11:47:21 2019 +0000" }, "message": "chipset_enable.c: Mark Intel HM76 as DEP\n\nTested reading, writing and erasing the internal flash chip using a\nSamsung NP530U3C laptop with an Intel HM76 PCH. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37803\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "a9d6d1a817ce20e834fe7c354629976e3e5f1108", "tree": "657071019f73d3b3070be348a73949544e6312b4", "parents": [ "34d07f00b2990bec4a2ce12852acd42c08ddf217" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Tue Nov 19 19:29:26 2019 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:50:36 2019 +0000" }, "message": "mysteries_intel: Add a section about SMM_BWP\n\nSomething to point users to when SMM_BWP might be causing problems.\n\nChange-Id: I394c033e8d4ff96433162f86aefb428d8acf6349\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36986\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "34d07f00b2990bec4a2ce12852acd42c08ddf217", "tree": "17ca5823749ac67144dc8e50c3f4c9b2f982522a", "parents": [ "4139438943010c7aec6549d8b18865da5b70e978" ], "author": { "name": "Rosen Penev", "email": "rosenp@gmail.com", "time": "Tue Jul 02 00:14:01 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:29:21 2019 +0000" }, "message": "flashrom: Add support for ARC platform\n\nSigned-off-by: Rosen Penev \u003crosenp@gmail.com\u003e\nChange-Id: I88cbe74b716d5fab16133fbf2ce9c35b74c25f32\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35831\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4139438943010c7aec6549d8b18865da5b70e978", "tree": "0c517723249fe9a4065ee2b52603d34a385290a6", "parents": [ "89622674b29c09bb33cb5844520d9271ebef8ea0" ], "author": { "name": "darkarnium", "email": "peter.adkins@kernelpicnic.net", "time": "Mon Nov 04 20:06:48 2019 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:25:30 2019 +0000" }, "message": "flashchips: Add AT25SF321\n\nThis commit adds support for the Adesto AT25SF321 SPI flash chip. Probe\nand read operations have been tested via FT2232H interface, but writes\nhave not been verified.\n\nDatasheet is available at the following URL:\nhttps://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf\n\nChange-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56\nSigned-off-by: Peter Adkins \u003cpete@kernelpicnic.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36904\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "89622674b29c09bb33cb5844520d9271ebef8ea0", "tree": "76f3035d59461fc0e70fee40e00ef410ea011769", "parents": [ "5d068ddca4aa8c657bbf3e7df8cf94c8e3212ada" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 10 18:05:55 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 10 16:38:50 2019 +0000" }, "message": "nicintel_eeprom: Reduce usage of is_i210()\n\nDon\u0027t entagle the code paths for the two NIC classes if it\u0027s not necessary.\n\nOnly compile tested.\n\nChange-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33637\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "5d068ddca4aa8c657bbf3e7df8cf94c8e3212ada", "tree": "b7b401c7dbdfa20aee86e70574cdcb77bda6f468", "parents": [ "7bd31a435b7c8f2b278b9e8233083ff2134abe2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 17 13:39:46 2019 +0100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Fri Dec 06 02:50:41 2019 +0000" }, "message": "Revert \"print.c: Dedup \u0027test_state_to_text()\u0027 logic\"\n\nThis reverts commit 61e16e549a52194ac80ef40504f2dc661d1ff99c.\n\nObviously throws alignment in the table off and changes output\nclass from `general` to `programmer` for no visible reason.\n\nChange-Id: I864044b9fac6af9cf6a89c053eccdcb36f17c7bd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36909\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7bd31a435b7c8f2b278b9e8233083ff2134abe2d", "tree": "a9f64423fa32bbb53adaa48eb08812d1274039b9", "parents": [ "e28d75ed7204d7fac2c0fac13978098530b0574e" ], "author": { "name": "Russ Dill", "email": "Russ.Dill@gmail.com", "time": "Wed Oct 30 00:40:43 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Dec 01 22:23:08 2019 +0000" }, "message": "ft2232_spi: Add support for Tin Can Tools Flyswatter/Flyswatter 2\n\nThe Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H\nwith a JTAG interface wired to port A. The buffers that drive the\nJTAG pins need to be enabled with an nOE signal from the\nFT2232H ADBUS6 and ADBUS7 pins.\n\nFlyswatter has an ARM-14 JTAG interface and Flyswatter 2 has\nan ARM-20 JTAG interface.\n\nChange-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd\nSigned-off-by: Russ Dill \u003cRuss.Dill@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36896\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e28d75ed7204d7fac2c0fac13978098530b0574e", "tree": "324401adc58b52b390684e05be4c96f79f51c236", "parents": [ "1d80d645875cde4aa1ea17bd1d166619bed09682" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Nov 27 16:44:19 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Nov 28 14:00:52 2019 +0000" }, "message": "pcidev.c: Factor out pcidev_validate() into pure fn\n\nThis makes writing unit-tests easier.\n\nChange-Id: Ia2718f1f40851d3122741cd0e50b0c2b647b727a\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37264\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1d80d645875cde4aa1ea17bd1d166619bed09682", "tree": "f40bdbc0af4782ffc5c91fb0b7b986268d3bca2b", "parents": [ "4a55e6885816aa2a45314975686356ce282cae5c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Nov 26 23:31:06 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Nov 28 10:00:21 2019 +0000" }, "message": "cbtable.c: Factor out lb_table_validation logic\n\nWrite a pure function for the table validation logic, it is\neasier to unit-test.\n\nChange-Id: I07b0f95ec0443fa6a8f54eb93f4a7ea1875cccad\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37239\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "4a55e6885816aa2a45314975686356ce282cae5c", "tree": "e689df39d5b23b188196c98fa5feb4ad5b85afee", "parents": [ "61e16e549a52194ac80ef40504f2dc661d1ff99c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Nov 26 23:28:05 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Nov 28 10:00:11 2019 +0000" }, "message": "cbtable.c: Factor out lb_header_validation logic\n\nWrite a pure function for the header validation logic, it is\neasier to unit-test.\n\nChange-Id: Ia288bcbc5c371329952a6efba30ccf0e18965a3d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37238\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "61e16e549a52194ac80ef40504f2dc661d1ff99c", "tree": "7531df670485b94cd5d1337115eb133e013d0928", "parents": [ "301ae22b456a040d8944daa0268aa97aa93a517f" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Sun Nov 17 14:29:33 2019 +1100" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Sun Nov 17 11:32:46 2019 +0000" }, "message": "print.c: Dedup \u0027test_state_to_text()\u0027 logic\n\nChange-Id: I72164323d7ff98fc50cb0c47b69741a4f047e098\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36905\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "301ae22b456a040d8944daa0268aa97aa93a517f", "tree": "31fcd3538c0d36fa43c392a86fc4c6383809cf0a", "parents": [ "83c56b870bcf0d241993813b9f695c2118532f7a" ], "author": { "name": "Ryan O\u0027Leary", "email": "ryanoleary@google.com", "time": "Mon Jun 24 19:14:33 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 15 09:29:37 2019 +0000" }, "message": "dediprog.c: Add id parameter to dediprog programmer\n\nWhen multiple dediprog programmers are connected, the \u0027id\u0027 parameter\nallows you to specify which one to use. The id is a string like SF012345\nor DP012345. The value is printed on a sticker on the back of the dediprog.\n\nThis is an improvement over the \u0027device\u0027 parameter which is based on\nenumeration order and changes when you plug/unplug devices or reboot the\nmachine.\n\nTo find the id without the sticker, run flashrom with the -V option.\nThis prints the ids as they are enumerated. Alternatively, with dpcmd,\nyou can use the --list-device-id and --fix-device commands to list and\nwrite device ids respectively.\n\nNote this only supports SF100 at the moment, but SF600 support is\npossible with more work.\n\nChange-Id: I4281213ab02131feb5d47bf66118a001cec0d219\nSigned-off-by: Ryan O\u0027Leary \u003cryanoleary@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34160\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "83c56b870bcf0d241993813b9f695c2118532f7a", "tree": "81af4dcd1d8c6b94343b8b230e18a6f802e47382", "parents": [ "93737bcaf5e9c54501eb411b84c3b32e2dff944a" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Tue Nov 05 17:47:43 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:47:32 2019 +0000" }, "message": "Fix building with GCC 4.9\n\nIt doesn\u0027t like empty initializers.\n\nChange-Id: If2988e60401155f87ee3369c77f00ccf9332012c\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36629\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93737bcaf5e9c54501eb411b84c3b32e2dff944a", "tree": "8accecfc9ff20ed5dd1fdab7c51ae0ef9e690a9e", "parents": [ "9355e6faf66653655cef5ab312c00e70582fe595" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 18:30:01 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:42:37 2019 +0000" }, "message": "sb600spi.c: Generalise determin_generation() after Yangtze\n\nDrop dead USE_YANGTZE_HEURISTICS code and add Promontory support.\n\nChange-Id: I5aa7370025f5c1af56c6cb96194b6f3007d0ede7\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36426\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9355e6faf66653655cef5ab312c00e70582fe595", "tree": "f270bcba5757d3efa66f841d697aa25956a3d485", "parents": [ "c0a27e1f1748650726d81f1c00c1ebd440f3ea38" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 18:18:18 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:42:22 2019 +0000" }, "message": "sb600spi.c: Fold up debug logic into determine_generation()\n\nChange-Id: I6c722e29b321285bf20fb5ee30c912dcdd83411b\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36425\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c0a27e1f1748650726d81f1c00c1ebd440f3ea38", "tree": "7c7b0f7a03e7deb33ce9df99ee9fff1cc9db78fc", "parents": [ "2d20d6db39547f013b66230f378ceb8e21fa36e3" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Oct 29 17:05:39 2019 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:41:10 2019 +0000" }, "message": "sb600spi.c: Consolidate smbus dev revision derivation\n\nV.2: Rename \u0027find_smbus_dev()\u0027 -\u003e \u0027find_smbus_dev_rev()\u0027.\n\nChange-Id: I766b29cc1c7d01aa0bcf6cb9ff5ab73fa1995dcd\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36420\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2d20d6db39547f013b66230f378ceb8e21fa36e3", "tree": "7816f91833c2540ec74f97fe5de4ad4dd81165e0", "parents": [ "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jan 30 20:20:15 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:40:21 2019 +0000" }, "message": "Add support for National Instruments USB-845x devices\n\nChange-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/25683\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d", "tree": "65860cc7d10787128bc90609af22e74ec1465f39", "parents": [ "80e8dc4df72b72170190a91c31cdc0a0b5e08358" ], "author": { "name": "Peichao Wang", "email": "peichao.wang@bitland.corp-partner.google.com", "time": "Mon Nov 11 15:26:41 2019 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 13 12:32:11 2019 +0000" }, "message": "flashchips: Add W25Q128JW_DTR\n\nPort the code from chromeos flashrom\n\nBUG\u003db:144297264\nTEST\u003dTested using W25Q128JWDTR in SPI mode\n\nSigned-off-by: Peichao.Wang \u003cpeichao.wang@bitland.corp-partner.google.com\u003e\nChange-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36717\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" } ], "next": "80e8dc4df72b72170190a91c31cdc0a0b5e08358" }