)]}' { "log": [ { "commit": "7e3c81ae7122120fe10d43fcba61a513e2461de9", "tree": "f505342cd2879b9cc77c2cbf66dda0231869ee9c", "parents": [ "0ee2dc06839d2f4f3197dd0ef51202e51e945bea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:56:50 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:48:28 2017 +0000" }, "message": "spi25: Merge remainder of spi4ba in\n\nChange-Id: If581e24347e45cbb27002ea99ffd70e334c110cf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22388\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ee2dc06839d2f4f3197dd0ef51202e51e945bea", "tree": "6eb5e8b7e9f16767ed5b63ea909ecb5b7001414c", "parents": [ "7a077222566c84546dca4a56c1a509626036e429" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:27:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:47:05 2017 +0000" }, "message": "spi4ba: Drop now obsolete, redundant functions\n\nChange-Id: I1d04448fd1acbfc37b8e17288f497a4292dfd6d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22387\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7a077222566c84546dca4a56c1a509626036e429", "tree": "b4cd487275dd4ffc92ad6ac885268842efbe9eb3", "parents": [ "a1672f829328e877d9b8dea7777f25e2eba52d0e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:18:30 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:46:54 2017 +0000" }, "message": "spi25: Remove now obsolete `four_bytes_addr_funcs` path\n\nChange-Id: Idb7c576cb159630da2268813388b497cb5f46b43\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22386\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1672f829328e877d9b8dea7777f25e2eba52d0e", "tree": "8f90cab7e18bc875241ff66eef153b80e7c4a71b", "parents": [ "f43c654ad0dcb11b2738bbfac9246d09bb1949e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:00:20 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:45:46 2017 +0000" }, "message": "spi25: Enable native 4BA read and write using feature bits\n\nPrefer the native 4BA instruction when they are supported. In this\ncase, override our logic to decide to use a 4BA address.\n\nChange-Id: I2f6817ca198bf923671a7aa67e956e5477d71848\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22385\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f43c654ad0dcb11b2738bbfac9246d09bb1949e5", "tree": "1d1f74d771dc2e8e8a67dab985945c00f68e0097", "parents": [ "0ecbacbfca7f919f1780f5062c775d94c7869d81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 17:47:28 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:44:17 2017 +0000" }, "message": "spi25: Integrate 4BA support\n\nAllow 4-byte addresses for instructions usually used with 3-byte\naddresses. Decide in which way the 4th byte will be communicated\nbased on the state of the chip (i.e. have we enabled 4BA mode)\nand a new feature bit for an extended address register. If we\nare not in 4BA mode and no extended address register is available\nor the write to it fails, bail out.\n\nWe cache the state of 4BA mode and the extended address register\nin the flashctx.\n\nChange-Id: I644600beaab9a571b97b67f7516abe571d3460c1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22384\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ecbacbfca7f919f1780f5062c775d94c7869d81", "tree": "2f84f6406d00bc89dd13dfeff3e69f77671a8f9e", "parents": [ "a3140d0b18058610a2694fc3592031a849b0c92a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 16:50:43 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:42:49 2017 +0000" }, "message": "spi25: Use common code for nbyte read/write and block erase\n\nIntroduce spi_prepare_address() and spi_write_cmd() and use them in\nnbyte_program, nbyte_read and block-erase procedures. The former\nabstracts over the address part of a SPI command to make it exten-\nsible for 4-byte adressing. spi_write_cmd() implements a WREN + write\noperation with address and optionally up to 256 bytes of data. It\nprovides a common path to reduce overall redundancy.\n\nAlso, reduce the polling delay in spi_block_erase_c4() from 500s to\n500ms as the comment suggests.\n\nChange-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22383\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a3140d0b18058610a2694fc3592031a849b0c92a", "tree": "194083a9889bb76a70cb447a14660d6ec449506c", "parents": [ "c8801734727e1e510cbd99e305007b73f9f57e93" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 11:20:58 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:41:38 2017 +0000" }, "message": "spi25: Introduce spi_simple_write_cmd()\n\nspi_simple_write_cmd() executes WREN plus a single byte write and polls\nWIP afterwards. It\u0027s used to replace current spi_erase_chip_*() imple-\nmentations.\n\nChange-Id: Ib244356fa471e15863b52e6037899d19113cb4a9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22382\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "c8801734727e1e510cbd99e305007b73f9f57e93", "tree": "84c6914f12ad1f4e1b00ae5bc76d159951233af0", "parents": [ "095522cceca4aede4b4a5e8cd74cbbd8f63e1116" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 01 18:19:43 2017 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:37:06 2017 +0000" }, "message": "internal: Only build on x86 and mipsel\n\ninternal_init() explicitly fails on everything but x86 and mipsel.\nInstead, we can just never build the internal programmer on other\narchitectures and drop a lot of #if boilerplate.\n\nChange-Id: I672ddab0415df3baa49ff39a1c9db1b41d8143a4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22671\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "095522cceca4aede4b4a5e8cd74cbbd8f63e1116", "tree": "dacb6975b940eec5772060afe2af35bfc9adc090", "parents": [ "19eb0792b8439198d7ef0077b8f79f275fa39a9d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 01 18:33:02 2017 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:36:38 2017 +0000" }, "message": "Move endianness definitions and provide it inside Makefile\n\nAdd an `endiantest.c` similar to `archtest.c` to provide the endianness\ninside the Makefile. The __FLASHROM_(LITTLE|BIG)_ENDIAN__ definitions\nhad to move from `hwaccess.h` into `platform.h`, therefor. This will\nbe used to decide whether to build the internal programmer in a follow-\nup.\n\nChange-Id: I55dcf5a88da48f885cda9ad89ab87395d895a891\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22670\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "19eb0792b8439198d7ef0077b8f79f275fa39a9d", "tree": "b2d1e9a9e53150c48828f2e38afbf6264d48b6ac", "parents": [ "3083ed90c62e9516615e2322f23ca798e5124a8f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 13 00:44:45 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:30:05 2017 +0000" }, "message": "ichspi: Fix 100 series PCH (Skylake) support\n\nPretty subtle missing `else` made flashrom treat Skylake like older\nchipsets.\n\nChange-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/22832\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3083ed90c62e9516615e2322f23ca798e5124a8f", "tree": "172265fd17a3d1c1184215bf898248505c92d7e0", "parents": [ "57a3b731daa8f0a6ed9d193b1b9e03216b66a802" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue May 02 13:25:56 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Dec 11 18:20:59 2017 +0000" }, "message": "flashchips: Add ISSI IS25LP128 and IS25WP128\n\nIS25LP128 is the 3.3V variant, IS25WP128 is the 1.8V variant.\n\nTested read, erase, and write using Dediprog SF600 on each.\n\nChange-Id: Ia1c7a9a950043c30b7525196e03ee394689e89a5\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22784\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "57a3b731daa8f0a6ed9d193b1b9e03216b66a802", "tree": "3ff81dcdd9f0991d076757b16979e8ba5b792ed4", "parents": [ "48729d31a6d5dcf9ed887df332518594e1ac6310" ], "author": { "name": "Martin Schiller", "email": "ms@dev.tdt.de", "time": "Thu Nov 23 06:24:57 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Dec 11 03:37:30 2017 +0000" }, "message": "Do not stop probing for flashchips after map_flash() failed\n\nInstead, continue probing the next chip.\n\nThis fixes the problem that flashrom aborts probing for\nflashchips if one big flashchip (e.g. 32M/64M) can\u0027t be mapped\nbecause of activated CONFIG_STRICT_DEVMEM kernel option.\n\nChange-Id: Iaecfb6d30a5152c8c4b5d2804efacac85fc615f9\nSigned-off-by: Martin Schiller \u003cms@dev.tdt.de\u003e\nReviewed-on: https://review.coreboot.org/22685\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48729d31a6d5dcf9ed887df332518594e1ac6310", "tree": "4cbcbcd595c72368d4058ee1cff1e23c7664a3ef", "parents": [ "b007278fac68f6c6f4926df336fd59a78404bbb8" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Fri Dec 08 14:44:07 2017 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 10 00:13:07 2017 +0000" }, "message": "flashchips: Mark W25Q128.W as tested\n\nTested read, erase, and write using W25Q128FWSIG and Dediprog SF600.\n\nChange-Id: Id0ef331ad3b3a8ab05a9472f3053f76c0789b1f9\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22790\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b007278fac68f6c6f4926df336fd59a78404bbb8", "tree": "a4b219351b967333b4486a6fac71f03dfa1729cf", "parents": [ "97a90497a7d0df5076b4412c3e995a7e4a2ff8cc" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 06 21:02:57 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 09 23:11:13 2017 +0000" }, "message": "flashchips: Add MX25L6473F\n\nJust another chip sharing the same ID. Tested by somebody on IRC.\n\nChange-Id: Ibea956e48e10fda91930b65b3bf3b3ae4ad13f63\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22759\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "97a90497a7d0df5076b4412c3e995a7e4a2ff8cc", "tree": "f590cd7fd6b2ab4cd4a6b45c17ff6dddf130fe7c", "parents": [ "6891709a1f04a78bc45ad4174f4416f24169a020" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 01 18:19:43 2017 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 09 22:42:55 2017 +0000" }, "message": "internal: Fix warnings about unused constants\n\nBy adding more #if guards, fix warnings about unused constants that\nare enabled by default in newer GCC versions.\n\nChange-Id: Ib3b6d7c0c2fadc4faeab971673bfadb1a6d25919\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22669\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "6891709a1f04a78bc45ad4174f4416f24169a020", "tree": "e0565fb6640d919bf9278ffa9fbe86abc038298e", "parents": [ "bbf0dbde3855a58f7324dedb81fdcce0f99c1c87" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Nov 13 20:12:58 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Dec 01 00:30:15 2017 +0000" }, "message": "README: Update packaging section for Git repositories\n\nChange-Id: I8d9c56be8c1381b175ce7695c53f31b1767d9d17\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22454\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "bbf0dbde3855a58f7324dedb81fdcce0f99c1c87", "tree": "081df1b795f34cfe65e4d436dc076f967af10c8e", "parents": [ "1f33cb58001f95c3de69f037acae6f72baddca2b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 19 16:29:45 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Nov 21 22:29:27 2017 +0000" }, "message": "chipset_enable: Mark SiS 630 as tested OK\n\nTested on an Elitegroup P6STMT with an SST39SF020A parallel flash [1].\n\n[1] https://mail.coreboot.org/pipermail/flashrom/2017-November/015193.html\n\nChange-Id: If8cc2af262e392bfba326a62c1a48c658c7d6ce8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22522\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1f33cb58001f95c3de69f037acae6f72baddca2b", "tree": "863f297f755279f16fbb4f4e2615b01279ae9733", "parents": [ "22f2dc5ec0b13a413a9ce42a5836ec2aa3b1abfc" ], "author": { "name": "Keno Fischer", "email": "keno@juliacomputing.com", "time": "Sun Nov 15 14:58:25 2015 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Nov 16 06:28:01 2017 +0000" }, "message": "linux_spi: Dynamically detect max buffer size\n\nRead max buffer size from sysfs if available.\n\nChange-Id: Ic541e548ced8488f074d388f1c92174cad123064\nSigned-off-by: Keno Fischer \u003ckeno@juliacomputing.com\u003e\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22441\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "22f2dc5ec0b13a413a9ce42a5836ec2aa3b1abfc", "tree": "9b496559cd9503628b42f19c5789400e0bcc5373", "parents": [ "1f081530b60ee805532f106f59cc33973e160481" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Aug 31 16:14:22 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 05 22:33:41 2017 +0000" }, "message": "ichspi: Disable software sequencing by default for Skylake\n\nSkylake is a mess, especially with coreboot. We have now a present and\nconfigured software sequencing interface with SCGO supposedly being\nreadonly (Apollo Lake has that feature and a strap documented, Skylake\nbehaviour might be the same). As we can\u0027t easily check if it\u0027s read-\nonly, just enable hardware sequencing by default (even if the software\nsequencing interface seems usable).\n\nChange-Id: I8a13fb9c3ca679b3f7d39ad1dc56d5efdc80045b\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/22274\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1f081530b60ee805532f106f59cc33973e160481", "tree": "ebb7155eaeda5f891a435d4087e6532ccb8a15c5", "parents": [ "8b2152d54a67e4139525ce49aefe1a6d0e41b85c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 15:01:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 05 14:36:50 2017 +0000" }, "message": "spi25_statusreg: Return defined value on failed RDSR\n\nThe interface of spi_read_status_register() is broken and can\u0027t return\nerrors. Let\u0027s not return random stack data at least.\n\nChange-Id: I714b20001a5443bba665c2e0061ca14069777581\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22017\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8b2152d54a67e4139525ce49aefe1a6d0e41b85c", "tree": "6b2b15743a972873d96c12591767780cdc905539", "parents": [ "f268d8b2d6fe5ea5ab0e0e2c5eec02c16d023ce5" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Aug 31 13:18:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 03 16:53:36 2017 +0000" }, "message": "ichspi: Fix software sequencing for Skylake\n\nTwo occurences of ICH9_REG_OPMENU were overlooked and not replaced,\nrendering the software sequencing unusable on Skylake.\n\nChange-Id: I16eebcf37ab8ba39b02f33135535552e380b0b92\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/22273\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "f268d8b2d6fe5ea5ab0e0e2c5eec02c16d023ce5", "tree": "e1bc61384072608248941a03ed03b1c0507816be", "parents": [ "e1a960e0a520263b380d898459b6909a8d7f59c5" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Thu Oct 26 18:45:00 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 03 16:50:17 2017 +0000" }, "message": "Fix standalone ich_descriptor_tool compilation with MinGW and DJGPP\n\nTARGET_OS as well as EXEC_SUFFIX were only set when called via the\nmain makefile and even then __USE_MINGW_ANSI_STDIO was not set\nfor MinGW.\n\nWhile at it, also replace the hardcoded gnu_printf printf format\nattribute with __MINGW_PRINTF_FORMAT which is set according to\n__USE_MINGW_ANSI_STDIO respectively.\n\nChange-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21838\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e1a960e0a520263b380d898459b6909a8d7f59c5", "tree": "afbbff719b0b4dec023f26d8b074ed90be1c6c3a", "parents": [ "4343e7d44006dcda2ea76b0e7625837832141539" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Thu Oct 19 14:54:44 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 21 02:15:58 2017 +0000" }, "message": "Use bzip2 when making a tarball\n\nTarballs on download.flashrom.org are generally packaged using bzip2, so\nwe may as well be internally consistent.\n\nChange-Id: Ib9fb1ea6d5994cd0285ce8db9675640fae992773\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/22116\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4343e7d44006dcda2ea76b0e7625837832141539", "tree": "18f07dec45cafc53621d1af74c33ae60e4169916", "parents": [ "2ec33f9e6a303a729ceb164d34a85563b6e2c1b0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 10 17:38:07 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 20 19:27:08 2017 +0000" }, "message": "fixup! nicintel_eeprom: Support for I210 emulated EEprom\n\nFix is_i210(), add a comment and break an overlong line.\n\nChange-Id: I5d3f71e4e0f77cc8793e7f395baf69e1fad930a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/21934\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "2ec33f9e6a303a729ceb164d34a85563b6e2c1b0", "tree": "05b5cd18d0a9d7393dcefdfc5048f5c66bf91b0d", "parents": [ "615ba1849c1ad67503cf000c9fea311962175525" ], "author": { "name": "Michael Zhilin", "email": "mizhka@gmail.com", "time": "Fri Dec 02 14:41:26 2016 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 19 15:17:05 2017 +0000" }, "message": "Fix serprog on FreeBSD\n\nUsing serprog on FreeBSD to read an SPI flash (MX25L6406) via an\nArduino Nano V3 with flashrom hangs after 5 seconds while reading. The\nproblem is that kernel method \"ttydisc_rint\" ignores some bytes. It\nhappens due to enabled IEXTEN local flag of termios. TTY cuts a few\nbytes, Arduino reads 11264 bytes, but flashrom gets only 11244 bytes\nand waits for the remaining 20 bytes.\n\nThe fix is simple: turn off the IEXTEN local flag.\n\nTested on Arduino Nano V3 + FreeBSD 12-CURRENT.\n\nChange-Id: I7aa6a283d523c544d9b8923cd4c622bf08c0fb3f\nSigned-off-by: Michael Zhilin \u003cmizhka@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21919\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "615ba1849c1ad67503cf000c9fea311962175525", "tree": "94c2b9ad0d8f1e486c2b5ac41acd0b65ebd7225a", "parents": [ "beaefe0f96758297d013bd48b598225410b44e34" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Thu Jun 15 15:28:27 2017 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 19 15:14:30 2017 +0000" }, "message": "serial: Support custom baud rates on linux\n\nThe function to do this is contained in custom_baud.c because\nof broken include stuff.\n\nChange-Id: I2a20f9182cb85e7bce5d6654a2caf20e6202b195\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20224\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "beaefe0f96758297d013bd48b598225410b44e34", "tree": "044fcb25328c80d0c57a9bc5b07cf60be9810ab7", "parents": [ "af111e25a9d00c3d99eae6196c616461cfdfb193" ], "author": { "name": "dhendrix", "email": "dhendrix@chromium.org", "time": "Sun Sep 03 18:06:53 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Oct 17 06:49:59 2017 +0000" }, "message": "Move get_layout() from flashrom.c to layout.c\n\nChange-Id: Ic67cf53abddc0aa905674acbcde717d9aed2f66e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21367\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "af111e25a9d00c3d99eae6196c616461cfdfb193", "tree": "b3b5ca8fc36a572ece5db17ffa79e2a86e095a97", "parents": [ "e29591dfb30fa8fc2bec930cf3bebe733469fb86" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 08 05:44:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 16 16:36:49 2017 +0000" }, "message": "Fix ID of ST M25P05\n\nThe (old) ST (now Micron) M25P05 does only support RES for identification.\nUnfortunately, the vendor datasheet states the same ID as for the M25P10\n(0x10) and thus flashrom has treated these two as evil twins in the past.\nHowever, real hardware confirmed that the real ID of this chip is 0x05.\n\nChange-Id: Idc75f8cb98e7ef0c47c4527cedcc4da3723bd779\nSigned-off-by: Serge Vasilugin \u003cvasilugin@yandex.ru\u003e\nTested-by: Serge Vasilugin \u003cvasilugin@yandex.ru\u003e\nReviewed-on: https://review.coreboot.org/21920\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e29591dfb30fa8fc2bec930cf3bebe733469fb86", "tree": "846fef6ac949d75a035b21ce542f858d9c937c36", "parents": [ "5bdb87e61f154524f37e249fa6ddae893840b9e5" ], "author": { "name": "Timothy Pearson", "email": "tpearson@raptorengineering.com", "time": "Sat Aug 27 15:43:00 2016 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 13:43:28 2017 +0000" }, "message": "Initial MX66L51235F support\n\nChange-Id: I94bee2832469d2df399a09e2f535a107edaec3e7\nSigned-off-by: Timothy Pearson \u003ctpearson@raptorengineering.com\u003e\nReviewed-on: https://review.coreboot.org/19856\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "5bdb87e61f154524f37e249fa6ddae893840b9e5", "tree": "ec2140efe09446bbdce0c046d77b0b2be58cd698", "parents": [ "199ab391145497645967b7629c0f74b1bdd2d46d" ], "author": { "name": "Timothy Pearson", "email": "tpearson@raptorengineering.com", "time": "Sat Aug 27 14:02:50 2016 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 13:38:24 2017 +0000" }, "message": "Initial MX25L25635F support\n\nChange-Id: I292e12d92cdf3961b8d47492a1d5679ff1ea21ce\nSigned-off-by: Timothy Pearson \u003ctpearson@raptorengineering.com\u003e\nReviewed-on: https://review.coreboot.org/19855\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "199ab391145497645967b7629c0f74b1bdd2d46d", "tree": "0a6c99ad32fd78d48c62037068151cf86a0d4eb7", "parents": [ "cc20a9b08e849437a58402f4a64d63d3710684af" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:33:44 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:37:34 2017 +0000" }, "message": "4BA: Add Micron N25Q/MT25QL 32MB and 64MB 3V SPI flash\n\nUse direct 4-byte address commands.\n\nChange-Id: I3c130c5ecf4bcc7cf3b34257cb5fc3df523ce08b\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20511\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cc20a9b08e849437a58402f4a64d63d3710684af", "tree": "01975202af6298ab6c357532b0e1d6e1d77715b8", "parents": [ "d94d254262594b912c65511b5d0675c6ab900d60" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:17:18 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:37:03 2017 +0000" }, "message": "4BA: Allow disabling 4-byte address mode for SPI flash\n\nThis allows us to support flash chips in any of the following\nconfigurations, regardless of whether the chip powers up in 3-byte or\n4-byte address mode.\n\n- standard commands with extended address register (*_4ba_ereg) or\n direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba \u003d\n spi_exit_4ba_*)\n- standard commands (*_4ba) or direct commands (*_4ba_direct) in\n 4-byte address mode (.set_4ba \u003d spi_enter_4ba_*)\n- direct commands (*_4ba_direct) in either address mode (.set_4ba \u003d\n NULL)\n\nChange-Id: I0b25309d731426940fc50956b744b681ab599e87\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20510\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d94d254262594b912c65511b5d0675c6ab900d60", "tree": "6e972f84e4bc74db8b76292aadbcc52fd1fba3d7", "parents": [ "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:02:18 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:55 2017 +0000" }, "message": "4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressing\n\nChange-Id: I553e7fb5028f35e14a3a81b3fa8903c1b321a223\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20509\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e", "tree": "0da033666d79e9b3dc471762d1b02ee41a7a7a8d", "parents": [ "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:03 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:08 2017 +0000" }, "message": "4BA: Support for new direct-4BA instructions + W25Q256.V update\n\nLarge flash chips usually support special instructions to work with\n4-bytes address directly from 3-bytes addressing mode and without\ndo switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)\nand 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these\ninstructions are supported by all large flash chips. Some chips\nsupport 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends\non the manufacturer of the chip.\n\nThis patch provides code to use direct 4-bytes addressing instructions.\n\nThis code should work but it tested partially only. My W25Q256FV has\nsupport for 4BA_Read (13h), but doesn\u0027t have support 4BA_Program (12h)\nand 4BA_Erase instructions. So, direct 4BA program and erase\nshould be tested after.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashchips.c\n+ modified definition of Winbond W25Q256BV/W25Q256FV chips\n\nflashrom.c\n+ modified switch to 4-bytes addressing for direct-4BA instructions\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for read/write/erase directly with 4-bytes address (from any mode)\n\nChange-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20508\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab", "tree": "f3480e7191c83965a9ab97d429f090e07f30a552", "parents": [ "aa6c37444c1d1a5944ea8bb3912bb0efe27dffce" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:02 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:33:37 2017 +0000" }, "message": "4BA: Support for 4-bytes addressing via Extended Address Register\n\nOn some flash chips data with addresses more than 24-bit field\ncan address may be accessed by using Extended Address Register.\nThe register has 1-byte size and stores high byte of 32-bit address.\nThen flash can be read from 3-bytes addressing mode with writing\nhigh byte of address to this Register. By using this way we have\naccess to full memory of a chip. Some chips may support this method\nonly.\n\nThis patch provides code use Extended Address Register.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashrom.c\n+ modified switch to 4-bytes addressing to support extended address register\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for write Extended Address Register\n+ functions for read/write/erase with Extended Address Register\n\nChange-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20507\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aa6c37444c1d1a5944ea8bb3912bb0efe27dffce", "tree": "cd9f0a67153f1b53dc067c10d7db09fc102bd75c", "parents": [ "9912718de18e455e16d26458aca4eac37f792aa2" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:01 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:31:22 2017 +0000" }, "message": "4BA: Winbond W25Q256.V chip (32MB) declaration, 4-bytes addr mode\n\nHere is the definition of new W25Q256xV chip with new functions pointers\nfor 4-bytes addressing reads and writes. Erase functions pointers are\nchanged in their old places. New feature flags for 4-bytes mode added.\n\nPatched files\n-------------\nflashchips.c\n+ added definition for Winbond W25Q256BV/W25Q256FV chips\n\nChange-Id: I90226f453f8147ae5ac7dbbef7549ee3bfacc3d6\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013201.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20506\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Lijian Zhao \u003clijian.zhao@intel.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9912718de18e455e16d26458aca4eac37f792aa2", "tree": "d447b47feb1d0f497c17ab6941e0b4c9afbed5cb", "parents": [ "b1f88360fc806ee69d7cf1b9404b3977bc53aace" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:00 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:30:26 2017 +0000" }, "message": "4BA: Flashrom integration for the 4-bytes addressing extensions\n\nThis patch integrates code of the previous patch into Flashrom\u0027s code.\nAll the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program\nand spi_byte_program. After this patch then are not static and can be called\nby their pointers saved in flashchips array. Also I added to flashrom.c some\ncode to switch a chip to 4-bytes addressing mode. And one error message is\ncorrected in spi.c because it\u0027s not suitable for 32-bit addresses.\n\nPatched files\n-------------\nflash.h\n+ added set of 4-bytes address functions to flashchip structure definition\n\nflashrom.c\n+ added switch to 4-bytes addressing more for chips which support it\n\nserprog.c\n+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read\n\nspi.c\n+ fixed flash chip size check in spi_chip_read\n\nspi25.c\n+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked\n+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked\n+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1\n\nConflicts:\n\tserprog.c\n\nChange-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20505\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b1f88360fc806ee69d7cf1b9404b3977bc53aace", "tree": "9c2b6aac3c378702d1596b8eb506f87b180638a0", "parents": [ "50a5660c9c11c77c794783cd9a3343bc3ff07b6e" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 10:10:17 2017 +0000" }, "message": "fixup! 4BA: Basic support for 4-bytes addressing mode extensions\n\nFix some whitespace, and braces. Remove sector size from comments that I\ncould not verify.\n\nChange-Id: I4faaa036fea744135fa37f405686fb9fd0882806\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/21947\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "50a5660c9c11c77c794783cd9a3343bc3ff07b6e", "tree": "7095a74f39788084a14c3657bc3b868f923f5340", "parents": [ "f4d7772cee806d68a06db5394ab85a6e76904e88" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 14 00:46:41 2017 +0000" }, "message": "4BA: Basic support for 4-bytes addressing mode extensions\n\nIf flash chip is switched to 4-bytes addressing mode then all\nread/erase/program instructions will be switched from 3-bytes mode\nto 4-bytes mode. Then well known instructions like 03h (Read),\n02h (Program) and 20h,52h,D8h (Erase) will become one byte longer\nand accept 4-bytes address instead of 3-bytes.\n\nThis patch provides support for well known instructions in 4-bytes\naddressing mode. Also here is the code to enter 4-bytes addressing\nmode by execute the instruction B7h (Enter 4-bytes mode).\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nMakefile\n+ added spi4ba.c\n\nAdded files\n-----------\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for enter 4-bytes addressing mode\n+ functions for read/write/erase in 4-bytes addressing mode\n\nChange-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20513\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f4d7772cee806d68a06db5394ab85a6e76904e88", "tree": "355098516d28d14ac5f03bd7b4eff3848a9c4ac9", "parents": [ "63bf222cbaa59b7552b9a268a878350b0919117d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Fri Oct 06 02:02:46 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 06 08:36:00 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nwithout the upcache there is no \"offline\" version (yet).\n\nChange-Id: Iac3bf11fbd55cfa034ef8af04ef90fe57182ee2b\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "63bf222cbaa59b7552b9a268a878350b0919117d", "tree": "9c6c2b8637d5f25bbdb7b7b8ec30250416ab6f78", "parents": [ "f3f996e33ddae9bed8d29f27c9f81516478e65ce" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 03:12:09 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 06 08:35:46 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nrefine the pre-push hook:\n - get rid of the concept of precious brances - all of them on the\n upstream repos are precious (this is a change in the face of\n using gerrit instead of a native git repository for staging purposes)\n - likewise, only allow new versioned stable branches and no feature\n branches there\n\nChange-Id: I1d4b4a7ef2673cabee980ec4a7d7d5fbebdcaed1\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21834\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f3f996e33ddae9bed8d29f27c9f81516478e65ce", "tree": "ebc5236fe001d0b657cb1158490dcca2c5f562ad", "parents": [ "3a937b77320f24b648306d90063df39cd08cf633" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 02:56:31 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:46:33 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - update the commit-msg to check for duplicate signoffs/acks\n\nChange-Id: Ia36147e673cceb6d175884b40d4bdd00015b96dc\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21833\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3a937b77320f24b648306d90063df39cd08cf633", "tree": "c9bdf39db6adebb02195aa922613423851c75f36", "parents": [ "68b5f00930132c12c98705e7728765171142d2ef" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 19:15:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:45:21 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - update the commit-msg hook to the latest one provided by Gerrit.\n However, disable the (new) code that would avoid adding Change-IDs\n to fixup/squash commits as needed on the staging branch\n\nChange-Id: I2f2d7ae58dcd7d3e55959e18fe664df10bc3cc41\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21832\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "68b5f00930132c12c98705e7728765171142d2ef", "tree": "2adfd0c736509a4ab2974f011dd16f379fbe8098", "parents": [ "fa25bc3cd433e2cdbf8d0922a29be71815a072cd" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 16:52:55 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:45:08 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - wrap a line in the hook installer. The line still exceeds our\n maximum limit by two chars but it makes no sense to break\n apart the one long argument IMHO\n\nChange-Id: I0e931fbb5902d2714d5399c1d1bfac0de35523bb\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21831\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa25bc3cd433e2cdbf8d0922a29be71815a072cd", "tree": "c15a00533e57c120f7700284f991af4a9f51aa0f", "parents": [ "5bf6b855d4083070390b5c0eb03bca678090d75d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 03:47:26 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:43:05 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - exploit Make\u0027s -include statement to simplify execution flow\n - expand and refine respective comment to better describe and\n match the new behavior\n\nChange-Id: I0c66f2508cc754cf9219211a06d6f305a32c422d\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21830\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5bf6b855d4083070390b5c0eb03bca678090d75d", "tree": "ee7e58ceb379e20056a6a393f97b749ab29acee0", "parents": [ "8eb1df69ab22829d61366e7d8e4eca6d7ed13657" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 03:46:51 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:41:23 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nRename getrevision\u0027s local_revision function to just revision.\nAll revisions are local in git and we certainly wont go back to\na non-distributed VCS :)\n\nChange-Id: I6689ac24077b3981b471ed69de7cc3ef79d435b1\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21829\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "8eb1df69ab22829d61366e7d8e4eca6d7ed13657", "tree": "db7a20661678df0e5aa1e724f53e55241dd13f00", "parents": [ "9620912607d5e99650624f74545268bba0f310ca" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 16:45:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:40:08 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nNote the non-strict POSIX compatibility in getrevision.sh and a add missing full stop*.* ;)\n\nChange-Id: Ia60186f783067ba084439a8ef701dc8f4c0072f0\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21828\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9620912607d5e99650624f74545268bba0f310ca", "tree": "d5fdf853e610a0422e5c64284d68caf397a653a5", "parents": [ "2dc5d294004f5d3ec37cc7bfd5d49ce1a41bf215" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 16:41:35 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:39:25 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\n - make version string generation independent of the actual VCS\n used by not generating \"unknown\" in the makefile but letting\n getrevision do that\n - make hook installation independent of version string generation\n since they have nothing to do with each other and there are no\n synergies anymore\n\nChange-Id: Iedc9df4c033a70447b8b1b65c83764c769b02c3f\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21827\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2dc5d294004f5d3ec37cc7bfd5d49ce1a41bf215", "tree": "e9a4ac8b9e11e5644f7f7f19788f6c1f33912949", "parents": [ "e4136854f18adcf3e753ebe6a2cc2cc9b9e43201" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 02:18:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:37:35 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nUse a more generic file name for the exported VCS data.\n\nChange-Id: Ie57b20dc014ba44ded5783bdb432eb7d0e0e28ad\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21826\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e4136854f18adcf3e753ebe6a2cc2cc9b9e43201", "tree": "6c7f39e023d2c4b636f5a4e906a2f3cbb7a4beac", "parents": [ "60f7a221e080e1847b56bd8aa03451c2459efc1c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 15:57:25 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Oct 05 10:37:15 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nFix broken/one-off loop to restore file dates.\nExplain what the sed program actually does because it is non-trivial.\n\nChange-Id: Iff4021be49a9fab208b619c555b9f9e81f671ab8\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21825\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "60f7a221e080e1847b56bd8aa03451c2459efc1c", "tree": "30e22a28114d451775b7f5f81406e3d6a14cb576", "parents": [ "f0cbbb05c909340607a5e7a14e80523752b6434c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 15:45:06 2017 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Oct 05 04:10:11 2017 +0000" }, "message": "fixup! Convert flashrom to git\n\nFix broken export\n\nChange-Id: I9d0fe93291de81b4d303589fd01565f429a61e9a\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21824\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f0cbbb05c909340607a5e7a14e80523752b6434c", "tree": "bd0f695ebf6db71d3fb111c5f65cfa681ce9c065", "parents": [ "79d838d31696542105a4185758f23db13d8ea045" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Sun Oct 01 00:49:05 2017 +0200" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@gmx.at", "time": "Wed Oct 04 01:21:12 2017 +0000" }, "message": "Add modification date to manpage header instead of the section\n\n\"System Manager\u0027s Manual\" or similar is way less interesting.\n\nChange-Id: I45c5d6a2316c51a57a49fd010682dc3f0f915382\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@gmx.at\u003e\nReviewed-on: https://review.coreboot.org/21822\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "79d838d31696542105a4185758f23db13d8ea045", "tree": "20162a2ada71c7ece57f96d9790ce8c7b791bb5c", "parents": [ "75a2a79aebe9ffd0bcdb5f8d014d9e5583973014" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Wed Sep 27 09:25:34 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Oct 03 00:23:34 2017 +0000" }, "message": "fixup! nicintel_eeprom: Support for I210 emulated EEprom\n\nA couple of C99-style variable declarations within loops are causing\ncompilation failures on some systems (gcc 4.9.2-10 on Raspbian). This\nmoves them to make gcc happy.\n\nChange-Id: Ib7ad5a69244e462f84eae93df9e841716e089b31\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21702\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "75a2a79aebe9ffd0bcdb5f8d014d9e5583973014", "tree": "6ea9442fc25620fb9fe0bf887501a4a715e13610", "parents": [ "26d33d2be2851ce0ac16252bc0997eb67068fbed" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Thu Mar 23 23:38:04 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:14:28 2017 +0000" }, "message": "nicintel_spi: Define BIT() macro\n\nReplace bit shits with BIT() macro. This improves the readability of the\ncode.\n\nChange-Id: I30315891f18d4d5bfbc247bb9012560479afab90\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21432\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "26d33d2be2851ce0ac16252bc0997eb67068fbed", "tree": "2a70468056dfd8ca894b8ebee80e6890309eea79", "parents": [ "9fe1fb71c7e53e4f44d633fe52dc33453b36848b" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Wed Mar 22 14:30:52 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:06:05 2017 +0000" }, "message": "nicintel_spi: Support for I210/I211 cards\n\nImplements I210 \"raw\" flash access as detailed in:\nhttp://www.intel.com/content/www/us/en/embedded/products/networking/i210-ethernet-controller-datasheet.html\n\nUnfortunately, most of the time the card is in Secure Mode, which means\nthat the raw access is not available. But his should be pretty useful\nfor bringing up boards.\n\nChange-Id: I8598ab21297b85dcae1e650a168043aa4cc15c10\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21430\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "9fe1fb71c7e53e4f44d633fe52dc33453b36848b", "tree": "726c76de3e2b36ea50bb50ff9e87f75aeecd3d21", "parents": [ "7b629bcde47e18d094e496fb8ae537272ead0998" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Thu Mar 23 15:11:22 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:05:16 2017 +0000" }, "message": "nicintel_eeprom: Support for I210 emulated EEprom\n\nOn the I210 family there is no MAC EEprom, instead there is a big flash\n(typically around 16Mb) with contents of the old MAC plus other stuff.\nThere is an interface to program the whole flash, but once it is\nprogrammed it enters a \"Secure Mode\" that disables the interface.\n\nLuckily, the section with the MAC can still be updated via the EEprom\ninterface. This patch adds support for this interface.\n\nroot@qt5022-fglrx:~# ./flashrom -p nicintel_eeprom:pci\u003d01:0.0 -w kk.raw -V\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at https://flashrom.org\n\nflashrom was built with libpci 3.4.1, GCC 5.3.0, little endian\nCommand line (5 args): ./flashrom -p nicintel_eeprom:pci\u003d01:0.0 -w kk.raw -V\nCalibrating delay loop... OS timer resolution is 1 usecs, 1856M loops per second, 10 myus \u003d 10 us,\n100 myus \u003d 102 us, 1000 myus \u003d 1017 us, 10000 myus \u003d 10044 us, 4 myus \u003d 4 us, OK.\nInitializing nicintel_eeprom programmer\nFound \"Intel I210 Gigabit Network Connection\" (8086:1533, BDF 01:00.0).\nRequested BAR is of type MEM, 32bit, not prefetchable\nRequested BAR is of type MEM, 32bit, not prefetchable\nThe following protocols are supported: Programmer-specific.\nProbing for Programmer Opaque flash chip, 0 kB: Found Programmer flash chip \"Opaque flash chip\"\n(4 kB, Programmer-specific) on nicintel_eeprom.\nFound Programmer flash chip \"Opaque flash chip\" (4 kB, Programmer-specific).\nReading old flash chip contents... done.\nErasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W\nErase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I553f33e5dcb4412d682fc93095b29bcfed11713c\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21431\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7b629bcde47e18d094e496fb8ae537272ead0998", "tree": "3c44a9d573fb61ca483054a845722e051558aefd", "parents": [ "8681df128708a548e64865bb6fd8f6cd957e061d" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Wed Mar 22 14:08:31 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:03:42 2017 +0000" }, "message": "sb600spi: Add support for Merlin Falcon Chipset\n\nThis patch has been tested on a board similar to AMD Bettong.\n\n00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus\nController [1022:790b] (rev 4a)\n00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC\nBridge [1022:790e] (rev 11)\nroot@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom\n\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at\nhttps://flashrom.org\n\nCalibrating delay loop... OK.\ncoreboot table found at 0x9ffd6000.\nFound chipset \"AMD FP4\".\nEnabling flash write... OK.\nFound Micron/Numonyx/ST flash chip \"N25Q128..1E\" (16384 kB, SPI)\nmapped at physical address 0x00000000ff000000.\nReading old flash chip contents... done.\nErasing and writing flash chip... Erase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21429\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8681df128708a548e64865bb6fd8f6cd957e061d", "tree": "835c820539d876f6bbe8b1f3430caf64d3a0d29f", "parents": [ "7a8305f1bd452a74a1679e75383f888b48e67f4d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 20:53:29 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 03 20:29:24 2017 +0000" }, "message": ".gitignore: Add Doxygen dir `libflashrom-doc/`\n\nChange-Id: Id25d05cdf6107cc7a99b94a8523e23bd8698c2d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/20811\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7a8305f1bd452a74a1679e75383f888b48e67f4d", "tree": "233c0b969a71ffc196466e5ff4138060a2654bc1", "parents": [ "0eb00d4e77d3ad0fceef62b0d2ea69aa4835aa8e" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Fri Sep 01 20:16:58 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 03 19:33:08 2017 +0000" }, "message": "ich_descriptors: Use MAX_NUM_FLREGS for entries[]\n\n5 regions made sense in 2013 when this bit of code was originally\nwritten. MAX_NUM_FLREGS is now used to keep track of the max number of\nflash regions and is \u003e5 since Sunrise Point.\n\nChange-Id: Idb559e618369fecf930724a7c1c84765247f3e38\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/21338\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0eb00d4e77d3ad0fceef62b0d2ea69aa4835aa8e", "tree": "9860c6d1b56afd370a1fdeaa7a43511ac96aa095", "parents": [ "a5216367d5640f07d58a6549fa6df86d91daff1a" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Fri Sep 01 20:02:36 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 03 19:32:52 2017 +0000" }, "message": "Move ich_layout from layout.h to ich_descriptors.h\n\nThis moves the ich_layout declaration from one header to another. This\nwill avoid a circular dependency when we update the entries[] member in\nthe follow-up patch to use MAX_NUM_FLREGS which is defined in\nich_descriptors.h.\n\nChange-Id: I08006f1f7c9ccdd17a9a6d74881ed2c8541d4de1\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/21337\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "aa91d5c16858cb400cc61e8a759838f645e3f314", "tree": "163b27954a680ea02f945ee383f8dbc7c1cc03c8", "parents": [ "a1bccd88c3c8c0041795b96faef2cb4179bfbd7c" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Aug 19 17:04:21 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 21 21:21:47 2017 +0000" }, "message": "ichspi: \"Fix\" access permission reporting for regions \u003e 7\n\nCan\u0027t find bits that tell us the actual permissions in charge. So report\nthem as unknown.\n\nChange-Id: Ib73f95e0348f5c6d89988e3ea3529af0ec3b23a6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/21106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a1bccd88c3c8c0041795b96faef2cb4179bfbd7c", "tree": "f7dd8abd576d25c606508fa2ea6b4007b5b3d291", "parents": [ "4d440a7c4102faae21b16204e667ea74c1dc8e52" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Tue Aug 08 23:28:54 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 19 20:34:34 2017 +0000" }, "message": "chipset_enable: Mark Braswell as tested\n\nReported by Uwe Vieweg:\nhttps://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html\n\nChange-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20923\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4d440a7c4102faae21b16204e667ea74c1dc8e52", "tree": "7122caef5133c365278a24d93cb7991a49aa36ae", "parents": [ "8e76230dfbcc7720c5565a70daff650496556702" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Aug 15 11:26:48 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Aug 16 17:01:59 2017 +0000" }, "message": "Include \u003csys/types.h\u003e wherever ssize_t is used\n\n`ssize_t` is a POSIX type (cf. IEEE Std 1003.1).\n\nChange-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21015\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8e76230dfbcc7720c5565a70daff650496556702", "tree": "ab453e50dfada2bc28e71e7202f7f3d397e3f581", "parents": [ "a54ceb1dbe76e76ca8701dbda3e5baf011b16d6d" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Wed Aug 09 22:21:31 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Aug 13 00:38:12 2017 +0000" }, "message": "ich_descriptors: Modify limits for C620/Lewisburg PCH\n\nChange-Id: Ic8adc4b87993e65096166fa6d665432697070b4c\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20936\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a54ceb1dbe76e76ca8701dbda3e5baf011b16d6d", "tree": "f27ce3b104511a8b1598e77858cb42b41cb5e515", "parents": [ "67d71792929f94d4638a3663f2fc19aea4918681" ], "author": { "name": "Youness Alaoui", "email": "kakaroto@kakaroto.homelinux.net", "time": "Wed Jul 26 18:03:36 2017 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 10 15:18:11 2017 +0000" }, "message": "rpci: Use pci_dev struct pointer to avoid API breaks\n\nThe pci_dev structure is never meant to be used as is, but always as a\npointer. By using the struct itself in undo_pci_write_data, we are risking\ndata corruption, or buffer overflows if the structure size changes.\n\nThis is especially apparent on my system where flashrom segfaults\nbecause I compile it with pciutils 3.3.0 and I run it on a system\nwith pciutils 3.5.2. The struture size is different and causes a\nstruct with the wrong size to be sent to the library, with invalid\ninternal field values.\n\nThis has been discovered and discussed in Change ID 18925 [1]\n\n[1] https://review.coreboot.org/#/c/18925/\n\nChange-Id: Icde2e587992ba964d4ff92c33aa659850ba06298\nSigned-off-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/20784\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "67d71792929f94d4638a3663f2fc19aea4918681", "tree": "ea1f35914191ac66f66734777a1e1542ea20b403", "parents": [ "500263434b69594dc01b3ccfe5e2c4c498d87656" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Jun 17 03:10:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:31:58 2017 +0000" }, "message": "ich_descriptors: Pretty print an assumed chipset\n\nChange-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20247\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "500263434b69594dc01b3ccfe5e2c4c498d87656", "tree": "e78ca90e544a00521dca899c5f9187ff57cc0250", "parents": [ "fa62294536a3ce5070e8d9065aaa1aa45031f910" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 18:24:32 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:30:48 2017 +0000" }, "message": "chipset_enable: Set 100 series chipsets to NT\n\nChange-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19047\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa62294536a3ce5070e8d9065aaa1aa45031f910", "tree": "66152f87787e5c3c6ce2c9db903f8e1a70bd9311", "parents": [ "1dc3d420831b0ee482aede5f46ba53a0d2de4b74" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 24 17:25:37 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:30:21 2017 +0000" }, "message": "ich_descriptors: Update for Intel Skylake\n\nInterpretation of component clocks changed. Also more regions and more\nmasters are supported now. The number of regions (NR) is now static per\nchipset (10 in the 100 Series case) and not coded into the descriptor\nany more.\n\nv2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().\n o Update region extraction in `ich_descriptors_tool`.\n\nTEST\u003dRun `ich_descriptors_tool` over a 100 Series dump and checked\n that output looks sane. Run `ich_descriptors_tool` over dumps\n of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,\n 1 x Haswell). Beside whitespace changes, regions not accounted\n by `NR` are not printed any more.\n\nChange-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18973\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1dc3d420831b0ee482aede5f46ba53a0d2de4b74", "tree": "2c42e68012e89e5dec203874eaa0b3e6e6e086e6", "parents": [ "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Jun 17 00:09:31 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:26:01 2017 +0000" }, "message": "ich_descriptors: Add function to guess chipset version\n\nAdd guess_ich_chipset() that takes fields from a descriptor dump and\nreturns the lowest possible chipset version.\n\nIntel did several incompatible changes to the descriptor through the\nyears. However, they forgot to add a version number. So we have to\napply some heuristics to detect the chipset version in case of exter-\nnal flashing.\n\nChange-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20246\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9", "tree": "1bd56eecff210a628c148c836e2dfce13ebfd5f8", "parents": [ "d54e4f467753a247552bfb629f007f8931b0caa7" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 16:44:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:24:06 2017 +0000" }, "message": "ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()\n\nThe condition `base \u003e limit` is still valid since `base` is always at\nleast 4096 greater than `limit` in this case.\n\nChange-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19046\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d54e4f467753a247552bfb629f007f8931b0caa7", "tree": "0a7bb8254865783ad1fa1dc958e74e1a57936953", "parents": [ "93c306939b732fb05f6d8a692acc3fca78bc0f9f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 23 23:45:47 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:22:58 2017 +0000" }, "message": "ichspi: Add support for Intel Skylake\n\nThe Sunrise Point PCH, paired with Skylake, has some minor changes\nin the HW sequencing interface:\n\n * Support for more flash regions moved PR* registers\n * Only 4KiB erase blocks are supported by the primary erase command\n * A second erase command for 64KiB pages was added\n * More commands were added for status register access etc.\n * A \"Dedicated Lock Bits\" register was added\n\nNo support for the new commands was added.\n\nThe SW sequencing interface seems to have moved register location and\nis not supported any more officially. It\u0027s also untested.\n\nChanges are loosely based on the Skylake support commit in Chromium OS\nby Ramya Vijaykumar:\n\n commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1\n Author: Ramya Vijaykumar \u003cramya.vijaykumar@intel.com\u003e\n\n flashrom: Add Skylake platform support\n\nChange-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "93c306939b732fb05f6d8a692acc3fca78bc0f9f", "tree": "197478ba299562a8044c7d998c24e365af61b295", "parents": [ "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Mar 20 14:25:09 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:13:59 2017 +0000" }, "message": "chipset_enable: Add support for Intel Skylake / Kabylake\n\nAll publicly known Skylake / Kabylake / Sunrise Point PCH variants\nshare the same register interface [1..6]. Although all SPI configu-\nration is now done through the SPI PCI device 1f.5, we can\u0027t probe\nfor it directly since its PCI vendor and device IDs are usually hid-\nden.\n\nTo work around the hidden IDs, we use another PCI accessor that doesn\u0027t\nrely on the OS seeing the PCI device.\n\nThis handles SPI flashes only. While booting from LPC is still sup-\nported, it seems nobody uses it any more.\n\nSome additional PCI IDs were gathered from driveridentifier.com.\n\nTEST\u003dCompiled with B150 set to NT (instead of BAD) and checked for\n sane register readings.\n\n[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002EN\n Document Number 332995\n\n[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms\n Volume 2 of 2\n Revision 001EN\n Document Number 332996\n\n[3] 7th Generation Intel® Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002\n Document Number 334658\n\n[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms\n Datasheet - Volume 2 of 2\n Revision 002\n Document Number 334659\n\n[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform\n Controller Hub (PCH)\n Datasheet - Volume 1 of 2\n Revision 004EN\n Document Number 332690\n\n[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)\n Datasheet - Volume 2 of 2\n Revision 001EN\n Document Number 332691\n\nChange-Id: I000819aff25fbe9764f33df85f040093b82cd948\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18925\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6", "tree": "cfd2ea28b75cb90db72f488ee237a068d0cb52a4", "parents": [ "731316a9128c4015bc0facd1743afeb3a080129e" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:57:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 13 16:27:55 2017 +0000" }, "message": "Drop redundant `enum msglevel`\n\nUse `enum flashrom_log_level` instead to avoid further confusion.\n\nChange-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20268\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "731316a9128c4015bc0facd1743afeb3a080129e", "tree": "841a0f5b86816f556254d45c26859981561c3c81", "parents": [ "026c7416515985f47fe26a0478a37c0a1c2466c5" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Thu Jun 15 13:32:01 2017 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 13 16:23:16 2017 +0000" }, "message": "Enable continuous SPI reads\n\nPrevious unnecessary page-by-page reading is repurposed to\nread by big naturally aligned areas (now chip size limited\nto 16MB for future-proofing of 4 byte addressed multi-die chips)\nand serprog hack for continuous reads is removed.\n\nChange-Id: Iadf909c9216578b1c5dacd4c4991bb436e32edc9\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20223\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "026c7416515985f47fe26a0478a37c0a1c2466c5", "tree": "3b6367dd6c0d69fa6fb71d45d9c9a1616297d78d", "parents": [ "7634708c98a6fa439443e0791dd62563f4baf746" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Jun 20 20:47:54 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Jun 23 06:09:38 2017 +0000" }, "message": "Remove djgpp-dos target\n\nIt is not different to other x-compilations.\n\nChange-Id: Ia582b4cf622e670f1af439095ff58d62554232aa\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nReviewed-on: https://review.coreboot.org/20293\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7634708c98a6fa439443e0791dd62563f4baf746", "tree": "ab92caf9995bf2819ef31a8b4245a13c386027f9", "parents": [ "8624e8cfa88ebd17ecf3bfd55c8dc1a799f47573" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Nov 27 17:45:49 2016 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Jun 23 06:08:36 2017 +0000" }, "message": "Convert flashrom to git\n\n - Drop support for Subversion in the getrevision script and Makefile.\n - Add .gitignore and .gitattributes file (the latter to limit exports).\n - Restore modification dates of the exported files from the SCM.\n - Stop exporting SCM log dumps to CHANGELOG. This makes no sense.\n - Do not export the pre-\"compiled\" manpage. It can be generated like\n anything else from the code dump when we export the respective\n variable.\n The latter is added with this change.\n - Add some initial client-side git hooks\n * When committing check for obvious stuff you never want anyway:\n - white space errors\n * When pushing to the upstream repository check mandatory rules:\n - existing signoffs and acks in all new commits\n - no deletions or creation of branches\n - do not rewrite history of the precious branches, even if forced\n\nNOTE: This patch is adapted from Stefan Tauner\u0027s original commit:\nhttps://mail.coreboot.org/pipermail/flashrom/2016-November/014877.html\n\nThere are a few major differences:\n- This uses coreboot\u0027s commit-msg hook which includes support for\n generating and appending Change-Id.\n- djgpp-dos target removal is moved to a follow-up patch.\n- Version string changes are moved to a follow-up patch.\n\nChange-Id: I64eef21982cac0a0a7419bcd2c8a936672ae9cb2\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/19206\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8624e8cfa88ebd17ecf3bfd55c8dc1a799f47573", "tree": "f61a16e60f193b5e3f13a377a81d1308b1b4f0ad", "parents": [ "2d62572d1dd0c37eb626fd8faa17b26690f20b15" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Nov 05 21:46:33 2012 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 22 11:14:15 2017 +0000" }, "message": "udelay: Use clock_gettime() if available and precise\n\nInstead of calibrating our busy loop against a coarse clock, check if\na precise clock is available and loop against that. The former is unre-\nliable by definition on any modern system that may dynamically reclock\nthe processor.\n\nv2: Apparently _POSIX_MONOTONIC_CLOCK being defined only means that\n the library knows about CLOCK_MONOTONIC. So check for its support\n at runtime and fall back to CLOCK_REALTIME if it\u0027s missing.\n\nTEST\u003dManually added a 10s loop and compared to real time. Run\n on Linux RPi3, Linux x86 and my original use case Linux in\n VirtualBox (Linux host).\n\nChange-Id: I85ad359823875237ada9cd027af3017d62e9a235\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/19391\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2d62572d1dd0c37eb626fd8faa17b26690f20b15", "tree": "c76d5035e6fe7b8f9ca841c7030a7f44712f3d16", "parents": [ "8d494992176abe0877c88f06fdbc9c8d8826ae87" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue May 03 10:48:02 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 22 10:34:51 2017 +0000" }, "message": "Fix linking with libpayload\n\no Move flashbuses_to_text() to flashrom.c, it\u0027s not a cli function.\no Guard `!defined(HAVE_STRNLEN)`. This guard was introduced in\n 23e10b87 (Add a bunch of new/tested stuff and various small\n changes 24) to support older BSDs. It\u0027s probably completely\n broken because HAVE_STRNLEN is presumably a GNU autotools\n thing. But we can\u0027t fix it without retesting these older BSDs.\n\nChange-Id: I561135209b819361d125eeaeef9ff886d6bae987\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18738\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8d494992176abe0877c88f06fdbc9c8d8826ae87", "tree": "f1755cda3f7c271c5510b98d9a11785b715eb360", "parents": [ "e8e7a80e6b876710bebaa9f5a0b6f5e083d47516" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:18:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 13:27:13 2017 +0200" }, "message": "fixup! Make read_ich_descriptors_from_dump() available in flashrom\n\nAdd a guard around read_ich_descriptors_via_fdo() which uses raw\nhardware access and is only called from `ichspi`.\n\nFixes linking in case `NEED_RAW_ACCESS !\u003d 1`.\n\nChange-Id: I5a35c607df44cdbcbacb960f8922c1bf9f1f2002\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20265\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e8e7a80e6b876710bebaa9f5a0b6f5e083d47516", "tree": "c559486e6b3eadcbcd5ce7667bb0c8154836858e", "parents": [ "1b172f2da5573bd8b1732921af1b25a2cc739572" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:38:39 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 13:26:20 2017 +0200" }, "message": "fixup! Add a convenient libflashrom interface\n\nUpdate `enum flashrom_log_level` to match `enum msglevel` again.\n\nThey diverged already. Found by clang.\n\nChange-Id: Icf175c5f2a415365bd756ca813e724f6797459b2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20267\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1b172f2da5573bd8b1732921af1b25a2cc739572", "tree": "95f3a22dde7fd1d784d07304716c547a5b4f94e0", "parents": [ "560111e2ce506b75b112f0d10b5f9b99f007bfa5" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:35:24 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 13:25:46 2017 +0200" }, "message": "fixup! Add a convenient libflashrom interface\n\nThe buffer passed to flashrom_image_write() isn\u0027t `const`. It might be\naltered for full verification (with mixed contents if a layout is being\nused).\n\nChange-Id: Ibd8a9579e5dd859ae03b0deb3042b7035719e5de\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20266\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "560111e2ce506b75b112f0d10b5f9b99f007bfa5", "tree": "d9a568d1b4c092a80c9252a648f7ea7ce79bff01", "parents": [ "512059118e9ff56d2b4f3c324db5e764e288ac68" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 26 12:27:17 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:48:06 2017 +0200" }, "message": "ichspi: Drop `dev` parameter from init functions\n\nIt\u0027s never used and has no clear contract (e.g. will the pointer stay\nvalid beyond the call?).\n\nChange-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19460\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "512059118e9ff56d2b4f3c324db5e764e288ac68", "tree": "7c3c384d1579b467135fd85dd9cfbb88abb4771c", "parents": [ "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 17 17:59:54 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:47:49 2017 +0200" }, "message": "Handle Intel Wildcat Point *LP* like Lynx Point LP\n\nThe subtle difference was ignored when adding these chipsets. The\nintegrated Wildcat Point LP PCH is documented in [1].\n\nI\u0027m not sure how to account for \"Broadwell H\" which seems not publicly\ndocumented. Maybe it\u0027s an unreleased HM9*, in which case the non-LP\npath should be correct.\n\n[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,\n Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor\n Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet\n Revision 004\n Document Number: 330837\n\nChange-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18883\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359", "tree": "3f7ac3cbf792ad89f581ff7884e6bff4a4577ca0", "parents": [ "7258cf5197d2f1502430ad1c64027af2b341b7a6" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 16:31:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:47:24 2017 +0200" }, "message": "ich_descriptors: Fix more odd +1s\n\n+1 on everything doesn\u0027t make software greater per se.\n\nv2: o Fix another +1.\n o Amend style of similar (not +1 suffering) code, too.\n\nChange-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19044\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "7258cf5197d2f1502430ad1c64027af2b341b7a6", "tree": "46a19bfde42801cf0b9a6fb8754affd0b60578af", "parents": [ "3145423c5330256310f57207a445e50878474b3a" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Sat Jun 17 11:31:57 2017 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 18 13:19:43 2017 +0200" }, "message": "fixup! Kill doit()\n\nFix building with CONFIG_INTERNAL\u003dno because force_boardmismatch\ndoesn\u0027t exist when internal is not enabled.\n\nChange-Id: Id9e715f09ef934bc36221b3e72c578ae96e0a3af\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20250\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3145423c5330256310f57207a445e50878474b3a", "tree": "739d747ea0de9e4e69dd46e427b4430c17fec1a5", "parents": [ "305f417ea565a18c1e87dcf5d97307369b721c6c" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue May 03 11:43:17 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 12:08:14 2017 +0200" }, "message": "Whitelist Roda/RV11 laptop\n\nChange-Id: I036c1f8cb914c8e3cca9d17eb221b582d7414ae9\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18739\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "305f417ea565a18c1e87dcf5d97307369b721c6c", "tree": "75fd4a1087415f99a64d0a5f26eaddcb54969883", "parents": [ "ad18631b59d814b38bb6757df93fac17937a6bc9" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jun 14 11:55:26 2013 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 11:43:32 2017 +0200" }, "message": "Add option to read ROM layout from IFD\n\nAdd an option --ifd to read the ROM layout from an Intel Firmware\nDescriptor (IFD). Works the same as the -l option, if given, -i\nspecifies the images to update.\n\nv2: o Rebased on libflashrom, use libflashrom interface.\n o Use functions from ich_descriptors.c.\n\nv3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent\n of arch and programmers.\n o Bail out if we aren\u0027t compiled for little endian.\n o Update flashrom.8.tmpl.\n\nv4: o Incorporated David\u0027s comments.\n o Removed single-character `-d` option.\n\nv5: Changed region names to match the output of `ifdtool --layout ...`\n\nChange-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17953\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "ad18631b59d814b38bb6757df93fac17937a6bc9", "tree": "64a5fde5ab5bc0432fa74e3c263291e931330e3e", "parents": [ "3828b39263d008fb6cc5ebdbe7fb49bc6f926566" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon May 02 15:15:29 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 11:32:36 2017 +0200" }, "message": "Make read_ich_descriptors_from_dump() available in flashrom\n\nI didn\u0027t really know what I was doing and hope removing the #ifdefs\ndoesn\u0027t have negative side effects.\n\nThe idea is to make the functions generally available for external\nflashing (e.g. you might want to flash an Intel machine using an ARM\ndevice as programmer).\n\nBeware of big endian trouble, I guess. :-P\n\nChange-Id: Ib3d38a622a581afee87b49777e775942cc901fc8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17952\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "3828b39263d008fb6cc5ebdbe7fb49bc6f926566", "tree": "594149187c7dc540df85d7e86eec2ccd74ff8af2", "parents": [ "99d1595329190de2a09785e8e2017ecfc397eb23" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon May 02 17:04:59 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 11:30:48 2017 +0200" }, "message": "cli_classic: Remove layout-for-write-only check\n\nChange-Id: I0f5e9623ca75bc4503aeb45ae346d7573c0fef2c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17951\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "99d1595329190de2a09785e8e2017ecfc397eb23", "tree": "52f806b11bcfcd39ff7a7a05b222e9cf432cedcb", "parents": [ "70eed9ff60af62604a856940d5b126909e2d679e" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon May 02 16:54:24 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 09 14:00:27 2017 +0200" }, "message": "cli_classic: Add option (-N, --noverify-all)\n\nThis option specifies to verify included regions only after a write.\nIt also reduces the data read before the write.\n\nv2: o Changed short option name to `-N`.\n o Added section in the manual page.\n\nChange-Id: I40b5983f56d62821d17b827b88b73d1d41a30bd7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17950\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "70eed9ff60af62604a856940d5b126909e2d679e", "tree": "c4f8afc89c8d89bdc9be6b2b105a2ac0401c2f1e", "parents": [ "899e4ec810a1e2f3d377bc2095ba3d25b234a797" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Apr 24 22:19:27 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 05 17:42:16 2017 +0200" }, "message": "flashchips: Add untested Winbond W25Q128.W\n\nOnly difference to its sibling W25Q128.V seems to be the supply voltage.\n\nChange-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/19436\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "899e4ec810a1e2f3d377bc2095ba3d25b234a797", "tree": "270ac1d7101251d95a295effcbe5cf01ce2250f4", "parents": [ "1878110848f36c53667c9855f0a413c43e64597f" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Apr 29 18:39:01 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 03 20:19:30 2017 +0200" }, "message": "Kill doit()\n\nNo words can describe this feeling.\n\nv2: Rejoice while removing more, orphaned code (layout.c).\n\nChange-Id: Id81177c50b4410e68dcf8ebab48386a94cd9b714\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17949\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1878110848f36c53667c9855f0a413c43e64597f", "tree": "66bacd63991be932b3d031dfe280576449b3280e", "parents": [ "a9fc4f4ebf335f3f20a47a48f2b9c2b00a4de696" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Dec 10 13:34:12 2012 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:15:56 2017 +0200" }, "message": "Adapt CLI to use new libflashrom interface\u0027 print callback\n\nThis renames CLI\u0027s print() to flashrom_print_cb() and registers it\nthrough the new libflashrom interface.\n\nv2: Add libflashrom.o to LIB_OBJS now that everything can be linked\n together.\n\nChange-Id: Idf19978eb8e340d258199193d2978f37409e9983\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17948\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a9fc4f4ebf335f3f20a47a48f2b9c2b00a4de696", "tree": "e4aec9e0d55a6d4f224abf811bee1f8991fd8260", "parents": [ "454f61338213f73ca74fda54c0bf86afb01947de" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Dec 10 13:34:11 2012 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:13:31 2017 +0200" }, "message": "Add Doxyfile for libflashrom documentation\n\nReference documentation for libflashrom can be build with doxygen. With\n doxygen Doxyfile\ndocumentation will be put into a libflashrom-doc/ subdirectory.\n\nv2: o Updated Doxyfile with `doxygen -u Doxyfile`.\n o Added flashrom.c to the INPUT list.\n\nChange-Id: I583bf9aa8c43049723aff498625d490c37832f13\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17947\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "454f61338213f73ca74fda54c0bf86afb01947de", "tree": "5c981a1a181c130467d3c37b99cdeaf686ff49c8", "parents": [ "7af0e79b44bdc86497a992a90855f284e74d73f1" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Dec 10 13:34:10 2012 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:13:06 2017 +0200" }, "message": "Add a convenient libflashrom interface\n\nThis adds a minimal libflashrom interface based on the draft in the\nwiki. While the glue code in libflashrom.c is build on top of the\nexisting code instead on overhauling it, the interface in libflashrom.h\nis supposed to be stable. So we can keep the interface and adapt\ninternals later if favoured, without breaking clients.\n\nA new make target, libinstall, is also added. It installs libflashrom.a\nand libflashrom.h in lib/ and include/ dirs respectively.\n\nHooking this into the build would break linking of the CLI and is post-\nponed until that got fixed.\n\nv2: Rebase and fixes by Anton Kochkov.\n\nv3: o fl_image_*() rewritten with layout support (touch only included regions).\n o Moved read/erase/write/verify operations to flashrom.c.\n o Added layout pointer and flags to the flash context.\n\nv4: Removed libflashrom.o from LIB_OBJS until CLI is adapted.\n\nv5: o Incorporated David\u0027s comments.\n o Added `fl_flashprog_t` as dummy parameter to hide the fact that\n we have global state all around, and for future-proofness ofc.\n\nv6: o Change namespace prefix to flashrom_.\n o Remove typedefs.\n\nChange-Id: I00f169990830aa17b7dfae5eb74010d40c476181\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17946\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7af0e79b44bdc86497a992a90855f284e74d73f1", "tree": "df4c2b5d2776597d14b459f9c5e8430a55c7c075", "parents": [ "3a9939b952e614cd8e9e0530c22453f8f91c4e3a" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Apr 29 16:40:15 2016 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Jun 03 20:07:39 2017 +0200" }, "message": "Add functions to read/erase/write/verify by layout\n\nInspired by Lynxis\u0027 related work, this implements a foundation for\nlayout based flash access.\n\nAll operations iterate over the given layout regions. Erase and write\nthen walk, per region, over all erase blocks in an inner loop (which\nmight not be what we want, see note on optimization below). Special care\nhas been taken that flash content is merged properly, in case an erase\nblock is only partially covered by a layout region or even affects mul-\ntiple regions.\n\nA note on performance: In the case an erase block affects multiple\nregions, it will probably be read, erased and written for each region.\nAnother approach would be to walk all erase blocks once and check for\neach erase block which regions it touches (i.e. for each erase block,\nmerge data pontentially from the flash and all layout regions, then\nflash the combined data). That might result in cleaner code. I haven\u0027t\ntried it yet, though.\n\nChange-Id: Ic6194cea4c4c430e0cf9d586052508a865b09c86\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17945\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3a9939b952e614cd8e9e0530c22453f8f91c4e3a", "tree": "615a0ccb696f08e7761204b35eff57150c4858aa", "parents": [ "9e14aeda6464b2ecb391186e5b21bf5985141499" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 27 15:56:14 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 03 12:18:02 2017 +0200" }, "message": "Give layouts their own type\n\nIntroduce `struct flashrom_layout` and refactor layout.c a little, so\nwe can reuse the layout from there and have other sources of layouts\nbeside it.\n\nI didn\u0027t want to clutter up flash.h any more. So things went into a new\nlayout.h.\n\nChange-Id: Icea1a58c283131cc9c5fde6f16d783538dc1a4c7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17944\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\n" }, { "commit": "9e14aeda6464b2ecb391186e5b21bf5985141499", "tree": "0eec081e85ff96879d2f9b101212974b6d33cbcd", "parents": [ "d2a03b3e43043b596a79803bcb93f70e513bbb50" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Mar 28 17:08:46 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu May 04 12:45:57 2017 +0200" }, "message": "ich_descriptors: Fix range checks for dumps\n\nThese explicit off-by-one calculations were... off-by-one.\n\nChange-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19031\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "d2a03b3e43043b596a79803bcb93f70e513bbb50", "tree": "9f91e409309d3a823d795075e187caaa9b764227", "parents": [ "a52731d78478056039f935f8fad86007132fd2a7" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Mon Mar 13 13:48:03 2017 +0100" }, "committer": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Thu May 04 12:24:12 2017 +0200" }, "message": "Remove undefined behavior\n\nPer clang-3.9, the compiler fails on #define ...defined(...) statements\nas they\u0027re undefined behavior (apparently with different behavior\nbetween gcc/clang and msvc, too).\n\nSee clang\u0027s cfe repo commit r258128 for details.\n\nChange-Id: I82b6235e11b425fae45eebbe06b08f81c5bdbb98\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-on: https://review.coreboot.org/18792\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" } ], "next": "a52731d78478056039f935f8fad86007132fd2a7" }