)]}' { "log": [ { "commit": "4f29bb799b4672eebcc0bdfc6fb544b2b5544b6f", "tree": "8a27542cc468d103319c7c36afe894f57870f59a", "parents": [ "c753c40971c1481943e8a18dc24b33037e2a579d" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@gmail.com", "time": "Wed Aug 12 12:48:06 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "Add support for Comet Lake-U/400-series PCH\n\nAdd enum CHIPSET_400_SERIES_COMET_POINT and treat it identically\nto CHIPSET_300_SERIES_CANNON_POINT.\n\nAdd PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT.\n\nTest: read/write unlocked CML-U board\n\nflashrom-stable:\nAs suggested above, treat it the same as 300 series. But don\u0027t add a\nnew enum.\n\nChange-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71325\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "c753c40971c1481943e8a18dc24b33037e2a579d", "tree": "63d730f2195ac8f19740b9f2ed4cce9592790049", "parents": [ "13f90e64821fb8af412c7d692c72d2663dc9ce04" ], "author": { "name": "Lachlan Bishop", "email": "lxb@google.com", "time": "Thu Sep 10 14:57:05 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "dummyflasher.c: Factor out global state\n\nMoves global state into spi_master data.\n\nflashrom-stable: Squashed many fixups\n\nChange-Id: I972b085875f1277d9ff33326669d2676a3bcd3aa\nSigned-off-by: Lachlan Bishop \u003clxb@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/45230\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71323\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "13f90e64821fb8af412c7d692c72d2663dc9ce04", "tree": "9093a2c7001756fb3d5fde006f6fddfbb1664867", "parents": [ "e19a41b5411c1a693ad81e9b138ac7d474bad495" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Jan 06 14:10:52 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "tree/: Drop const from opaque data ptr in master definitions [alt]\n\nThe opaque data pointer need not necessarily have constant\ndata for the life-time of the specific master. This is because\nthe data field purpose is for the master to use as it sees fit\nfor managing its own internal state and therefore we should not\nconstrain this as being RO data at init time.\n\nflashrom-stable:\nAdd cast in bitbang_spi to avoid compiler warning.\n\nChange-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71336\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e19a41b5411c1a693ad81e9b138ac7d474bad495", "tree": "5d906d491859296f784ec0255beebabf07242077", "parents": [ "3531123fda54237b096ec67a932ce2ff8f544a1f" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Wed Aug 19 12:19:06 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG\n\nIntel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA.\n\nFix guess_ich_chipset_from_content() accordingly.\n\nPrint status info of read_ich_descriptors_from_dump() to facilitate\ndebugging upon failure.\n\nTested: run flashrom successfully from OCP Yosemite V3 DeltaLake server.\n\nChange-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44621\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71322\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3531123fda54237b096ec67a932ce2ff8f544a1f", "tree": "e497c4992beedcbb1727f0aff43ce7463be4ec16", "parents": [ "1592fe589725cccbc72db60fdb1858b6edb7432c" ], "author": { "name": "Namyoon Woo", "email": "namyoon@google.com", "time": "Fri Aug 28 07:56:00 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "dummyflasher.c: Only write back emulated image if modified\n\nWhen the image is not modified, there is no point in writing it back.\nIn fact we may not have file permissions to do so.\n\nSigned-off-by: Namyoon Woo \u003cnamyoon@google.com\u003e\nChange-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44907\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71321\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1592fe589725cccbc72db60fdb1858b6edb7432c", "tree": "caf214baffdfd692575632e27eec9c20b128f780", "parents": [ "c218a053aafbedc985ba448d9a1430116d38ad9b" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Aug 28 12:48:32 2020 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel Q77 as DEP\n\nTested reading and writing internal flash on Dell Optiplex 9010 SFF.\n\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nChange-Id: I4717959be1b79aa986f1276589d01ce7475bda8f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44910\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71320\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "c218a053aafbedc985ba448d9a1430116d38ad9b", "tree": "ab4cc37bd2680e2c5c0337c1e580801ec7e009b0", "parents": [ "9f0641960c4b3a4d71d5876b12e9c1e354bec139" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Wed Aug 19 12:16:40 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "add PCI IDs for additional c620 series PCH chips\n\nAdd PCI IDs for C621A, C627A and C629A.\n\nChange-Id: I636becd9f08bdf604c6af81ce396049655353b04\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71319\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "9f0641960c4b3a4d71d5876b12e9c1e354bec139", "tree": "8149dd59cba3645b9ea66faae3f2f1168f10f6b3", "parents": [ "5c639b32004925ae89ac6eb654344bad21cea9ef" ], "author": { "name": "Luka Kovacic", "email": "luka.kovacic@sartura.hr", "time": "Thu Jul 30 13:31:15 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller\n\nSupport for the Intel C620 Series Chipset SPI Controller (rev 04) is added\nto enable SPI flash access on the following platform:\n\n- Intel Xeon D-2187NT\n\nSupport for this controller was shortly tested on the platform above.\nThe flash is recognized, some regions of the flash are locked.\n\nSigned-off-by: Luka Kovacic \u003cluka.kovacic@sartura.hr\u003e\nOriginal-Tested-by: Jakov Petrina \u003cjakov.petrina@sartura.hr\u003e\nCc: Luka Perkov \u003cluka.perkov@sartura.hr\u003e\nChange-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71318\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "5c639b32004925ae89ac6eb654344bad21cea9ef", "tree": "d50bdf03700e78463ae850cbfe62186fb240672a", "parents": [ "dba5fa76c7e65ebe1b90da6a7a1ed223768ea9e5" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Sun Jul 26 10:40:46 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "stlinkv3_spi.c: Improve printed messages\n\nAdd missing line ends, and add a note about the first version of the\nupdater which contains the necessary V3 bridge feature.\n\nChange-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43900\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71317\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "dba5fa76c7e65ebe1b90da6a7a1ed223768ea9e5", "tree": "198fd4dd36bc595c2a0c68485a22d76a245ed353", "parents": [ "1f967c8acf61e2cc0d5e53c50bae11513a16755c" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Jul 19 13:02:03 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "endiantest: Fix #if expression\n\nWithout this, `gcc -E endiantest.c` can fail and return the incorrect\nendiannes as well as exiting with non-zero. Here is the actual error\nshown in the output:\n\nendiantest.c:2:31: error: #if with no expression\n #if __FLASHROM_LITTLE_ENDIAN__\n\nI was able to reproduce this using gcc-6.3.0 and clang-4.0.1, but\nnewer compilers didn\u0027t have this issue.\n\nChange-Id: Iba2febd861471ec821a494336e800c2564984332\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43598\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71316\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1f967c8acf61e2cc0d5e53c50bae11513a16755c", "tree": "3a38c1422300513fe68cbeafbd76603290abcd23", "parents": [ "7a6bce62a7b178c141a4dfc5e73b6b9ad80db84e" ], "author": { "name": "Jan Samek", "email": "jan.samek@siemens.com", "time": "Wed Jan 08 12:35:14 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: add PCI ID for APL-I (Broxton)\n\nChange-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324\nSigned-off-by: Jan Samek \u003cjan.samek@siemens.com\u003e\nSigned-off-by: Henning Schild \u003chenning.schild@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71315\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7a6bce62a7b178c141a4dfc5e73b6b9ad80db84e", "tree": "c7655661e4f347e2f5a3fa3b2ce21e0bbd17b675", "parents": [ "c3685189816e538f5db89e68d1151c5601dc9e52" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu Jul 02 09:36:50 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "serial: Fix file read/write error handling for Windows\n\nFile read/write semantics are different between POSIX and Windows. In\nparticular Windows file read/write functions return a boolean type to\nindicate success or failure, while the POSIX equivalents return a\nsigned integer indicating number of bytes read if successful or -1 if\nnot.\n\nThis attempts to correct some error handling paths for Windows and\navoid invalid comparisons that were causing compilation issues.\n\nReported on https://github.com/flashrom/flashrom/issues/149\n\nChange-Id: Ib179d51ede2dbd38f54f3641bfe90340a6a87e31\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43051\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71314\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "c3685189816e538f5db89e68d1151c5601dc9e52", "tree": "bf6fe43212d9ad0af8723df929570d6cd141d1e8", "parents": [ "cdb290e40cf977b7eb2d21b125f6117ad554dfde" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Jun 23 17:36:09 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "dediprog: Correct REQTYPE_OTHER_OUT macro\n\nIt\u0027s not used anywhere, but it should be correct if we continue to\nkeep it in.\n\nChange-Id: I8a6941c2906dda2c5aac5e0af3364fd2ac5773f3\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42763\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71313\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "cdb290e40cf977b7eb2d21b125f6117ad554dfde", "tree": "31d9eac835dafbea1ef954428d29b03895b4758e", "parents": [ "9148620a0d53bb8216d25f12be95b304786eeb9e" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Jun 23 14:16:26 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "tree: Remove unneeded semicolons after loops\n\nTrivial cleanup\n\nChange-Id: Id93a019a39b765c70b1a4eaeb25d9b582c3e4141\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42742\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71312\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "9148620a0d53bb8216d25f12be95b304786eeb9e", "tree": "8f134c4bda3606699f24c468ab0a6a8581d385d2", "parents": [ "68c32db5b4d404d96f72d660457671022fa44a46" ], "author": { "name": "Keith Hui", "email": "buurin@gmail.com", "time": "Tue May 12 21:43:58 2020 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "Add board enable for ASUS P3B-F\n\nWith this change flashrom can detect, enable and flash on this board\nboth under vendor BIOS and coreboot.\n\nChange-Id: I395ff50fbcda8ecdaa26033f0d99b2b0eb42f7ff\nSigned-off-by: Keith Hui \u003cbuurin@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/41354\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71311\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "68c32db5b4d404d96f72d660457671022fa44a46", "tree": "a9ab406182ea0c52b715ea2b97b92bccd25e7700", "parents": [ "abefc466e311de6b33eb0e0cf25fb72e558cc805" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 31 11:16:42 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "82802ab.c: Remove duplicated check\n\nChange-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/38661\nOriginal-Reviewed-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71310\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "abefc466e311de6b33eb0e0cf25fb72e558cc805", "tree": "620b775973797a6ec3312d9af47be0d509de3a81", "parents": [ "6d42d2ba8c718c5123286401bbcc61b0142aecef" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 29 15:23:59 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Spell `BIOS` in uppercase\n\nIntel document #336067 uses `BIOS Control` to refer to this register.\n\nChange-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Marcello Sylvester Bauer \u003csylv@sylv.io\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71309\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6d42d2ba8c718c5123286401bbcc61b0142aecef", "tree": "ab5eae104b4b15f3b6512cb107eabf5f4dc970c6", "parents": [ "739899a8ca23dd12430b1cb73b30960252ea8318" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Mar 31 15:34:35 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "ft2232_spi.c: Improve handling of static buffer\n\nIf `buf` became NULL because of an error, subsequent calls to the\n`ft2232_spi_send_command` function with a smaller buffer size will\nresult in a null pointer dereference. Add an additional null check\nbefore using `buf` to prevent that. Moreover, use `size_t` for the\n`bufsize` and `oldbufsize` variables, as it\u0027s what `realloc` uses.\n\nChange-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39975\nOriginal-Reviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71308\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "739899a8ca23dd12430b1cb73b30960252ea8318", "tree": "4498f1c4276831640d43a71154c017a5080bfad4", "parents": [ "34e7456dbf4ff47c85aeeb1d2b24d10d20fdffa4" ], "author": { "name": "Patrick Georgi", "email": "pgeorgi@google.com", "time": "Thu Apr 23 09:35:06 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "stlinkv3_spi: Fix memory leak\n\nChange-Id: Ic650b43395c64b1677f6e114b0faf42a3b7b3759\nFound-by: Coverity Scan #1415214\nSigned-off-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40652\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71307\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "34e7456dbf4ff47c85aeeb1d2b24d10d20fdffa4", "tree": "30b4154b498ab3cede1ddc6155d975e24197ee2b", "parents": [ "eb75123e3cf94631d884f0ec711d25dc3230a638" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Tue Apr 21 21:20:44 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "pcidev.c: Drop unused variable\n\nChange-Id: I6eea3e34ed6fc5d3fe65d5cf7e7bfc5e571bfa73\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40576\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71306\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "eb75123e3cf94631d884f0ec711d25dc3230a638", "tree": "7de399cbe11cf9aabede37087d4ca8dfab52deed", "parents": [ "77a2a6e43576ab3c3b31263ec7464e30fa62b44d" ], "author": { "name": "el-coderon", "email": "simon.buhrow@sieb-meyer.de", "time": "Fri Mar 20 18:52:15 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "ft2232_spi.c: change the chunksize from 256 to 270\n\nThis is to really make use of page write time advantage.\nBecause the Chunksize must be 256Byte raw data plus the address and cmd bytes.\n\nFor details check:\nhttps://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2HULJTDPHWPBZY6MLM6TGT7RTHSGHON/\n\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nChange-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39632\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71305\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "77a2a6e43576ab3c3b31263ec7464e30fa62b44d", "tree": "f4440424307f96043492269721d81ce396b19ef0", "parents": [ "a9335cc637c4d96ec37d8965628efbc0a7eb233a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Mar 23 16:05:07 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add more Lewisburg PCH IDs\n\nChange-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39780\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71304\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a9335cc637c4d96ec37d8965628efbc0a7eb233a", "tree": "0a5527d8e79de6d9c86848c87a88b3b5868b7853", "parents": [ "7113d17adc9f51400003bbdb4ed53e7b5d46b9dc" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Mon Mar 09 03:05:42 2020 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel HM75 as DEP\n\nTested reading and writing on a Samsung laptop (see CB:39388).\n\nChange-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71303\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7113d17adc9f51400003bbdb4ed53e7b5d46b9dc", "tree": "6e69cac79ec6a491aeef722d5536b604b98871a9", "parents": [ "de307c0d68ae46749a1dc392d983892b06f6a78a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sat Feb 29 23:13:43 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Skylake U Premium as DEP\n\nTested reading, writing and erasing the internal flash chip using an\nAcer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\n" }, { "commit": "de307c0d68ae46749a1dc392d983892b06f6a78a", "tree": "f12ef676bd45214b3cd106c77948c6ea076e1840", "parents": [ "99b518611a36da843d134fc4a2a7818a642c7de4" ], "author": { "name": "Michael Niewöhner", "email": "foss@mniewoehner.de", "time": "Sat Dec 11 22:15:06 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "SFDP: make mandatory table length check work with newer SFDP revisions\n\nThe JEDEC SFDP specification JESD216A (1.5) adds five new DWORDs to the\nBasic Flash Parameter Table. Later versions of the spec add even more\nfields. This increases the table being read from 36 bytes to currently\n64 bytes and makes flashrom bail out for any SFDP version \u003e\u003d 1.5 due to\na static table length check.\n\nThis was discovered on a GigaDevice GD25B127DSIGR from 2021 with SFDP\nrevision 1.6, while another flash of the same model from 2020 with SFDP\nrevision 1.0 was detected fine by flashrom.\n\nGD25B127DSIGR - 2020 version:\n\n Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision \u003d 1.0\n SFDP number of parameter headers is 2 (NPH \u003d 1).\n\n SFDP parameter table header 0/1:\n ID 0x00, version 1.0\n Length 36 B, Parameter Table Pointer 0x000030\n\nGD25B127DSIGR - 2021 version:\n\n Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision \u003d 1.6\n SFDP number of parameter headers is 2 (NPH \u003d 1).\n\n SFDP parameter table header 0/1:\n ID 0x00, version 1.6\n Length 64 B, Parameter Table Pointer 0x000030\n\n ...\n\n Length of the mandatory JEDEC SFDP parameter table is wrong (64 B),\n skipping it.\n\nThe specification says that changes of the minor SFDP revision will\nmaintain compatibility. Thus, simply check for the minimal required\ntable length, which is 16 bytes for legacy Intel pre-SFDP and 36 bytes\nfor SFDP.\n\nChange-Id: Id84cde4ebc805d68e2984e8041fbc48d7ceebe34\nSigned-off-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60055\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71301\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "99b518611a36da843d134fc4a2a7818a642c7de4", "tree": "72bef9a5fff9bbf0c951d967c4462fd4d52818d7", "parents": [ "abfb70c241b1dbf75e211ea182369d8710705cdc" ], "author": { "name": "Michael Niewöhner", "email": "foss@mniewoehner.de", "time": "Tue Jan 25 19:46:53 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "sfdp: drop redundant check of the mandatory table size\n\nChange-Id: I464856612a6d21c682f1d9ad5110fa11a0a276c2\nSigned-off-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61379\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71300\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "abfb70c241b1dbf75e211ea182369d8710705cdc", "tree": "fd8ccd7b5f55b2892e6d45c3826ae70222382270", "parents": [ "a97e353df0b3bb514502b7684b0171af75ff351e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 22 12:09:36 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:04:30 2023 +0000" }, "message": "libflashrom: Drop querying functions\n\nThis implementation of querying functions has shown too many\nmaintainability issues and at the same time we couldn\u0027t find\nany user of it. Questions on Gerrit and the ML [1] were left\nunanswered.\n\nPart of it was already removed, let\u0027s remove all of it to re-\nduce the churn.\n\n[1] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/3OJVU6QVYV47HLLVDZEWMFS24ND7PHB2/\n\nChange-Id: I006db190e69bc07959df40ce8737db93c9559265\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71299\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "a97e353df0b3bb514502b7684b0171af75ff351e", "tree": "15fb98340333226c91a5a08780465672f7cb3195", "parents": [ "f5bffd99bd7737b77e51b3e1bdb3392355b10ff6" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Dec 16 15:41:05 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:58 2022 +0100" }, "message": "flashchips.c: Mark W25Q128.V WP as tested\n\nTested: `-p internal --wp-status`.\n\nChange-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71240\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f5bffd99bd7737b77e51b3e1bdb3392355b10ff6", "tree": "294477f73e4d021f19df9c55ce3758563640e2c5", "parents": [ "3c9bdb97190cbeaf383633d52a57810a2361dccc" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Dec 14 12:30:43 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:58 2022 +0100" }, "message": "flashchips: Add WP settings for Flash Chip `W25Q512NW`\n\nThis patch adds WP register bits and decode range for Flash\nChip `W25Q512NW`.\n\nTested: Able to flash AP FW, wp-enable/disable on Google/rex device\nwhich has flash chip `W25Q512NW`.\n\nSigned-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nChange-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827\nOriginal-Reviewed-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Eric Lai \u003ceric_lai@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71239\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3c9bdb97190cbeaf383633d52a57810a2361dccc", "tree": "daf19e4813959ffc7c8ac9d8ca19ae34bde731ea", "parents": [ "b931e7a81314d0a9e44312ada2996719da19154e" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Dec 15 23:30:16 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "flashchips.c: Indent definition of W25Q512NW-IM properly\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151\nOriginal-Reviewed-by: Eric Lai \u003ceric_lai@quanta.corp-partner.google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71238\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b931e7a81314d0a9e44312ada2996719da19154e", "tree": "06a427c3a3410a48e05e9c1c2da4fc571cd038ab", "parents": [ "09dd6ba4b16fd8d80e09de55702e0ba0a111ac89" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Dec 05 13:06:14 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "flashchips.c: remove WREN from GD25Q256D enter 4BA sequence\n\nAs noted in a comment on\n`commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D\ndatasheet indicates that the chip does not require a WREN command to\nenter 4BA mode.\n\nTesting has confirmed that a WREN command is not required, so change the\nflashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA.\n\nTicket: https://ticket.coreboot.org/issues/356\n\nTested: read/write/erase/verify GD25Q256D flash with FT2232H programmer\nTested: called spi_enter_exit_4ba(true), dumped registers, checked ADS\u003d1.\n\nChange-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71015\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "09dd6ba4b16fd8d80e09de55702e0ba0a111ac89", "tree": "040b9f98b7a48c793f630dfa6f2d4e4fc27a539e", "parents": [ "d5ba24c1a0870c9b1e3142ffa122851b22acf0da" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Nov 21 19:10:54 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "writeprotect.c: Split register value/mask calculation into pure func\n\nExtract the code that converts `struct wp_bits` into a collection of\nregister values and bit masks out of `write_wp_bits()` into a new\nfunction.\n\nThis avoids monadic transformer stacks where unit-testing cannot\npenetrate well to give suitable coverage, therefore keep the bit\nlogic in a separate pure function.\n\nTested: ninja test\nTested: flashrom --wp-{{dis,en}able,range,list,status} on dedede\n\nChange-Id: I604478ecbb70392c5584bf5d87c76b6f20f882b1\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69846\nOriginal-Reviewed-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71013\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d5ba24c1a0870c9b1e3142ffa122851b22acf0da", "tree": "8208daddbf73ed9733b183524519d1c8b5206601", "parents": [ "b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:28:35 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E\n\nChange-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71011\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86", "tree": "159be3b6cf099734c86474a71131660f903399ab", "parents": [ "c6e8b1ad88ed1c65bba9c6002a36b16181c1ffec" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:27:37 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M\n\nSplit chips:\n * W25Q32.V -\u003e W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV\n * W25Q32.W -\u003e W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q\n\nChange-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71010\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c6e8b1ad88ed1c65bba9c6002a36b16181c1ffec", "tree": "a96474c1ccdee8b8fcb54bf36894f639016979c2", "parents": [ "39687acc6bf41b955a11e8a8fa3f0029342cbb3e" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Aug 14 20:57:48 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for EN25QH32 and EN25QH64\n\nSplit chips:\n * EN25QH32 -\u003e EN25QH32 and EN25QH32B\n * EN25QH64 -\u003e EN25QH64 and EN25QH64A\n\nUnlike older revisions both newly added EN25QH32B and EN25QH64A support\nhalf block (32KiB) erase operation via 0x52 opcode.\n\nChange-Id: I759f0119346235ce0bddc78cde9c461495990c25\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71009\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "39687acc6bf41b955a11e8a8fa3f0029342cbb3e", "tree": "36f702391d17eae36554a2064297284a14cbc10b", "parents": [ "081ffbae47cbebda5611de101b9dd53b3a58b6bb" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:23:25 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "writeprotect_ranges.c: add more range functions\n\nNot all chips follow the same pattern. There are differences in how CMP\nbit is treated or in block size used.\n\nChange-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71008\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "081ffbae47cbebda5611de101b9dd53b3a58b6bb", "tree": "0aa667febe2679732655e1b6be68582c2b3b6ac1", "parents": [ "0b5a70736f59dce25d0f6d71a6dc89a54b680fcd" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Wed Aug 17 18:29:10 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "writeprotect.c: refuse to work with chip if OTP WPS \u003d\u003d 1\n\nPerform the check right in read_wp_bits() as it\u0027s used by various WP\noperations and also because its results won\u0027t make sense if WPS bit is\non and can\u0027t be changed.\n\nChange-Id: I143186066a1d3af89809b7135886cb8b0d038085\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66836\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71005\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0b5a70736f59dce25d0f6d71a6dc89a54b680fcd", "tree": "990c09b00907579493b355284b5a4d43724824ce", "parents": [ "29c8b5db5da5c0506aaac26fdfd3c8312638a51b" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Aug 14 16:51:46 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "writeprotect.c: skip unnecessary writes\n\n* Don\u0027t write register because of RO and OTP bits.\n* Skip the write of RW bits if register state wouldn\u0027t change by it.\n\nChange-Id: I81d2d3fc0a103ee00ced78838d77fe33a9d3056a\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66754\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71004\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "29c8b5db5da5c0506aaac26fdfd3c8312638a51b", "tree": "4977598e6bfbbfe95ec1be529dd5b5d2b454c327", "parents": [ "d81997cdb76a721e46cfd98a7e65410d4e9790a5" ], "author": { "name": "Evan Benn", "email": "evanbenn@chromium.org", "time": "Tue Sep 13 16:01:10 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "flashchips: Add write protect bits to W25Q64JW...M\n\nhttps://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale\u003den\u0026DocNo\u003dDA00-W25Q64JW\n\nTested: None\n\nChange-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62\nSigned-off-by: Evan Benn \u003cevanbenn@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71003\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d81997cdb76a721e46cfd98a7e65410d4e9790a5", "tree": "db791021e0353c4be0dd8dfcb2b1c5a78d032db0", "parents": [ "c74eac2fa3349c41f43eb9bd73809a1f051a9346" ], "author": { "name": "Evan Benn", "email": "evanbenn@chromium.org", "time": "Tue Sep 13 17:12:59 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:54 2022 +0100" }, "message": "writeprotect: Add some debug logging if wp_verify fails\n\nChange-Id: I5fcaf767570418f90ae44826a1135d9b49653033\nSigned-off-by: Evan Benn \u003cevanbenn@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67720\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71002\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c74eac2fa3349c41f43eb9bd73809a1f051a9346", "tree": "330e6692197e48a9ad63b1b7db3fbf1eb201efde", "parents": [ "c720b6e8fbe9245e670f1424c5d24143b22a4c72" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Thu Oct 06 18:17:58 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:54 2022 +0100" }, "message": "flashchips.c: mark WP of 9 entries as tested\n\nThis is based on information from:\n * commit a850fd0aa8054a1125a9231fa3317428f15900f4\n - GD25LQ128C/GD25LQ128D/GD25LQ128E\n - GD25LQ64(B)\n - GD25Q127C/GD25Q128C\n - GD25Q256D/GD25Q256E\n - GD25Q64(B)\n * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba\n - GD25Q32(B)\n * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8\n - W25Q64BV/W25Q64CV/W25Q64FV\n * https://github.com/Dasharo/dasharo-issues/issues/67\n - W25Q128.V..M\n * https://github.com/Dasharo/flashrom/pull/8\n - W25Q64.W\n\nChange-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Tested-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Tested-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Tested-by: Kamil Pokornicki \u003ckamil.pokornicki@3mdeb.com\u003e\nOriginal-Tested-by: Przemyslaw Banasiak \u003cprzemyslaw.banasiak@3mdeb.com\u003e\nOriginal-Tested-by: Maciej Pijanowski \u003cmaciej.pijanowski@3mdeb.com\u003e\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71001\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c720b6e8fbe9245e670f1424c5d24143b22a4c72", "tree": "82c71b6415f8583d331ea7fc88ce73e2705f6071", "parents": [ "590525835ab9f8b9471c17f859e0e18245008c08" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Thu Oct 06 15:17:52 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:54 2022 +0100" }, "message": "flash.h: extend `struct tested` with .wp field\n\nUsing \"B\" letter for \"block protection\" in TEST_* macros.\n\nTicket: https://ticket.coreboot.org/issues/377\nChange-Id: I791400889159bc6f305fb05f3e2dd9a90dbe18a4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68179\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71000\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "590525835ab9f8b9471c17f859e0e18245008c08", "tree": "16fb4a4b18661a8692fd3f10e14ea8b25c29a3da", "parents": [ "3ca0af0c8baadb8a25056f0d6d7c2299822ae55b" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Mar 08 15:23:58 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips.c: Mark MT25QU256 as tested\n\nAs reported by Charles Parent on the mailing list.\n\nChange-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62664\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70998\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ca0af0c8baadb8a25056f0d6d7c2299822ae55b", "tree": "d47899d5e121026e9dcc7655c0e1ed455030bf24", "parents": [ "bb608ff1900eee52c4bb3eb624421a8c0fe1b694" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri Jun 17 15:10:18 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips.c: change GD25Q256D to \"GD25Q256D/GD25Q256E\"\n\nExtend \"D\" chip entry to include newer \"E\" parts.\n\nChange-Id: I6b398d417da9289cc1d6a191fb20e3f937addb21\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65191\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70997\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bb608ff1900eee52c4bb3eb624421a8c0fe1b694", "tree": "3b020028e30f3c6888a26cccad0f99040d32e5dd", "parents": [ "26237922269390f11788ae573c4af39eb17d5e30" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:33:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips: Add missing block eraser for S25FL512S\n\nNow that we can make use of the extended-address register, we can also\nadvertise the `d8` eraser that can take 3- or 4-byte addresses.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTicket: https://ticket.coreboot.org/issues/357\nChange-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64637\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70996\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "26237922269390f11788ae573c4af39eb17d5e30", "tree": "a91ae80f27628b92bc2401c6c3e871c0473473e5", "parents": [ "ad55d5a4ea4bc82450b076fbf9faffc130a698bb" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:37:37 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512S\n\nAccording to its datasheet, Spansion S25FL512S supports writing/\nreading its extended address register via 0x17/0x16 opcodes. With\nthat enabled, we can also enable the EAR7 feature, i.e. toggling\n4BA mode via bit 7 of that register.\n\nS25FL512S did not advertise EAR support at all, so we set it to\nTEST_UNTESTED again.\n\nChange-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70995\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ad55d5a4ea4bc82450b076fbf9faffc130a698bb", "tree": "6beb87c779785e2e3a823b171231c51c5c6f2602", "parents": [ "9bb8a322e991b899a6faff4ec14d2f4c6dba447d" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:32:16 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips\n\nAccording to their datasheets, ISSI IS25LP256 and IS25WP256 support\nboth 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended\naddress register. Flashrom will use 0xc5 by default if available,\nso adding the FEATURE_4BA_EAR_1716 flag makes no difference for now\n(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA\nset). It\u0027s better to have a comprehensive description of the chips,\nthough, in case somebody wants to use them in the future with a\nmaster that restricts available opcodes.\n\nChange-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70994\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d", "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35", "parents": [ "542b1f04869e7ac42b84800675f08f617ddf3f2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:07:34 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n instructions (and some programmers may be picky about which\n instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "542b1f04869e7ac42b84800675f08f617ddf3f2d", "tree": "9516bc3f06c3fc5d67203328e524b967b5d36901", "parents": [ "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 14:30:12 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Rename FEATURE_4BA_EXT_ADDR -\u003e _EAR_C5C8\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\nTo prepare for other instructions than the default 0xc5/0xc8, rename\nthe original feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70992\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c", "tree": "175824426d5d38363c842aa3bfd4267477d89073", "parents": [ "5215eab80aa6ce4682aaadac5b318cb6c6d1bd7b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 15:17:14 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Drop FOUR_BYTE_ADDR comments\n\n4BA support is implemented by now. So drop these obsolete comments.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I28c5d1de052c28735d5f07874874068ee744b77f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64600\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70991\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5215eab80aa6ce4682aaadac5b318cb6c6d1bd7b", "tree": "c927408b441b4e47102a46386176f27a14f2c3d6", "parents": [ "fffc48d247cef5102113d97538054066546b2297" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 15:13:07 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Split W25Q256.V\n\nThe W25Q256JV supports the full set of 4BA instructions, including two\nnative-4BA block erasers.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I1a68121ff40d2b1769632d8e5151c2cd972c23ef\nTicket: https://ticket.coreboot.org/issues/362\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64599\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70990\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fffc48d247cef5102113d97538054066546b2297", "tree": "cdb49567c3d7c2291fa33221989516afb1b03abf", "parents": [ "3f3c1f3238dcede30d0d15d36da6326b428b8b12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 14:26:06 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L\n\nThese chips seem to be rather regular, supporting 2.7V..3.6V, the\ncommon erase block sizes 4KiB, 32KiB, 64KiB and the usual block-\nprotection bits.\n\nStatus/configuration register naming differs from other vendors,\nthough. These chips have 2 status registers plus 3 configuration\nregisters. Configuration registers 1 \u0026 2 match status registers\n2 \u0026 3 of what we are used from other vendors. Read opcodes match\ntoo, however writes are always done through the WRSR instruction\nwhich can write up to 4 bytes (SR1, CR1, CR2, CR3).\n\nS25FL256L supports native 4BA commands and entering a 4BA mode.\nHowever, it uses an unusual opcode (0x53) for the 32KiB 4BA block\nerase.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I356df6649f29e50879a4da4183f1164a81cb0a09\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f3c1f3238dcede30d0d15d36da6326b428b8b12", "tree": "9adc4f207793fe401c9ffd28e2f7c60460766533", "parents": [ "478e179f2d5ecf6a8b82984444b9111913a8f50f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 16:48:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "spi25_statusreg: Allow WRSR_EXT for Status Register 3\n\nSpansion flash chips S25FL128L and S25FL256L use the WRSR instruction to\nwrite more than 2 registers. So align SR2 and SR3 support: The current\nFEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3\nis added. Also, WRSR3 needs a separate flag now.\n\nVerified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "478e179f2d5ecf6a8b82984444b9111913a8f50f", "tree": "a87192cf8ab508ce56cb441147d00d0658355e29", "parents": [ "1e6aabc39de5ca46a69ef1b164ce55a4288753c3" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Sat Jun 04 01:34:44 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "flashrom.c, flashcips.c: Test the order of erase functions\n\nAdd a check so that the erase functions for all flashchips are in\nincreasing order of their respective eraseblock sizes. This is required\nfor the implentation of the improved erasing algorithm. The patch uses\nthe count of eraseblocks in each erase function to determine the order\n(More eraseblocks means that the function has smaller eraseblock size).\nAlso fix the structs in flashchips.c which were found to be not\nconforming to this test.\n\nTested: make \u0026\u0026 ./flashrom\n\nChange-Id: I137cb40483fa690ecc6c7eaece2d9d3f7a851bb4\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64961\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70987\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Aarya \u003caarya.chaumal@gmail.com\u003e\n" }, { "commit": "1e6aabc39de5ca46a69ef1b164ce55a4288753c3", "tree": "103de40711dcff4b3e4332e879b1aae380183a82", "parents": [ "2502dbd627e595d2974b1419f5e54a2faa7406a1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 16:39:07 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "writeprotect: Add line-break after each `spew` message\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I3131ff0e3fa4f9e949ce2e8d2d0a9c862a15e1cd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64745\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70986\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2502dbd627e595d2974b1419f5e54a2faa7406a1", "tree": "139f05845f46312101c492dd4aefd75a75ade642", "parents": [ "8f5bd989971c97c9d160cf4f1aa2b91f72b152fe" ], "author": { "name": "Atul Dhudase", "email": "adhudase@codeaurora.org", "time": "Tue Sep 21 10:02:20 2021 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "Add W25Q512NW-IM ID to flashrom\n\nAdd Winbond W25Q512NW-IM chip ID and specs to flashrom.\n\nTested: flash W25Q512NW-IM using CCD.\n\nOriginal-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65\nOriginal-Signed-off-by: Atul Dhudase \u003cadhudase@codeaurora.org\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890\nOriginal-Reviewed-by: Shelley Chen \u003cshchen@chromium.org\u003e\nOriginal-Reviewed-by: Vadim Bendebury \u003cvbendeb@chromium.org\u003e\nOriginal-Tested-by: Shelley Chen \u003cshchen@chromium.org\u003e\nOriginal-Commit-Queue: Shelley Chen \u003cshchen@chromium.org\u003e\n(cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61)\n\nNote: this commit was cherry-picked from the cros tree but\nincludes corrections to errors in the original commit\u0027s 4BA\nfeature flags that were spotted by Angel Pons\n\nChange-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70985\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8f5bd989971c97c9d160cf4f1aa2b91f72b152fe", "tree": "2a3ead55a8311b9a917f4e6291c8e9e61291ea4a", "parents": [ "d1af307018bf73b1e585b6427a84b4a58e42c934" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Wed Aug 26 09:15:53 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "flashchips: Fix W25Q256.W\n\nThe JW is the only known variant. A W25Q256FW may have existed with\nless 4BA instructions supported, but it never showed up and no data-\nsheet is available.\n\nUsed the datasheet from here:\nhttps://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf\n\nChange-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTicket: https://ticket.coreboot.org/issues/362\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70984\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1af307018bf73b1e585b6427a84b4a58e42c934", "tree": "74e8bddd48fb391178abc188141c96bfc1625da1", "parents": [ "801fcd0123af9a253d68089e2728d0f51a64b749" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Nov 08 00:00:43 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "flashchips: enable write-protection for W25Q{64,128}.V\n\nConfiguration for W25Q64 was tested on hardware (W25Q64FV).\n\nEmulation of W25Q128 in dummyflasher will be extended to support WP.\nHaven\u0027t tested this one on hardware, but it\u0027s the same configuration as\nfor W25Q64 except that it has WPS.\n\nW25Q64JV chip was renamed to W25Q64JV-.M (those with QPI).\n\nW25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)\nand W25Q64JV-.Q (SR3 and WPS, but no QPI).\n\nflashrom-stable: FIXME added, W25Q128.V should probably be split.\n\nChange-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59071\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70982\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "801fcd0123af9a253d68089e2728d0f51a64b749", "tree": "71351110f1e02733565e415bf6ec322e11958d8d", "parents": [ "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Dec 19 18:45:16 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "writeprotect: add WPS bit and always set it to zero\n\nWPS bit controls use of individual block protection which is mutually\nexclusive with protection based on ranges. Proper support requires\nextension of the API as well as implementation, so here we\u0027re just\nmaking sure that range-based protection is enabled and our WP\nconfiguration is not ignored by the chip.\n\nChange-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60231\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70981\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf", "tree": "020dea176939135afa15e8f328088e808b6c812a", "parents": [ "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Dec 19 18:37:51 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "spi25_statusreg.c: add SR3 read/write support\n\nAdds support for reading and writing the third status register.\n\nFeature flag is not needed because it would never on its own control\nwhether SR3 access occurs. If added, it would be in one of three\npossible states: wrong, useless or redundant.\n\nChange-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70980\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21", "tree": "cd09884914e46f8641d59b95a68132d47c1daa13", "parents": [ "551664c6a7c447746503afcd6e303c9b21fff71c" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Oct 20 17:09:09 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "flashchips.c: mark IS25LP064 as TEST_OK_PREW\n\nTested \u0027-w\u0027, \u0027-E\u0027 and \u0027-r\u0027 successfully with\nmy FT2232H programmer.\n\nChange-Id: I2197ce0be9db7c3d74b24c7445dc06238584ffea\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58472\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70979\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "551664c6a7c447746503afcd6e303c9b21fff71c", "tree": "7d2044394629218ba5b58afad9dd8f68e5034f87", "parents": [ "ccae68ac91b00eb68adf11fa88e6d9a1aaa01b0b" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Mar 09 16:09:08 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "flashchips.c: Mark GD25Q40(B) as tested\n\nAs mentioned by Wolf Dieter Brandt in his mail from 07.Feb.22.\n\nChange-Id: Idec3d82efbdf095c3d57bfe5f0fd487007b554cb\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62712\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70978\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ccae68ac91b00eb68adf11fa88e6d9a1aaa01b0b", "tree": "3f1f0c9d24adb8b3034dd5414b84a06b15084637", "parents": [ "d32e18b0c03a0426f808477544f6ecec9ae10f66" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 08 01:07:01 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "writeprotect.c: refactor and fix wp_mode functions\n\nThis is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.\n\nUse a lookup table in get_wp_mode() and drop the srp_bit_present check,\nsince a chip without SRP is just FLASHROM_WP_MODE_DISABLED.\n\nAdd a srp_bit_present check to set_wp_mode() if the mode requires it.\n\nTested: flashrom --wp-{enable,disable,status} on AMD dut\n\nChange-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70977\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d32e18b0c03a0426f808477544f6ecec9ae10f66", "tree": "73e1e07c595028935a4183b628101b95c53fd660", "parents": [ "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Feb 15 18:06:55 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "flashchips.c: add writeprotect support for more chips\n\nChips I had available for testing were tested with all writeprotect\ncommands and an FT232H adapter. Chips I wasn\u0027t able to test were just\nchecked against the datasheets.\n\nChips used for testing (including chips added in previous patches) are\nlisted in the table below:\n\nFlashrom Chip name | Chip(s) tested\n---------------------------------+----------------------------\nAT25SL128A |\nEN25QH128 |\nGD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG\nGD25LQ64(B) | GD25LQ64CWIG\nGD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG\nGD25Q256D | GD25Q256DYIG\nGD25Q64(B) | GD25Q64CSIG\nW25Q128.JW.DTR |\nW25Q128.V..M |\nW25Q128.W |\nW25Q256JV_M |\nW25Q256.V |\nW25Q64.W |\nXM25QH128C |\nXM25QH256C |\n\nTested: flashrom --wp-{enable,disable,range,list,status}\n\nChange-Id: I7f3d4c4148056098a845b5c64308b0333ebda395\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70976\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb", "tree": "85191d34786a8297b7618919e50b64095fa2cee0", "parents": [ "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 28 16:18:28 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "spi25_statusreg: delete spi_read_status_register()\n\nDelete the spi_read_status_register() function because the generic\nspi_read_register() function can be used instead.\n\nThis patch also converts all call sites over to spi_read_register().\nA side effect is that error codes are now properly propagated and\nchecked.\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n Read SR1/SR2 with --wp-status and activated various WP ranges\n that toggled bits in both SR1 and SR2.\n\nChange-Id: I146b4b5439872e66c5d33e156451a729d248c7da\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70975\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3", "tree": "cbbb97227c2ae0e4cf45b9d222e22893118f0ec0", "parents": [ "9e1afb785efd0e6144a19d1faff012d4cbf5a668" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Nov 22 13:18:49 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:46 2022 +0100" }, "message": "spi25_statusreg: inline spi_write_register_flag()\n\nCreating the entire SPI command that should be sent to the chip in\nspi_write_register() is simpler than splitting it across two functions\nthat have to pass multiple parameters between them.\n\nAdditionally, having separate spi_write_register_flag() function\nprovided little benefit, as it was only ever called from\nspi_write_register().\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n Read SR1/SR2 with --wp-status and activated various WP ranges\n that toggled bits in both SR1 and SR2.\n\nChange-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70974\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9e1afb785efd0e6144a19d1faff012d4cbf5a668", "tree": "9a638ea81371e96b8dfe4740c536d5e04e7d8111", "parents": [ "b6112a53add4a9fc144066252be11099cecc496b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 02:29:22 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:46 2022 +0100" }, "message": "writeprotect: add {get,set}_wp_mode()\n\nTested: flashrom --wp-{enable,disable,status}\n\nChange-Id: I7b68e940f0e1359281806c98e1da119b4caf8405\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58483\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70973\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b6112a53add4a9fc144066252be11099cecc496b", "tree": "d31441efeee7633ff172e95551dbe4200e9f737a", "parents": [ "077c0d131a98f7b4fd19de3ff30e7dc9a558ce60" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 02:28:23 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:46 2022 +0100" }, "message": "writeprotect: add set_wp_range()\n\nTested: flashrom --wp-{status,range}\n\nChange-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58482\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70972\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "077c0d131a98f7b4fd19de3ff30e7dc9a558ce60", "tree": "c4281650f8f0d80d4de1d2b07de21b08c31f8a3b", "parents": [ "1234d110cf11e2b72ef96349920d5b79d3089f6c" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:50:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "libflashrom,writeprotect: add flashrom_wp_get_available_ranges()\n\nGenerate list of available ranges by enumerating all possible values\nthat range bits (BPx, TB, ...) can take and using the chip\u0027s range\ndecoding function to get the range that is selected by each one.\n\nTested: flashrom --wp-list\n\nChange-Id: Id51f038f03305c8536d80313e52f77d27835f34d\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58481\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70971\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1234d110cf11e2b72ef96349920d5b79d3089f6c", "tree": "89329957cf6bc237fd254dbb18795eec7cb0838e", "parents": [ "c9feb1bdfa96745a200b9a62dc4234446db8ddb6" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 02:28:23 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "writeprotect: add get_wp_range() for decoding ranges\n\nTested: flashrom --wp-{status,range} at end of patch series\n\nChange-Id: I5a1dfcf384166b1bac319d286306747e1dcaa000\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59183\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70970\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c9feb1bdfa96745a200b9a62dc4234446db8ddb6", "tree": "b532df293904cb48d7efa7b127a0072f48801835", "parents": [ "da1c834e9899e5094377a33d19daa53c0d88640b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:35:13 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "flashchips,writeprotect_ranges: add range decoding function\n\nAllow chips to specify functions that map status register bits to\nprotection ranges. These are used to enumerate available ranges and\ndetermine the protection state of chips. The patch also adds a range\ndecoding function for the example chips. Many other chips can also be\nhandled by it, though some will require different functions (e.g.\nMX25L6406 and related chips).\n\nAnother approach that has been tried in cros flashrom is maintaining\ntables of range data, but it quickly becomes error prone and hard to\nvalidate.\n\nUsing a function to interpret the ranges allows compact encoding with\nmost chips and is flexible enough to allow chips with less predictable\nranges to be handled as well.\n\nTested: dumped range tables, checked against datasheets\n\nChange-Id: Id163ed80938a946a502ed116e48e8236e36eb203\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70969\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "da1c834e9899e5094377a33d19daa53c0d88640b", "tree": "9fc9415b879ad477b8e6475bb94075b406b4180e", "parents": [ "e75127a19dc53c6c076fa634a647897f6a8c875f" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 00:58:12 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "libflashrom,writeprotect: add functions for reading/writing WP configs\n\nNew functions are exposed through the libflashrom API for\nreading/writing chip\u0027s WP settins: `flashrom_wp_{read,write}_cfg()`.\n\nThey read/write an opaque `struct flashrom_wp_cfg` instance, which\nincludes the flash protection range and status register protection mode.\n\nThis commit also adds `{read,write}_wp_bits()` helper functions that\nread/write chip-specific WP configuration bits.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58479\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70968\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e75127a19dc53c6c076fa634a647897f6a8c875f", "tree": "10cbe1cea1c4da8207fc7ddeeb7476cb0768d639", "parents": [ "c6c3f28c66e0ad792274ca05029a120925e21be6" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:12:39 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "writeprotect.h: add structure to represent chip wp configuration bits\n\nAdd `struct wp_bits` for representing values of all WP bits in a chip\u0027s\nstatus/config register(s).\n\nIt allows most WP code to store and manipulate a chip\u0027s configuration\nwithout knowing the exact layout of bits in the chip\u0027s status registers.\n\nSupporting other chips may require additional fields to be added to the\nstructure.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58478\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70967\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c6c3f28c66e0ad792274ca05029a120925e21be6", "tree": "0df6153a2d812235b3defe835f40b9ed08684c92", "parents": [ "9de3f8710d5c46d35cd9869018c85e5aa51483b0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 23:34:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "flash.h,flashchips.c: add writeprotect bit layout map to chips\n\nThis patch adds a register bit map `struct reg_bit_info`, with fields\nfor storing the register, bit index, and writability of each bit that\naffects the chip\u0027s write protection. This allows writeprotect code to be\nindependent of the register layout of any specific chip. The new fields\nhave been filled out for example chips.\n\nThe representation is centered around describing how bits can be\naccessed and modified, rather than the layout of registers. This is\ngenerally easier to work with in code that needs to access specific bits\nand typically requires specifying the locations of fewer bits overall.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70966\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0", "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df", "parents": [ "0167522794a2e66f00248347122c1bb8ce3b001d" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:32:25 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0167522794a2e66f00248347122c1bb8ce3b001d", "tree": "ac01ed9312b2946bdcdbe1abf1078b69f6117183", "parents": [ "236a38cc46ac810d0be679402bb21e83aebcb8b9" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:30:41 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "spi25_statusreg: make register read/write functions generic\n\nThis patch adds new spi_{read,write}_register() functions that take the\nsource/destination register as an argument. Currently they can only\naccess SR1, support for other registers will be added in another patch.\n\nSince we\u0027re refactoring things, this commit also makes\nspi_read_register() return an error code, making it possible to identify\nerror conditions that spi_read_status_register() concealed.\n\nThis also removes the initial 100ms delay between writing a register and\nthe first attempt to check the chip\u0027s status. An initial delay was added\nto avoid needing to read the status register multiple times, but that is\nunlikely to cause problems on modern flash chips.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70964\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "236a38cc46ac810d0be679402bb21e83aebcb8b9", "tree": "a460050e0a50e0cb37383709b1abfdbcbc7bbcbc", "parents": [ "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Fri Nov 05 11:48:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips: Add W25Q64JV\n\nI have successfully tested it with FT2232H-programmer.\n\nChange-Id: Ia9a32146b225eca66e9a6bfef45be5f2b24aef46\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58971\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70963\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6", "tree": "daf3ce9e6a6aa471eeeea5296904ff369d448f65", "parents": [ "571f6ad31f0047fdbf613448e04d9c7138ade662" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Sep 29 09:28:07 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips.c: mark EN25F10 as TEST_OK_PREW\n\nAs reported by Wolf Dieter Brandt in his e-mail from 09.Aug.2021.\n\nChange-Id: I0c19f84780e7fa3699fd706f8e105fc5937ba8bf\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58031\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70962\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "571f6ad31f0047fdbf613448e04d9c7138ade662", "tree": "a0926521de7d240eab415da54dc70ffa5712fd5a", "parents": [ "981a344f65c2125b7aba72c0a61760f33c508ec2" ], "author": { "name": "Tao Xia", "email": "xiatao5@huaqin.corp-partner.google.com", "time": "Wed Jul 21 16:41:53 2021 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12833F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nSigned-off-by: Tao Xia \u003cxiatao5@huaqin.corp-partner.google.com\u003e\nChange-Id: I14ab7e04f5209d2bcf34b0d2de9da2c01bf32d00\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56546\nOriginal-Reviewed-by: Weimin Wu \u003cwuweimin@huaqin.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70961\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "981a344f65c2125b7aba72c0a61760f33c508ec2", "tree": "79e38d75327c731023c3e4b5f2729eb5695b2484", "parents": [ "2649dde2be69f01f4c5bee4a7d21223bd25e322c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Tue Jun 22 11:16:55 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips.c: Add \u0027GD25LQ128E\u0027 to match C and D variants\n\nAs defined by gigadevice. C, D and E are all meant to\nbe the same.\n\nChange-Id: I3bef9386a185a0e8c54c125af5509b63540995aa\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55742\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70960\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2649dde2be69f01f4c5bee4a7d21223bd25e322c", "tree": "2232b470f8921c5b5cb9cddf8864536c5e9eec26", "parents": [ "3ba8315e134c3fc0f29b538abb22fd9e85a2361f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 03 13:47:39 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12873F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nChange-Id: I59c8067f15b5ceac5a2e2f8fe93431a465f17e23\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56054\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70959\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ba8315e134c3fc0f29b538abb22fd9e85a2361f", "tree": "315ee58cda0d2d9de74142d442d43bf31ba500e2", "parents": [ "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Tue Jun 08 10:52:19 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add support for Macronix MX66L1G45G\n\nTested on Dediprog SF600: Reading and writing works.\n\nChange-Id: I554e828c97d9ec77b08489573a34e176599d2518\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55353\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70958\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8", "tree": "67f1c17c4dd4fd6ab500a78c5aee1ce7db03d5d1", "parents": [ "5fa050515d2fff9679d38803a8594e4a8c5a407a" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Mon Feb 15 13:16:57 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: Mark MT25QL256 as tested\n\nAs mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020.\n\nChange-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70957\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5fa050515d2fff9679d38803a8594e4a8c5a407a", "tree": "59ba8caf8f49cbec055d2cb0b47052d3e54c65ab", "parents": [ "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri May 14 15:26:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips: change chip name from \u0027W25Q64JW\u0027 to \u0027W25Q64JW...M\u0027\n\nAccording to the W25Q64JW datasheet rev. E, only devices ending with the\nletter \u0027M\u0027 have a device ID of 8017h. There are other variants with\ndifferent device IDs. This patch makes the \u0027W25Q64JW...M\u0027 definition\nconsistent with the \u0027W25Q32JW...M\u0027 definition.\n\nThe device ID macro defined in flashchips.h has also been renamed from\nWINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.\n\nChange-Id: Ib0dc914da286a191d22e666332b1063b88db4251\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70956\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0", "tree": "0d12cf62cf976d9a3378fa48a245478c1caffab1", "parents": [ "b6683e0a5586537269524eaadee5619d1dec410b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Sat May 08 17:31:23 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: add support for W25Q32JW...M\n\nThe chip was added to cros flashrom in\n`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.\nQuoting from the commit message:\n\n\u003e We have varied the correct chip name is reported as well as\n\u003e write and read 16MBytes of random data and verified the checksum\u0027s match.\n\u003e Further, --wp-list appears to report the correct ranges.\n\u003e\n\u003e BUG\u003db:130199963\n\u003e BRANCH\u003dnone\n\u003e TEST\u003dRan flashrom with a Dediprog SF100, RW random data and checksum matched.\n\nChange-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70955\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b6683e0a5586537269524eaadee5619d1dec410b", "tree": "b2bdb49813421373adc4a5f8ede57b920b89e05c", "parents": [ "6e69e2b5f78104e5b54e83be889ae887702309ff" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:04:29 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add MX25L3233F\n\nOnly mattering difference to the MX25L3273E seems to be the voltage\nrange (starting at 2.65V instead of 2.7V). I don\u0027t think that would\njustify yet another entry.\n\nChange-Id: I73402dddedf360ab84caed4c019efe27b477d4c2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52570\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70954\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6e69e2b5f78104e5b54e83be889ae887702309ff", "tree": "78ea64917e28700796c57bba0d0f8602145360d0", "parents": [ "475a7eed6d6589c8a1e5267a1f4be3500fb245c4" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:03:13 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Correct OTP comment for MX25L3273E\n\nThe datasheet says 4K bits, maybe just a copy-paste error.\n\nChange-Id: I42b10aa09c969e5c5e7102b1e8ab496f52bd27bb\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52569\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70953\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "475a7eed6d6589c8a1e5267a1f4be3500fb245c4", "tree": "6a90aa1167acc44f0ddf92f0124d3eaa220bef33", "parents": [ "1ebda787f1c6bec8e63d06a01ba921c49c4e2187" ], "author": { "name": "Christian Kudera", "email": "coreboot@kudera.at", "time": "Tue Apr 20 22:50:01 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add support for Boya/BoHong Microelectronics B_25D16A\n\nRead tested on CH341A\n\nChange-Id: I25b776204affda94cc7e753e7671ef9d3d9508f1\nSigned-off-by: Christian Kudera \u003ccoreboot@kudera.at\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52555\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70952\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1ebda787f1c6bec8e63d06a01ba921c49c4e2187", "tree": "193cb9fe46cd8ca4887496c6fc63e6cc7e8fe7cc", "parents": [ "148254be920530d54d76d742b30a3fb61689cf07" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Apr 20 21:39:11 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips: Adapt IDs for Boya Microelectronics\n\nLooks like BoHong Microelectronics has the same vendor ID and makes very\nsimilar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have\nthe same specifications and their datasheets are mostly identical.\n\nChange-Id: I8d6951797daeeecca6af200c995297c0394adefd\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70951\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "148254be920530d54d76d742b30a3fb61689cf07", "tree": "ff3580e4dcd6726dc1dd97ce6fa2d01d5f1135f6", "parents": [ "e64ef6d72741c39cb9a5e866d9952f2b14366996" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:21:10 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark MX25U25635F as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit 419e32ae457cc36b03757b89471a7ce3770e9611`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dTested writes using Servo\n\nChange-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70950\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e64ef6d72741c39cb9a5e866d9952f2b14366996", "tree": "9ae607243716dcdab4d39e4e282d89412bf020af", "parents": [ "df889fa924154ffd1265971b05002c28651b8e83" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:15:40 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark GD25Q256D as TESTED_OK_PREW\n\nTested read/write/erase/verify with FT232H programmer.\n\nChange-Id: Ia7d52b69eb571113fe3c60ec9a139ee67180509b\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51735\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70949\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "df889fa924154ffd1265971b05002c28651b8e83", "tree": "068e75775d2d757e3cf1a264aa8e7f4d5c069c22", "parents": [ "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:10:45 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: mark EN25S64 as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dread and write BIOS on glimmer with Eon device.\n\nChange-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70948\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5", "tree": "e65d194cc42f67ab9caf8bcc6dbf400d5546b6f5", "parents": [ "c205487aede60d9926541159631a0e360abdc82d" ], "author": { "name": "Tim Chen", "email": "tim-chen@quanta.corp-partner.google.com", "time": "Mon Jul 06 14:59:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "CHROMIUM: flashrom: update .tested field for EN25QH128\n\nupdate .tested field from TEST_UNTESTED to TEST_OK_PREW\n\nTested: Flash Duffy bios\n pass on running `flashrom_tester /usr/sbin/flashrom host`\n\nOriginal-Change-Id: I9467588988c2cab0987737c53ace0832144ef169\nOriginal-Signed-off-by: Tim Chen \u003ctim-chen@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Commit-Queue: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n(cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff)\n\nChange-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70947\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c205487aede60d9926541159631a0e360abdc82d", "tree": "417b46539f418ddfc293d1041ad762d54207dec5", "parents": [ "813a7e2eef268f2e63b2cac2e9b60a2ed2365945" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 15 18:57:32 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips: Mark Macronix MX25L1635D as tested\n\nTested probe, read, erase and write with a FTDI FT2232H successfully.\n\nChange-Id: I7421b7e36e687ea2ffff494c00157976db73ac43\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49489\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70945\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "813a7e2eef268f2e63b2cac2e9b60a2ed2365945", "tree": "89eba409e95982a9507434721351671c52df042d", "parents": [ "721a4f390410debb77487562c8a47a20edb4d7f2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Jan 08 08:48:17 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW\n\nI have successfully probed/read/erased/written a GD25LQ128D, so marking\nthis entry as tested.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70944\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "721a4f390410debb77487562c8a47a20edb4d7f2", "tree": "cf842e10410c39de9bf712d547cdd23f40a5a19b", "parents": [ "ef88423928abf61fa894d2798a9d265fd001cd26" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Dec 14 07:39:02 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "spi25_statusreg.c: restore SR contents at flashrom exit\n\nregister_chip_restore() provides a general mechanism for restoring a chip\u0027s state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR\u0027s sector layout bits so that entire flash accessible.\n\nThis patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash.\n\nImported from cros flashrom at `b170dd4e1d5c33b169c5`\n\nChange-Id: If2f0e73518d40519b7569f627c90a34c364df47c\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70943\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ef88423928abf61fa894d2798a9d265fd001cd26", "tree": "8ceb8aa058cf63a0f39e4a9c8114733b0914af1c", "parents": [ "e0e8b2b8f99030962994b876353e3a69cb68af80" ], "author": { "name": "luke he", "email": "sixuerain@qq.com", "time": "Mon Dec 28 18:22:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips.c: Add support for XMC new SPI flash types\n\nAdds initial support for the follow SPI flash chips:\n\n XM25QU64C\n XM25QU128C\n XM25QU256C\n XM25QH64C\n XM25QH128C\n XM25QH256C\n\nflashrom-stable:\n* Added missing 4BA flags / erasers\n* Dropped wrong, superfluous comments\n* Sorted\n\nSigned-off-by: Luke He \u003csixuerain@qq.com\u003e\nChange-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70942\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e0e8b2b8f99030962994b876353e3a69cb68af80", "tree": "ff9e47bf8eba1954ad347a9ea8bab70bb7af2306", "parents": [ "4ad486465ccceedce372c498ad19ac84edbc0078" ], "author": { "name": "Zoltan HERPAI", "email": "wigyori@uid0.hu", "time": "Sat Aug 08 16:04:34 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips: Mark Intel 25F640S33B8 as TESTED_PREW\n\nTested with ch341a_spi from an Atheros AP81 reference board.\n\nChange-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef\nSigned-off-by: Zoltan HERPAI \u003cwigyori@uid0.hu\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44342\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70941\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4ad486465ccceedce372c498ad19ac84edbc0078", "tree": "b278a2499ed1ac3101b4e74f48a8a622640c15d3", "parents": [ "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Nov 05 13:54:27 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashrom.c: implement chip restore callback registration\n\nAllows drivers to register a callback function to reset the\nchip state once programming has finished. This is used by\nthe s25f driver added in a later patch, which needs to change\nthe chip\u0027s sector layout to be able to write to the entire flash.\n\nAdapted from cros flashrom at\n`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.\n\nChange-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70940\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e", "tree": "bb4d94a94cf593bae5592de6bdee9afe61eafeae", "parents": [ "0cf3e12fd5e420115551062a225b44e1782ba629" ], "author": { "name": "Jack Olsen", "email": "omegasec@tutanota.com", "time": "Sat Aug 08 21:12:13 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Boya Microelectronics BY25Q128AS\n\nTested on Buspirate.\n\nSigned-off-by: Jack Olsen \u003comegasec@tutanota.com\u003e\nChange-Id: I881ba86cfaa82e43c73360135d47c74d896cc191\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70939\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" } ], "next": "0cf3e12fd5e420115551062a225b44e1782ba629" }