)]}' { "log": [ { "commit": "4f00912c704ea6b69df8dc331199503b1c6739c3", "tree": "18b7d84641364382629a82122b858bd5d90db5b3", "parents": [ "dd59220e7e774d3e8fa100cd0b448fa363e3be73" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 10:45:18 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:47 2019 +0000" }, "message": "flashchips: Add GD25Q127C name to the GD25Q128C entry\n\nRenamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128.\n\nAccording to downstream (ChromiumOS) change\n4216ba3d0fbd1804a71002b9c17e0b04029a03f1 \"flashchips: Add GD25Q127C name\nto the GD25Q128C entry\", the 127C chip is replacement for the 128C chip.\nI have confirmed that 127C is newer and that 128C does not appear to be\ndocumented on Gigadevice\u0027s website or available from Digikey.\n\nTEST\u003dRan flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35089\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "dd59220e7e774d3e8fa100cd0b448fa363e3be73", "tree": "6d7c8fb007bf977a011c3b4b63bb906f5872b677", "parents": [ "71b706f544eff68657a15139c39b9f0d8c3b2940" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Aug 23 10:11:37 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:13 2019 +0000" }, "message": "flashchips.c: Put SFDP-capable chip back into position\n\nPut entry for Unknown SFDP-capable chip back into place at end of file.\n\nChange 1f9cc7d89992114c70f7a0545ad9f98701bebe56 \"flashchips.c: Sort file\nby vendor and model\" reordered many entries in flashchips.c, including\nthis one. However, the entry for Unknown, SFDP-capable chip should not\nhave been moved before any specific chip entries.\n\nAs reported by Angel Pons \u003cth3fanbus@gmail.com\u003e at\nhttps://review.coreboot.org/c/flashrom/+/33931:\n\n\"\"\"\nOops, this introduced a bug: the SFDP entry is no longer at the end of\nflashchips.c, so probing on a SFDP-capable Winbond chip results in added\nnoise (flashrom says things about an unknown chip, and then has two\ndefinitions for the same chip).\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5955020456dbcd5e7db280a459b668a743e464dc\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35037\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "71b706f544eff68657a15139c39b9f0d8c3b2940", "tree": "c1dde02bfa7df1aeb1c29d2dd881f826f0b6c118", "parents": [ "188127e5692df218c560253095a1e96cdff7c6cd" ], "author": { "name": "Artur Raglis", "email": "artur.raglis@3mdeb.com", "time": "Wed Jun 05 19:24:52 2019 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Sep 17 00:34:37 2019 +0000" }, "message": "libflashrom: add querying functions with meson integration\n\nWork based on lukasz.dmitrowski@gmail.com code\n\nChange-Id: I49041b8fa5700dabe59fef0d2337339d34cd6c6f\nSigned-off-by: Artur Raglis \u003cartur.raglis@3mdeb.com\u003e\nSigned-off-by: Lukasz Dmitrowski \u003clukasz.dmitrowski@gmail.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34363\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "188127e5692df218c560253095a1e96cdff7c6cd", "tree": "f4e17efd282d0c26c07ab5c1342c9120874e45b6", "parents": [ "ea0c093246fbaba9ab89348400ba4e99032aa4e0" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Aug 06 16:10:34 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Aug 21 06:18:16 2019 +0000" }, "message": "flashchips: upstream changes to GD25LQ128\n\nChange name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the\nchange from the chromium flashrom repo SHA\n6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at\nhttps://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)\n\nThe rationale from that change was:\n\n The GD25LQ128C part is EOL. It\u0027s replacement is GD25LQ128D, but\n both chips identify in the same manner. Add GD25LQ128D to the name\n of the part so that it doesn\u0027t confused people.\n\nMaking this name consistent will simplify further merging from the\nchromium fork.\n\nChange-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34735\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "ea0c093246fbaba9ab89348400ba4e99032aa4e0", "tree": "f5982cd4b2d3e207d064612083a286fcd5ad5cfc", "parents": [ "bde44a1989342859240c6993d1f782945bb4ce94" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 17:34:16 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:33:25 2019 +0000" }, "message": "chipset_enable: Mark Intel CM236 and CM246 as DEP\n\nThe usual ME-lock limitations apply, so this is DEP instead of OK.\n\nTested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also\nregression tested on Apollo Lake. Flashrom works fine, and logs and\ndescriptor dumps look good. Also, register and descriptor output\nagree on the flash layout and permissions.\n\nChange-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34073\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "bde44a1989342859240c6993d1f782945bb4ce94", "tree": "8887b05e3561727001e0dd6ad14ee1d040ff9ee3", "parents": [ "2a5dfaf140eb8f22c923a026df855da0c5e9bf82" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@puri.sm", "time": "Thu Jul 04 17:52:40 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:46 2019 +0000" }, "message": "chipset_enable: Add support for Cannon Lake U Premium\n\nAdd support for Cannon Lake U Premium (CFL-U/WHL-U).\nSame as discrete 300-series CNP PCH.\n\nTested on a WHL-U laptop w/unlocked IFD.\n\nChange-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@puri.sm\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34076\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "045b97ebd97426b70706db7338a7fd76790b8781", "tree": "428bed111f3cc84a29c0059d74e337fe4cf7c7c9", "parents": [ "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:26:56 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:47 2019 +0000" }, "message": "flashchips: Add missing MT25Q erase commands\n\nThis adds additional 32KiB subsector erase commands 0x5c and 0x52 and an\nadditional bulk erase command of 0x60.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34490\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130", "tree": "28ad082eab9008a0906bd409bf01377511202b27", "parents": [ "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:21:22 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:41 2019 +0000" }, "message": "flashchips: Fix N25Q512 bulk erase\n\nThe N25Q is a stacked device, so it requires 0xC4 to perform a die\nerase.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34489\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24", "tree": "e554fa9e21be6164a33b6486e1cc04346f39d005", "parents": [ "a4e579f94a80b949a0173b4b49cce01f20383aa7" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:04:40 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:09:32 2019 +0000" }, "message": "flashchips: Split MT25Q from N25Q\n\nThe MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q\nis almost entirely backwards compatible with the N25Q series, however,\nthe MT25Q has additional subsector erase commands available, and there\nare differences in stacked devices in the higher capacity variants. The\nN25Q devices are left with \"Micron/Numonyx/ST\" as the vendor and MT25Q\ndevices are set with \"Micron\" as the vendor.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34488\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a4e579f94a80b949a0173b4b49cce01f20383aa7", "tree": "320e0898ff31848178faa258ae6d326a10a37c14", "parents": [ "8855257d2051b2db0f6b1a4125d39f075d360cc4" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 24 14:18:39 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 03 14:47:06 2019 +0000" }, "message": "flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PRE\n\nThe AMD Am29F010 was marked TEST_OK_PRE in chromium repo change\nSHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other\ndifferences in the definition of this chip.\n\nThis is the only change from the Chromium repo to be upstreamed for AMD\nchips.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34534\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "8855257d2051b2db0f6b1a4125d39f075d360cc4", "tree": "3968368edfdf80bc3b8be45714492d29654e2a88", "parents": [ "a508ca0acdc5cbd0ae8c2342d865d363ef24f185" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 24 13:56:06 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 03 14:46:24 2019 +0000" }, "message": "flashchips.c: Mark Intel 82802AB as TEST_OK_PREW\n\nIntel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their\nSHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork\nand here in upstream are otherwise substantially similar.\n\nThere are no other downstream changes for Intel chips to be upstreamed.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34533\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "a508ca0acdc5cbd0ae8c2342d865d363ef24f185", "tree": "8fe50245d5bb3b8817427287510f199df1015e73", "parents": [ "519be66fc59558971dd653afe69ccaf1a633b492" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 24 19:34:43 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:27:57 2019 +0000" }, "message": "chipset_enable: Fix recent -Wmissing-field-initializer trouble\n\nChange-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "ef78de4a21323b8c459337356289218211f2c5ce", "tree": "5f6b24b01b1091c97ce32e72fb8424c2d8e9b9c1", "parents": [ "5800f5841de2fd74bfc6590978bd034a6c9e6102" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 15:08:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:20:08 2019 +0000" }, "message": "cli_classic: Fix Memory leak\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I84e642b57b95953f376569e443ef8d8eda7bf98f\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34405\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "5800f5841de2fd74bfc6590978bd034a6c9e6102", "tree": "929fbfc5ca19a359b7bf1743ac138e1cac63e34d", "parents": [ "3384fb6ddae9583c2e201fc9c8a819e9df530369" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 14:30:47 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:17:58 2019 +0000" }, "message": "spi25: Remove dead increment\n\nValue stored in \u0027pos\u0027 is never read.\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I9a70593f182d7558e71e831fc2b834ac58a25b2a\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34404\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3384fb6ddae9583c2e201fc9c8a819e9df530369", "tree": "c0b78c341908d77ff6573416eca2e98094ee0b82", "parents": [ "a136d425cebc01fa4cfb670696243fd2194dd711" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 14:00:13 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:17:44 2019 +0000" }, "message": "pickit2_spi: Fix \"dead\" assignment\n\nWe never read the first \u0027ret\u0027. Let\u0027s check the first \u0027ret\u0027\nand exit if it failed.\n\nAlso, print the version only when the command succeeded.\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I4aac5e1f3bd0604b079e1fdd9b7f09f1f4fc2d7f\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34403\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a136d425cebc01fa4cfb670696243fd2194dd711", "tree": "9792a00db0dbd81de32d32f5da3b2d1651e5437b", "parents": [ "b221cd7048f9cde1fe789e686a0e0adaf9a688b3" ], "author": { "name": "Hemanth Guruva Reddy", "email": "meethemanth@gmail.com", "time": "Thu Jul 11 11:08:27 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 17 10:45:16 2019 +0000" }, "message": "flashchips: Add Macronix MX25L51245G as known chip\n\nMX25L51245G is identical to handling of MX66L51235F.\n\nChange-Id: I964e630197e33d69b199fdfb8816f18e3112bbb1\nSigned-off-by: Hemanth Guruva Reddy \u003cmeethemanth@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34234\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b221cd7048f9cde1fe789e686a0e0adaf9a688b3", "tree": "9937847a661fbf7b83ee7d341daf59367d4d3a6e", "parents": [ "d2d3993a25c3236d397209f9c2118c3b17ce4f95" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Fri Apr 05 15:08:35 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 10 18:59:55 2019 +0000" }, "message": "pickit2_spi: update to libusb1 and drop libusb0 dependency\n\nTESTED: read, write, verify\n\nChange-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32213\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d2d3993a25c3236d397209f9c2118c3b17ce4f95", "tree": "8c91f0f2d588e66963c13e48dd972de555985bf4", "parents": [ "3750986348cb99b8f0d828b73972b545a2f9c878" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 16:49:37 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:23:53 2019 +0000" }, "message": "ichspi: Add Apollo Lake support\n\nIt\u0027s almost identical to 100 series PCHs and later. There are some\nadditional FREGs (12..15). To not clutter the `if` conditions further,\nmake more use of `switch` statements.\n\nTested on Kontron mAL10. Mark it as DEP as usually the last sector\nis not covered by the descriptor layout and can\u0027t be read.\n\nChange-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30995\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3750986348cb99b8f0d828b73972b545a2f9c878", "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315", "parents": [ "908adf4589d34eaf3bd8395afa52aed8c8887cfd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 14:23:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:15:58 2019 +0000" }, "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "908adf4589d34eaf3bd8395afa52aed8c8887cfd", "tree": "7381774317fc86dd8426183093d99ca45b06d5c1", "parents": [ "1f9cc7d89992114c70f7a0545ad9f98701bebe56" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 03 15:34:06 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 05 22:48:40 2019 +0000" }, "message": "flashchips.c: Make .tested lines consistent\n\nAs per comments on https://review.coreboot.org/c/flashrom/+/33833/, make\nplacement of spaces in .tested attributes with literal definitions\nconsistent.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33998\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "1f9cc7d89992114c70f7a0545ad9f98701bebe56", "tree": "be790c5a8ade8cbf74fccf2c05a878f77ea25651", "parents": [ "2d7ab6963c4450f2fae74632e0e74037641d50d2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Jul 01 11:10:45 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 05 22:48:18 2019 +0000" }, "message": "flashchips.c: Sort file by vendor and model\n\nFor self-consistency, and to allow tools to assist with merging the\nchromium fork of flashrom, sort the entries of flashchips.c. The file is\nalready largely sorted, though deviations have crept in over time.\n\nThis is a non-clever mostly ASCII-order sorting. It is not intended to\nbe permanent.\n\nChange-Id: I75a99583592526f60ba5264e92391bf8b1213b20\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33931\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2d7ab6963c4450f2fae74632e0e74037641d50d2", "tree": "6f8fb00ab0aa528ac495152610d98826cce7f99a", "parents": [ "69146f70a65e8f376833390ced3951d8a8746996" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Wed Jul 03 17:58:24 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 04 18:48:31 2019 +0000" }, "message": "layout: Increase max rom layout size\n\nWhen trying to flash a single FMAP region on VBOOT enabled boards the\ndefault of 32 entries is to small to store all regions. Flashrom will\nbail out with \"Cannot add fmap entries to layout - Too many entries.\"\n\nIncrease the maximum rom layout size to 128 to support complex FMAPs.\n\nTested on coreboot\u0027s UP/squared mainboard using SF600.\nWith this patch it\u0027s possible to update a single FMAP region.\n\nChange-Id: I68084b08f7b35a162b5f2d3109d82a8b63c194ff\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34025\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Christian Walter \u003cchristian.walter@9elements.com\u003e\n" }, { "commit": "69146f70a65e8f376833390ced3951d8a8746996", "tree": "645527630eca55e910925cf5239294931a34ef9b", "parents": [ "f29ea362bb9ea035b6a36f0eff88c6ab77bbb97f" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 17:14:11 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:32:50 2019 +0000" }, "message": "flashchips.c: Format SFDP-capable chip entry\n\nTo allow automated tools to manipulate flashchips.c, make the definition\nof SFDP-capable chip more consistent with other definitions. This\ninvolves\n- reordering fields to match both other entries and the definition of\n struct flashchip.\n- reformatting comments to make them consistent with other entries.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I8708a11993822085b3e8d8c80532dfb935d39876\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33834\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "f29ea362bb9ea035b6a36f0eff88c6ab77bbb97f", "tree": "ed7eeb1e769ca400001f31c54985655f20f69f04", "parents": [ "c1863cad848a03a07e6d1a9b24dafaac39d62a94" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 17:14:02 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:32:22 2019 +0000" }, "message": "flashchips.c: Make comment placement consistent\n\nFor consistency, move a comment about an entry from inside the open\nbrace to outside it.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33837\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "c1863cad848a03a07e6d1a9b24dafaac39d62a94", "tree": "60e3d752d3d826d7f45f9872f3a1aed1233fe73c", "parents": [ "f5ad688f8be10c23dacc853ec0120bef5c6c3e1f" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:08:03 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:31:57 2019 +0000" }, "message": "flashchips.c: Fix field order\n\nFor consistency and in order to allow automated tools to work with\nflashchips.c, put fields in the same order as they are defined in struct\nflashchip, in flash.h\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33833\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "f5ad688f8be10c23dacc853ec0120bef5c6c3e1f", "tree": "474ca95ab1203026b761fbcfd325ab99390bcf32", "parents": [ "86bf6ab8876898d93ec19472190d8a2d0d56056e" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 12:09:13 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:30:42 2019 +0000" }, "message": "flashchips.c: Add comma after every .voltage attribute\n\nTo allow automated tools to manipulate flashchips.c, ensure that every\nvoltage attribute ends with a comma, even if it is the last member in\nthe definition.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33832\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\n" }, { "commit": "86bf6ab8876898d93ec19472190d8a2d0d56056e", "tree": "5001c54868278741c6675e2bf319128d88ef1b6e", "parents": [ "fdf5da43975808230f4e7c455dd0c57552622dfb" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 16:58:20 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:29:26 2019 +0000" }, "message": "flashchips: Drop dead code of AT26DF321\n\nThe definition for the AT26DF321 has been commented out since it was\nfirst added in 2008. The chip now appears to be obsolete, being marked\n\"obsolete\" and unstocked at Digikey. It is also only referred to in\nhistorical documents on the manufacturer\u0027s website (microchip.com).\n\nTo avoid further bitrot of this dead code, drop it.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "fdf5da43975808230f4e7c455dd0c57552622dfb", "tree": "27b3ddb8e2b32af53ce543deea1526b96b09fbd5", "parents": [ "cbb85c007605c4c643aa99738981ee6284644667" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 16:56:52 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Jul 03 13:08:52 2019 +0000" }, "message": "flashchips.c: format block_erasers members\n\nTo allow automated tools to manipulate flashchips.c, ensure all\n.block_erasers definitions have consistent formatting:\n- start with the opening brace on a new line.\n- ensure end brace indented exactly two tabs.\n\nSFDP-capable chip is the one exception to this rule as it has an empty\nblock instead.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33831\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cbb85c007605c4c643aa99738981ee6284644667", "tree": "d8a51d547c2ebafb629219854350355ae8438299", "parents": [ "57938f86991548c2efa62cb0fabd30f8090847b3" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Jun 25 13:42:34 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:49:26 2019 +0000" }, "message": "flashchips.c: Make end of line comments consistent\n\nTo allow automated tools to manipulate flashchips.c, make end of line\ncomment formatting more consistent. Specifically, this change moves the\ncomma from end of line to immediately after the field value, before the\ncommment.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33830\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "57938f86991548c2efa62cb0fabd30f8090847b3", "tree": "c93fc8e290c4d3a80ce0b2dd1bbda2bd770422a0", "parents": [ "fa3fcd3ab353deb959130ee82f72f845f0fd8209" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:06:43 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:46:38 2019 +0000" }, "message": "flashchips.c: ATMEL-\u003eAtmel for consistency\n\nReplace the single instance where a vendor name was spelled\ninconsistently.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33829\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa3fcd3ab353deb959130ee82f72f845f0fd8209", "tree": "1b0839e1cb7b8e257ded1dd9d132b043c76f486a", "parents": [ "f75d8c558778a47e90f814860b3c664115aefc36" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:41:50 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:45:53 2019 +0000" }, "message": "flashchips.c: Make whitespace consistent\n\nFor consistency, and to make the file amenable to manipulation by tools,\nuse only tabs when indenting. Some previous changes had introduced\nspaces for indenting.\n\nAlso ensure that every table entry is separated by a single blank line.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib2193798cc52641d6c443f8851903c749b31cb74\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33828\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f75d8c558778a47e90f814860b3c664115aefc36", "tree": "7ceb5b5f2a4c4ae037e48290f747c61240e711de", "parents": [ "0a0b45bba6c1f467958c92620110a731d4917c89" ], "author": { "name": "David Tomaschik", "email": "davidtomaschik@google.com", "time": "Thu Jun 20 09:49:01 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 28 06:44:59 2019 +0000" }, "message": "Add support for MX25U25635F\n\nThis is a 256Kb part with support for JEDEC 4 byte addressing modes.\nTested successfully for probe/read.\n\nChange-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c\nSigned-off-by: David Tomaschik \u003cdavidtomaschik@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33639\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0a0b45bba6c1f467958c92620110a731d4917c89", "tree": "d5d6b03b2dfb1e1db99770fddf4e4a9f50a5969b", "parents": [ "deeac7e41a311a0806af0e65a2ce5c6673f9cf92" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Wed Jun 26 10:35:11 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 28 06:42:41 2019 +0000" }, "message": "cli_classic: Remove old usage warnings\n\nWe are at version 1.1 now, and the user interface change in 0.9.6 was\nto make setting the programmer mandatory. This was done all the way\nback in 2012, so it is safe to remove these warnings now.\n\nChange-Id: If1b379b7b8234d50a2f0a4f522f15820a1a6603c\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33815\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "deeac7e41a311a0806af0e65a2ce5c6673f9cf92", "tree": "2ff1082bf9ed049c2863deff9a6d66b6980b1812", "parents": [ "959aafa53eeae4f22766b9d098e5ca952af8c070" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:25:15 2019 +0000" }, "message": "spi: Drop spi_controller type\n\nNot needed anymore. Drop it fast before it encourages anyone to\nviolate layers again!\n\nChange-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33651\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "959aafa53eeae4f22766b9d098e5ca952af8c070", "tree": "12b2cf5512e0331370f75645a73372750f273d46", "parents": [ "afc3ad64300bbcc14266e645beec897ef06df13d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:13:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:24:47 2019 +0000" }, "message": "spi25: Fix layering violation in probe_spi_rdid4()\n\nMove the message to a lower level where we can do a more generic check\nand don\u0027t need internal knowledge of the SPI-master driver.\n\nChange-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33650\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "afc3ad64300bbcc14266e645beec897ef06df13d", "tree": "d356edb82af5f5d530c36626b575467c80136211", "parents": [ "cd8aeba7f1cee4c2bd1f8598009fc3e6e7afd8bb" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Jun 24 16:05:28 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 26 07:25:01 2019 +0000" }, "message": "tree: Make internal variables static\n\nAll these variables are only used in the files they are defined in, so\nthey can be made static.\n\nChange-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33747\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cd8aeba7f1cee4c2bd1f8598009fc3e6e7afd8bb", "tree": "4ad6bbf2cc48fa388bdbfd12f6dfe76819b9cdbc", "parents": [ "cf3976e658e06464e84d04c5230c466e0ec44df7" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:43:19 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:40:20 2019 +0000" }, "message": "Makefile: Enable -Wmissing-prototypes\n\nChange-Id: Ia2ea3dee11e505c04a9e7956417615e39d511886\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33670\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cf3976e658e06464e84d04c5230c466e0ec44df7", "tree": "a5d76371a4e67765060f63693568c9a3f26da8c1", "parents": [ "6c68363d0c1db0fd5e2ac95fb4adeaf254f669a7" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:40:33 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:40:09 2019 +0000" }, "message": "tree: Remove unused functions with no prototypes\n\nThese functions are no longer used, or were never used in the first place.\n\ngenerate_testpattern() - Introduced in commit eaac68bf8b, never used\nlist_programmers() - Introduced in commit 552420b0d6, never used\npci_dev_find_filter() - Prototype removed in commit 5c316f9549\nerase_chip_jedec() - Usage and prototype removed in commit f52f784bb3\nprintlock_regspace2_blocks() - Introduced in commit ef3ac8ac17, never used\nspi_write_status_enable() - Usage dropped in commit fcbdbbc0d4\n\nChange-Id: I742164670521fea65ffa3808446594848ce63cec\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33669\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "6c68363d0c1db0fd5e2ac95fb4adeaf254f669a7", "tree": "d04d0449d10e7d37744447aebae8530af02edd9a", "parents": [ "beeb8bc925bef6973e1c9fa6c4fd26a4113a1777" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:33:09 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:39:48 2019 +0000" }, "message": "tree: Include missing headers for function prototypes\n\nThese files all contain functions whose prototypes are in header files,\nso make sure those header files are included.\n\nChange-Id: I0189a1550bf90d4a0b87dcef9f8a8449590cc9d7\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33668\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "beeb8bc925bef6973e1c9fa6c4fd26a4113a1777", "tree": "30c63cf4ae4bb14a19849b1680622ad6eed86d63", "parents": [ "cb44eb7dad17522f47792dca4fc499310ff7d6f3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:24:17 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:39:31 2019 +0000" }, "message": "tree: Make internal functions static\n\nNone of these functions are used outside of the files they are defined\nin, so make them all static.\n\nChange-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33667\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "cb44eb7dad17522f47792dca4fc499310ff7d6f3", "tree": "026822102436ac0dcda8d8d007f16757ad73488b", "parents": [ "712ba3a0659a70c2e93a55d9e194b2fae6db28d1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 13:06:51 2019 +0000" }, "message": "bitbang_spi: Drop bitbang_spi_master_type\n\nIt only existed to make maintenance harder and waste our time.\n\nChange-Id: I7a3b5d9ff1e99d2d4f873c6f19fb318f93762037\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33638\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "712ba3a0659a70c2e93a55d9e194b2fae6db28d1", "tree": "fe655d8877332059bcda1ea220466d2e45589d42", "parents": [ "e276411e82588e93a8578b5eadd672ecd35058ee" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:11:49 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:08:58 2019 +0000" }, "message": "ft2232_spi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: Ia4762d0c0601d56528de56658b869b62fbe5b263\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33346\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e276411e82588e93a8578b5eadd672ecd35058ee", "tree": "e097d63f30075b36a289683ff922ba7a89f2c6da", "parents": [ "a67ac58dd7d62de17b7d1d8a13b327dd825502f6" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:09:25 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:08:30 2019 +0000" }, "message": "fmap.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: I5df4d8075be012b9edf7be520d611042d9945094\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33345\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "a67ac58dd7d62de17b7d1d8a13b327dd825502f6", "tree": "d4947a65cccf6a2c166bfc173db0cd36925d9875", "parents": [ "ec819d6ccc2575f2b600b2570bb20ffde91e1bbf" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:06:50 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:07:47 2019 +0000" }, "message": "dmi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: I71ab1fec98c2b61d73aeb646ddfc810662d4136d\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33344\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "ec819d6ccc2575f2b600b2570bb20ffde91e1bbf", "tree": "1a912f89cf703649bfa67967ac47637e540e6243", "parents": [ "29e46d0aa6ec9ce0b5234bf3bdbd9f22c951252c" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:50:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:07:09 2019 +0000" }, "message": "serprog.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: I9015020889c25ecbd391a18f56f99affc8ea307d\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33348\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "29e46d0aa6ec9ce0b5234bf3bdbd9f22c951252c", "tree": "5c2e329fbd6ca08b5dfe66c65eb8fa00049ff7ab", "parents": [ "504215b9f68e26938eea75afcbc22bdf389af991" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:38:25 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:06:47 2019 +0000" }, "message": "ichspi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: Ie000732158f27632ee92404c66a9aab43f3b374c\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33347\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "504215b9f68e26938eea75afcbc22bdf389af991", "tree": "85f3be7cd8fb2512a2eca63eb2ac3f3cf2456ce9", "parents": [ "477e1693c830d3246c4fd7caae8a2f2b8e9f49c1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:13:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 12:00:34 2019 +0000" }, "message": "spi25: Fix layering violation in default_spi_write_aai()\n\nChange-Id: I8aa3e2992f64906edc669060936f9522d32637fb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33649\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "477e1693c830d3246c4fd7caae8a2f2b8e9f49c1", "tree": "1c0680caa6ef647771fec6994e474af6de76e552", "parents": [ "d8b2e808cd46986f945ba9cf3b90c70fe58de9c6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 18 23:56:01 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:54:37 2019 +0000" }, "message": "dediprog: Bail out on unsupported, long transfers\n\nChange-Id: I7b16701597909c015f98199e73ebb7d923f2b072\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33614\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Ryan O\u0027Leary\nReviewed-by: ron minnich \u003crminnich@gmail.com\u003e\n" }, { "commit": "d8b2e808cd46986f945ba9cf3b90c70fe58de9c6", "tree": "4094be4996c4ae32a78e0e13c558ee78bcdd85dc", "parents": [ "0373ce31fe5b11dcf23b27fbc221ba019a1cf7f1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 18 23:39:56 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:54:19 2019 +0000" }, "message": "spi: Move 16MiB partitioning up into spi_chip_read()\n\nWe enforced a 16MiB limit in spi_read_chunked() for multi-die flash\nchips that can\u0027t be fully read at once. The same limit can be useful\nfor dediprog programmers. So move it into a more generic place.\n\nChange-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33613\nReviewed-by: Ryan O\u0027Leary\nReviewed-by: ron minnich \u003crminnich@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "0373ce31fe5b11dcf23b27fbc221ba019a1cf7f1", "tree": "473242727e8cd1df910c3787c42857ff8ab9741e", "parents": [ "5ca5523fd8f6800c32cbc8f3724b393e791cebd6" ], "author": { "name": "Paul Menzel", "email": "pmenzel@molgen.mpg.de", "time": "Wed Oct 04 13:14:13 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:51:30 2019 +0000" }, "message": "print: Update Asus URLs to use more secure HTTPS\n\nAsus set up HTTPS for their site, and redirects to that by default. So,\nuse this by default, which also saves one redirect.\n\n```\n$ curl -I http://www.asus.com/\nHTTP/1.1 301 Moved Permanently\nContent-Length: 0\nLocation: https://www.asus.com/\nDate: Wed, 04 Oct 2017 11:15:14 GMT\nConnection: keep-alive\nX-Akamai-Device-Characteristics: desktop\nX-Akamai-Device-Model: ; ; cURL; cURL\n```\n\nUse the command below to change the occurrences.\n\n```\nsed -i \u0027s,http://www.asus.com,https://www.asus.com,g\u0027 print.c\n```\n\nChange-Id: I62319bfbf39c73f98ed3f865a11f4fe870befee4\nSigned-off-by: Paul Menzel \u003cpmenzel@molgen.mpg.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/21874\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "5ca5523fd8f6800c32cbc8f3724b393e791cebd6", "tree": "f68209e48c9c54006a5af5c09e6d0b5d4ad1c9d9", "parents": [ "70461a9524fc84ec5c095f11927cffa0429a6267" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 22:29:08 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:33:09 2019 +0000" }, "message": "layout: Introduce layout_next_included()\n\nChange-Id: Ib01c8af06c3f84eafbd585760e74c3c287b9fa7d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33518\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "70461a9524fc84ec5c095f11927cffa0429a6267", "tree": "0df6b67aec1d936bf8b39a86d5d9ed97ef5aa125", "parents": [ "4f213285d78974c4b8915b311aff88449279f554" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 14:56:19 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:32:43 2019 +0000" }, "message": "layout: Make `romentry.name` a pointer\n\nThis should provide more flexibility while we don\u0027t have to allocate\n256B extra per layout entry.\n\nChange-Id: Ibb903113550ec13f43cbbd0a412c8f35fe1cf454\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33515\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4f213285d78974c4b8915b311aff88449279f554", "tree": "6927f36d10acff0bee42054d881072354dff192c", "parents": [ "2b94cdb5cb2a33958b2b0165e02bec17a58a8494" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 17:33:49 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:31:18 2019 +0000" }, "message": "layout: Move generic layout functions into `layout.c`\n\nChange-Id: If1edde70fc51e88e6e1c560d79a0d51941b9627c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33514\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "2b94cdb5cb2a33958b2b0165e02bec17a58a8494", "tree": "fb28dffe7e4c2e8bf09b606f98869cffcf30c0bb", "parents": [ "b04fef91c100d815265bc1948e61a62f284c42ef" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 18:19:26 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:31:07 2019 +0000" }, "message": "layout: Never use global `layout` directly\n\nAnd rename it to `global_layout` to free `layout` as a local variable\nname. We will get rid of the global layout entirely later.\n\nChange-Id: Ia2d7d1f4f649cd239b559ba6a40ee0977004e774\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33513\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "b04fef91c100d815265bc1948e61a62f284c42ef", "tree": "9446fe01e60f38fde4dd777602a1e8dab2cce8cd", "parents": [ "ee13d0c8fa365455002b109ded7f94f990be8347" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Feb 05 17:35:05 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:03:12 2019 +0000" }, "message": "layout.c: Don\u0027t use global variables for included regions\n\nThis removes the use of global variables for included region arguments\nand also uses a linked list to store the arguments.\n\nChange-Id: I6534cc58b8dcc6256c2730c809286d8083669a6c\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31247\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ee13d0c8fa365455002b109ded7f94f990be8347", "tree": "c2e9fc62f57b32ce0347a16646562db67528d2fb", "parents": [ "911b8d8bc425ad1e519013e68799c494bf60ca4f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 17:47:40 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 14 16:02:45 2019 +0000" }, "message": "libflashrom: Add CPP guard to fix big-endian builds\n\nCalm a compiler warning on big-endian builds about the unused static\nflashrom_layout_parse_fmap(). The guard is ugly but gets the job done.\nWe should forbid endian-specific code in the future, I guess.\n\nChange-Id: Id3f4a57e027f88cc469ed50312adddcc8af71a63\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33306\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "911b8d8bc425ad1e519013e68799c494bf60ca4f", "tree": "c79baaae62dd56fcaa2b34af2ad672eb70a7e8b7", "parents": [ "a724602fe0a573071c50a54e75dbe40ff43ecc1d" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Thu Jun 06 11:23:55 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 14 16:00:56 2019 +0000" }, "message": "cli: Add error on missing IFD\n\nWhen no IFD is present, but the option --ifd is specified, flashrom would just\nexit without printing a helpful error message.\n\nAdd error message that IFD could not be read or parsed.\n\nTested on Intel platform without IFD present.\n\nChange-Id: Ie1edd7f36f647c52b17799878185d1e69e10d3b0\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33245\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a724602fe0a573071c50a54e75dbe40ff43ecc1d", "tree": "2abea5c6783a7bcf8777550c594ba606d2c7de5a", "parents": [ "84c6fb5fe2b58c61dc4ed6a2026d2041a5beec5d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 17:39:18 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 08 20:47:32 2019 +0000" }, "message": "Makefile: Also blacklist J-Link SPI for DOS\n\nlibjaylink will probably never be available.\n\nChange-Id: Ie9222f82e16fe4c76fe7dd0f9aac7de6a862ab98\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33305\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "84c6fb5fe2b58c61dc4ed6a2026d2041a5beec5d", "tree": "1a91cb1f276a9a101b71740f74ff3af52e5cf238", "parents": [ "129e938e4c79caccc376d05869d2b2d08a0664ec" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 17:35:56 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 08 20:47:02 2019 +0000" }, "message": "Makefile: Blacklist Digilent SPI (using USB) for DOS\n\nChange-Id: I9a7dd5a2afcd12dd247e1f5534db61b79d77525e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33304\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "129e938e4c79caccc376d05869d2b2d08a0664ec", "tree": "9500d1d8476aaaf5ffb34f157a1e2862e55f028e", "parents": [ "32b9f5c665f4fd65d9ba742e72ae8e762f33762f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:43:27 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 12:32:14 2019 +0000" }, "message": "ich_descriptors: Drop line numbering comments\n\nChange-Id: Ia895e35edfc86b6955395c4570d67477da70e2c7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33256\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "32b9f5c665f4fd65d9ba742e72ae8e762f33762f", "tree": "40050630587b90d86f83e9d32e442d5e78b301ec", "parents": [ "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Feb 05 16:14:55 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 16:18:02 2019 +0000" }, "message": "layout.c: Use the libflashrom function for included arguments\n\nUse the libflashrom function to determine whether included regions are\npresent in the layout file.\n\nChange-Id: I5e9375baad763612e179262973413a7161acba8b\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31244\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "ba22411335f26601a76dbdf0d74a71e932b7cff8", "tree": "aaefbff11150db7ffd80d0ef2a1e3ea4d33e875d", "parents": [ "7eb38aa7dbd45cbc040ac513ed4375995246aa93" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Tue Jun 04 12:21:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 13:04:57 2019 +0000" }, "message": "dediprog: Allow 4BA on all protocol V2 devices\n\nTested on dediprog SF100 protocol V2 (firmware V:6.5.03).\nAssume it works fine on SF200 protocol V2, too.\n\nChange-Id: I8822b79f46876feff0fd443f711c57dffb67b349\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33195\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7eb38aa7dbd45cbc040ac513ed4375995246aa93", "tree": "0b96573c7ec755ca09aa8799501e307284f337e6", "parents": [ "17890b37f362e551e886506f39e7bf7181419457" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Mar 21 15:42:54 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Jun 04 13:54:54 2019 +0000" }, "message": "dediprog: Implement 4BA EAR mode for protocol v1\n\nWith an SF100 and protocol version 1, using the extended address\nregister of the flash chip seems safe. Make use of that and remove\nthe broken 4BA modes flag.\n\nTested with SF100 V:5.1.9 and W25Q256FV.\n\nChange-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32016\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "17890b37f362e551e886506f39e7bf7181419457", "tree": "9278586896099d40869319f64cd3124e1c4f902a", "parents": [ "f9632d82634bbbdc7e90357d3ea7c4a631ab4376" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Sun Jun 02 23:07:52 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 03 20:21:58 2019 +0000" }, "message": "chipset_enable: Mark Intel QS77 as DEP\n\nTested reading and writing with `-p internal` on MacBook Air 5,2 with\nIntel QS77.\n\nChange-Id: I508b6379507c2881c976d6baf7348b1161449cfe\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33164\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f9632d82634bbbdc7e90357d3ea7c4a631ab4376", "tree": "7534151dac52915dd1b1ebf8e462dc1a411a98e9", "parents": [ "4ca575dc5a81587da5affecd2cd97b7c8b4596b3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 20 11:23:49 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 03 10:46:01 2019 +0000" }, "message": "dummyflasher: Add emulation for Winbond W25Q128FV\n\nJust needed a 16MiB chip.\n\nChange-Id: Ic01d45c1f709808404ad53bb31f8b998c6977a9d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31011\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "4ca575dc5a81587da5affecd2cd97b7c8b4596b3", "tree": "f29d091284687337fb0757dbeb64cbe9ac24bb87", "parents": [ "93db6e16895287b7ac3a8a8f7f4a4f176547b7ed" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Mon May 20 11:31:44 2019 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon May 27 19:18:28 2019 +0000" }, "message": "usbdev: Only match requested USB devices\n\nDon\u0027t use a device that has the same vendor ID, but a different\nthan requested product ID.\n\nFixes broken dediprog detection with TOMU in use.\n\nChange-Id: I08c1c363ce2d6603e46efecc61d3910e02314fca\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32891\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93db6e16895287b7ac3a8a8f7f4a4f176547b7ed", "tree": "5f7d8dcfce6b7bb62829251b381526fbdc2f5497", "parents": [ "cb97368328bc68698ab7e58a6d692635dfb1b1c7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 30 01:18:43 2018 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Apr 15 18:44:22 2019 +0000" }, "message": "dediprog: Enable 4BA support for SF600, protocol V2\n\nThe only combination we could successfully test so far is the SF600 with\nprotocol version V2 (firmware 7.2.21) and native 4BA commands. Let\u0027s\nenable that at least.\n\nChange-Id: I665d0806aec469a3509620a760815861fbe22841\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28804\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "cb97368328bc68698ab7e58a6d692635dfb1b1c7", "tree": "c2cd06a37dcad1ccb0ff5103317c932efca46d37", "parents": [ "dc5af547df8b2f852deb5ddad86bb90ff0fc50c0" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 11:44:22 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 02 17:33:27 2019 +0000" }, "message": "Add support for the meson build system\n\nThe fwupd project has to build in all kinds of crazy targets, e.g. for odd\nendians, odd instruction sets, and in odd ways, e.g. installing with a prefix\nof /app for projects like flatpak. We also have other \"robustness\" guarantees\nand therefore have a comprehensive set of CI tests which enable a lot of\nwarning flags and run linting and static analysis code like Coverity.\n\nRather than hack the Makefile I ported the codebase to use Meson.\nMeson is a(nother) next-generation build system used by a lot of open source\nprojects ranging from low level libraries to desktop software. As part of the\nport, I also copied the CONFIG_ logic from the makefile, e.g.\n\n Option Current Value Possible Values Description\n ------ ------------- --------------- -----------\n config_atahpt false [true, false] Highpoint (HPT) ATA/RAID controllers\n config_atapromise false [true, false] Promise ATA controller\n config_atavia true [true, false] VIA VT6421A LPC memory\n...\n\nAt the moment I\u0027m using the meson port so I can include flashrom as a subproject\nto fwupd as distros are not yet shipping libflashrom as a shared library.\n\nChange-Id: I3d950ece2a0568c09985eab47ddab9df1d0c43a2\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/31248\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "dc5af547df8b2f852deb5ddad86bb90ff0fc50c0", "tree": "3b23dcce1e43e520ca0a6db314d6920a89b1f72a", "parents": [ "3d7b1e3b5c04304d3680bd950e7672f6336b01d6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 16:54:59 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 02 16:55:43 2019 +0000" }, "message": "dediprog: Disable 4BA completely\n\nThis is an interim solution. We\u0027ll have to enable 4BA step-by-step for\neach dediprog protocol version.\n\nChange-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30386\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3d7b1e3b5c04304d3680bd950e7672f6336b01d6", "tree": "f316ba1bd2474850ff3267ff1acbbb2b9c7336cd", "parents": [ "0cacb11c6252b6e1f4f0a2a33b47717ff22995d9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 00:53:14 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 02 16:42:53 2019 +0000" }, "message": "Fix verification with sparse layouts\n\nThe full verification step was not accounting for sparse layouts.\nInstead of the old contents, combine_image_by_layout() implicitly\nassumed the new contents for unspecified regions.\n\nChange-Id: I44e0cea621f2a3d4dc70fa7e93c52ed95e54014a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30370\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\n" }, { "commit": "0cacb11c6252b6e1f4f0a2a33b47717ff22995d9", "tree": "062ee516f90ae51baf0f5c0f8ffe27c8c91bc4bb", "parents": [ "1cf369fb59546e705c5ca9368e629681c98b2893" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Feb 04 12:16:38 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 04 15:46:25 2019 +0000" }, "message": "Remove trailing whitespace\n\nChange-Id: I1ff9418bcf150558ce7c97fafa3a68e5fa59f11e\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/31227\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1cf369fb59546e705c5ca9368e629681c98b2893", "tree": "d09bd6e36811c7dcb085afdf8ae98d5ede49082c", "parents": [ "ae24b8bfd36bba528f7ff31145f37e1c6d6a840f" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Tue Feb 05 15:57:27 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 04 15:45:13 2019 +0000" }, "message": "layout.c: Remove unused variable\n\nChange-Id: I0c0c085999a12987376d75825fcf43e788a55a4b\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/31243\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "ae24b8bfd36bba528f7ff31145f37e1c6d6a840f", "tree": "f6643c929caba28baba6a3519336e3693fbc9951", "parents": [ "6e61e0cf9cf038d5f95bcbe5b6516d58ecd81d7d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 20 11:33:07 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 04 15:34:31 2019 +0000" }, "message": "layout: Add missing stdbool.h include\n\nChange-Id: I9a413d491038b29c832011a738f3b49e029dcf6f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/31013\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "6e61e0cf9cf038d5f95bcbe5b6516d58ecd81d7d", "tree": "00ef055c999d0c6ddec61f0dd500859908e22425", "parents": [ "db7482bb72035fab8386226d1720cde09e0c700e" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Jan 23 17:07:49 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 04 15:01:59 2019 +0000" }, "message": "Fix erasing of unaligned regions\n\nThe erase (-E) feature is somehow a brute force method, but still, if we\nare given a region to erase, we should make sure to restore surrounding\ndata if the erase block expands beyond the region.\n\nIt shares a lot of code with the write path. Though, experiments with\ncommon functions have shown that it would make the whole function even\nharder to read. Maybe we could add some abstraction if we ever need\nsimilar code on a third path.\n\nChange-Id: I5fc35310f0b090f218cd1d660e27fb39dd05c3c5\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/31068\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\n" }, { "commit": "db7482bb72035fab8386226d1720cde09e0c700e", "tree": "8a2114a45c22a44e01d8494f224b38c35b17cb71", "parents": [ "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 12:04:30 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 11 23:50:12 2019 +0000" }, "message": "Fix several -Wno-implicit-fallthrough warnings\n\nGCC is picky about the comment being where the break should go.\n\nChange-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30406\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2", "tree": "3d0a25e70f59aae1f0016adf7f001094b42c5426", "parents": [ "84b453e4d4140230bd4d72d530b2b08f9a51b4e2" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Jan 02 21:11:08 2019 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 19:08:37 2019 +0000" }, "message": "Fix one more -Wmissing-field-initializers warning\n\nFixes:\n\n ichspi.c: In function ‘ich_init_spi’:\n ichspi.c:1707:9: warning: missing initializer for field ‘component’\n\nChange-Id: Iee5728167963fece24822ad2e3ab7bd9d444b42c\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/31224\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "84b453e4d4140230bd4d72d530b2b08f9a51b4e2", "tree": "103cd0d186c54a7e80921a3813abd8d24292e581", "parents": [ "df4905822754ac1f303f7939f5b77b35e5ac4a67" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 15:30:39 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 19:08:33 2019 +0000" }, "message": "Fix a trivial calloc warning\n\nChange-Id: Id457c15555a6ca6333474601f92982446afa40ab\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/31223\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "df4905822754ac1f303f7939f5b77b35e5ac4a67", "tree": "547a0248de382233cecfc018a25996ffc0195b2d", "parents": [ "93e1625f9fb5f1080c40685488d006b2982062d7" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 11:57:15 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 18:44:16 2019 +0000" }, "message": "Fix several -Wno-missing-field-initializers warnings\n\nChange-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30405\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93e1625f9fb5f1080c40685488d006b2982062d7", "tree": "810e5b2807d6f5c102059e2b8a99a91a17c8f9c7", "parents": [ "d82be7b2be34fb3273781e72f5d8e52a3103b961" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 11:54:47 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 18:31:45 2019 +0000" }, "message": "Fix several -Wold-style-declaration warnings\n\nChange-Id: Iffe5e652779a13ee7f64696fb5df4a781fe9a632\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30404\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "d82be7b2be34fb3273781e72f5d8e52a3103b961", "tree": "a2f2694e7cbbd18d52d3267167ffc3d4e3cff5b2", "parents": [ "6eca76123ca765e4afcfac43bfe2f27a5f977a97" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 15:38:51 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 05 16:26:01 2019 +0000" }, "message": "buspirate_spi: Fix a missing error check during _init()\n\nChange-Id: I17c6737853bf311b3f7aa9bfb10b54ce19e95ecc\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30407\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "6eca76123ca765e4afcfac43bfe2f27a5f977a97", "tree": "ed67581d106d0267c236ee643957684cd4eb919b", "parents": [ "3578ec6a3d7187438c4093f4bb7ac2bb6d4184cb" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 15:40:27 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 05 16:25:49 2019 +0000" }, "message": "Fix a tiny memory leak in the CLI tool\n\nChange-Id: Iec696cb15dcf437f08e1e4f2a5a1faa0df6fd081\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30408\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3578ec6a3d7187438c4093f4bb7ac2bb6d4184cb", "tree": "53c7ccc03fa21dcd4664e6fb1b48a9ec1661e023", "parents": [ "9cecc7e25dc3fe27a801a745410825cfc2cfaac3" ], "author": { "name": "Marc Schink", "email": "flashrom-dev@marcschink.de", "time": "Thu Mar 17 16:23:03 2016 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 05 16:25:04 2019 +0000" }, "message": "Add initial J-Link SPI programmer\n\nTested with SEGGER J-Link EDU, Flasher ARM and flash chip W25Q16.V.\n\nChange-Id: Ie03a054a75457ec9e1cab36ea124bb53b10e8d7e\nSigned-off-by: Marc Schink \u003cflashrom-dev@marcschink.de\u003e\nReviewed-on: https://review.coreboot.org/c/28087\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9cecc7e25dc3fe27a801a745410825cfc2cfaac3", "tree": "4d2f9f1d8959db64600e2ce61844726ada00781d", "parents": [ "099c8b2d5faae4d7f49c01c856f78398b743baa3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 00:08:50 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 23:03:57 2018 +0000" }, "message": "linux_spi: Hardcode default spispeed of 2MHz\n\nLeaving the `linux_spi` driver\u0027s unknown default is almost never what we\nwant and resulted in many support requests since Raspbian switched to a\ndefault that is too high for most applications.\n\nChange-Id: I9361b7c1a1ab8900a619b06e1dae14cd87eb56c2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/30368\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "099c8b2d5faae4d7f49c01c856f78398b743baa3", "tree": "738cd19feef5a59b0b4b8cfaf9beac3ed9145a67", "parents": [ "e7cbfae69e2bdf22018f14fbaf076a78995a2b60" ], "author": { "name": "Tristan Corrick", "email": "tristan@corrick.kiwi", "time": "Sat Dec 22 00:41:54 2018 +1300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 13:07:34 2018 +0000" }, "message": "chipset_enable.c: Mark Intel C224 as DEP\n\nTested on a Supermicro X10SLM+-F. The flash chip has been read, written,\nand erased many times without issue. Most boards with this chipset will\nhave the ME region locked, hence the selection of DEP.\n\nChange-Id: I25126b94e691289a7b29dd81d5c864854a4e0245\nSigned-off-by: Tristan Corrick \u003ctristan@corrick.kiwi\u003e\nReviewed-on: https://review.coreboot.org/c/30361\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e7cbfae69e2bdf22018f14fbaf076a78995a2b60", "tree": "5dc0687acc4661c6a010c96f2c0d800aee42501f", "parents": [ "ba72e91ec13f6adfd018a7af394a0d1db3ab2f81" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Dec 10 15:21:40 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 21 13:37:03 2018 +0000" }, "message": "libflashrom.h: Add missing includes\n\n\u003cstddef.h\u003e for `size_t` and \u003csys/types.h\u003e for `off_t`.\n\nChange-Id: Ifc84dfe2a06633321d0abd364bdea1216925a779\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/30153\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ba72e91ec13f6adfd018a7af394a0d1db3ab2f81", "tree": "312dc0bb35b45409a16eecab028a953eaad78df2", "parents": [ "bbaa1719b13908ae570c93eba74e5b5f990e8271" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Dec 11 12:10:04 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 21 13:36:56 2018 +0000" }, "message": "fmap: Fix length calculation in error message\n\nChange-Id: Ie0f448970de6a7829f304448e0835eaeb7d103a3\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/30152\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "bbaa1719b13908ae570c93eba74e5b5f990e8271", "tree": "c562597f1417c201eac0a7f8edb1ad71ca515635", "parents": [ "7fb508dc137818587bf142ec1f28fbc1c3a371fc" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Dec 05 13:26:20 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 06 15:47:35 2018 +0000" }, "message": "dediprog: Fix small, unaligned reads\n\nThis never was a use case until now but the `--fmap` code makes it\nobvious: Unaligned reads that were smaller than the `chunksize` here,\nwere extended without considering the length of the buffer read into.\n\nWith that fixed we run into the next problem: dediprog_spi_bulk_read()\nshouldn\u0027t report an error when an empty read is unaligned.\n\nChange-Id: Ie12b62499ebfdb467d5126c00d327c76077ddead\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/30051\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7fb508dc137818587bf142ec1f28fbc1c3a371fc", "tree": "10d295db825b47c407d21f37e66bb4b7eff9e40a", "parents": [ "f2cd32570eb8624c60e97aecd5c9045249b376fe" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Nov 02 14:25:31 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Nov 03 11:33:25 2018 +0000" }, "message": "chipset_enable.c: Mark Intel PM55 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nPavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since\nall ME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29437\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f2cd32570eb8624c60e97aecd5c9045249b376fe", "tree": "6a268512dc000d2a0e0a08e68ccad9df4b5853c5", "parents": [ "c4e9fd0abc51959885aafe6312a2d8c9b3935434" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:03:45 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 01 16:37:32 2018 +0000" }, "message": "flashchips: Add Sanyo LE25FU206/A and LE25FU106B\n\nAs per user `The_Raven Raven` on the mailing list. Since the added\nvalues had some inconsistencies, the chips are marked as untested.\n\nChange-Id: I6c26aafdca232110986334e85297d73d513600dc\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28813\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c4e9fd0abc51959885aafe6312a2d8c9b3935434", "tree": "d04cdf7484dac323c64eff0ec80526d26e2f3aa5", "parents": [ "61818dc098edf3bf41f2d6502456fe0cd078c007" ], "author": { "name": "Tristan Corrick", "email": "tristan@corrick.kiwi", "time": "Thu Nov 01 00:33:57 2018 +1300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 01 11:06:07 2018 +0000" }, "message": "chipset_enable.c: Mark Intel H81 as DEP\n\nTested on an ASRock H81M-HDS. The flash chip has been read, written, and\nerased many times without issue. Most boards with this chipset will have\nthe ME region locked, hence the selection of DEP.\n\nChange-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4\nSigned-off-by: Tristan Corrick \u003ctristan@corrick.kiwi\u003e\nReviewed-on: https://review.coreboot.org/29391\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "61818dc098edf3bf41f2d6502456fe0cd078c007", "tree": "ac2ba748f001cf84e2b69edbc48f169adac70797", "parents": [ "4987679d73fbbf270c4c2ee628652985d02de3c4" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Oct 28 01:02:21 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 30 09:39:15 2018 +0000" }, "message": "flashchips: Add IS25LP256 and IS25WP256\n\nTested IS25LP256 using Raspberry Pi and Dediprog SF600 programmers.\nTested IS25WP256 using Dediprog SF600.\n\nChange-Id: Idf7a224abcde5f7935d9ef88309f78207de60a7a\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29306\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4987679d73fbbf270c4c2ee628652985d02de3c4", "tree": "b07ff5f9d3a2de7e04b9ba7179bccfd8d0d81134", "parents": [ "3a41e2a27e45f17889b0789eb2ba43b97af0d1b6" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 27 20:19:42 2018 +0000" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Oct 29 22:50:49 2018 +0000" }, "message": "flashchips: Add W25Q256JV support\n\nSimilar to W25Q256FV, but it supports the native 4BA page program\ninstruction (12h). Note that the variant with QE enabled by default\nshares the device ID of the W25Q256FV.\n\nTested using a Raspberry Pi.\n\nChange-Id: I76d7362777d364594d2a733d7e478741b0bef7c4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29305\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3a41e2a27e45f17889b0789eb2ba43b97af0d1b6", "tree": "e3dad0477a3486c447feb447aae67d2057132f66", "parents": [ "f56607e66bdce71ec992c167633c7e7f0eb0482c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 17:45:59 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 23 21:15:53 2018 +0000" }, "message": "dmi: Remove nonsense guard; Makefile handles it\n\nChange-Id: If4216be1f9ed308e4580c36d0356480e637ffc82\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/28715\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "f56607e66bdce71ec992c167633c7e7f0eb0482c", "tree": "737e077587a7356ade0d48cf1ac80a935330b7d5", "parents": [ "c82900b661420989856a969cd9edf27410b758eb" ], "author": { "name": "Kasper Revsbech", "email": "krev@triax.com", "time": "Fri Oct 19 23:59:17 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 23 21:15:45 2018 +0000" }, "message": "flashchips: Mark MX25L25635F as tested\n\nAs reported by Kasper Revsbech on 2018-10-19.\n\nChange-Id: Icf05288c4e7e34af2e3f4b951457df695078847d\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29202\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c82900b661420989856a969cd9edf27410b758eb", "tree": "2f0ac2c60530769830ee6386047712fb46cdccd0", "parents": [ "4acc3f3a8990cda15f04e5eabf028c5cda0d6619" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Wed Jan 10 12:48:16 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 23 21:15:05 2018 +0000" }, "message": "Add support to get layout from fmap (e.g. coreboot rom)\n\nFlashmap, or simply fmap, is a binary data format for describing\nregion offsets, sizes, and certain attributes and is widely used by\ncoreboot. This patch adds support for the fmap data format version 1.1\nand adds --fmap and --fmap-file arguments.\n\nUsing --fmap will make flashrom to search the ROM content for fmap\ndata. Using --fmap-file will make flashrom search a supplied file\nfor fmap data.\n\nAn example of how to update the COREBOOT region of a ROM:\nflashrom -p programmer --fmap -w coreboot.rom -i COREBOOT\nflashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT\n\nThe fmap functions are mostly copied from cbfstool.\n\nCurrently it is made mutually exclusive with other layout options until\nwe are more clever about this input.\n\nChange-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/23203\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "4acc3f3a8990cda15f04e5eabf028c5cda0d6619", "tree": "ce763d072afff4636de2c9fc9f8622ebfc67cc18", "parents": [ "73ab88d58ee6ca1f0a822faafe0b14996e65ddbf" ], "author": { "name": "Sergey Alirzaev", "email": "zl29ah@gmail.com", "time": "Wed Aug 01 16:39:17 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 08 14:01:08 2018 +0000" }, "message": "ft2232_spi: add an ability to use GPIO for chip selection\n\nChange-Id: I6db05619e0d69ad18549c8556ef69225337b1532\nSigned-off-by: Sergey Alirzaev \u003czl29ah@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28911\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" } ], "next": "73ab88d58ee6ca1f0a822faafe0b14996e65ddbf" }