)]}' { "log": [ { "commit": "6bd4f10ed9f24c1ac60f18598edef0b45b4885c3", "tree": "4e97539643c3599f8ff5577a462387f406dd9d99", "parents": [ "2e0a0031139fe9aa4e7ad3259c6a864112b06f11" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 22 23:28:13 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "edi: Move EDI related things into new chipdrivers/edi.h\n\nChange-Id: I592449693647587b5817614b6c6cac07e8009a89\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/421\n" }, { "commit": "fbc41d2a932ede9c02aa7803472c31f39ec200f2", "tree": "8b72b78abfd99bf8737b90cc2fece11f2dbe93d3", "parents": [ "966dc9b776c2897d1245937639ab41fc834d7cb9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 22 23:04:01 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Move SPI related things into new chipdrivers/spi.h\n\nA few things that rely heavily on `flash.h` are moved there instead:\n* function signatures containing `erasefunc_t`,\n* the inline default_wrsr_target() that needs to know struct flashctx.\n\nThis allows to keep the new header file free of a transitive `flash.h`\ninclude.\n\nChange-Id: Ib215821feeb822ea3fc11bf9f48c0328f9a394d4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/416\n" }, { "commit": "966dc9b776c2897d1245937639ab41fc834d7cb9", "tree": "517dabeaf5bf7e79fbbdbf988cd2ef7734b7b0d9", "parents": [ "af9d738a66a885f19fdb0659455834f114d9d1e0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 07 21:59:15 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "Use new probing path for chips w/o IDs\n\nWe used to have a probe_noop() that simply assumed a chip is there\nbut wasn\u0027t called by default. Instead we can handle this case spe-\ncifically in the new probing path.\n\nChange-Id: I633c55f8de3a36c4de96f79fd938f58aa39b5bf9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/426\n" }, { "commit": "32f1ea8df501b41362058bb699a7ea96482e4db3", "tree": "294501d43632515901c1262e6e2b294d75ba3d1a", "parents": [ "b89c4524d978d3104ce3346894503e8d7b3fce51" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 15:11:48 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 22:42:55 2026 +0000" }, "message": "at45db: Use .prepare_access hook for non-power-of-2 preparations\n\nWe performed some additional preparations in probe_spi_at45db(). Turn\nit into a .prepare_access hook, spi_prepare_at45db(), so we can use\na pure probing function.\n\nChange-Id: I75570078301b9a06a229543f44714a0941457a5a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74895\n" }, { "commit": "ee8cf1c9c6218681f78193ba29c890bf9b7ba30a", "tree": "63429fd591599bc1bd63e0007d0f648324f4dd80", "parents": [ "4e6155afd4b0e1f5cf190cdd21fa83a656c4088a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 02 23:17:25 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 17:23:14 2025 +0000" }, "message": "Provide no-op probe function, always returning 1\n\nChange-Id: Ic0567a0da29790dbde24c432f3f1d4d109156165\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/315\n" }, { "commit": "55e788491607997ca93c86e58a38f2ac5dc73afe", "tree": "90be6d93bedff5fc983054de1e474d31aff6f559", "parents": [ "fbba4545dd9ec5ea7f3416370d6b71ccc85e3f7e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 21 00:46:19 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 03 17:54:48 2024 +0000" }, "message": "Introduce FLASHPROG_FLAG_NON_VOLATILE_WRSR\n\nAdd a new flag to our flash context that tells us if we should use\nvolatile or non-volatile status-register writes by default. Use it\nin the write-protection API. The logic to disable block protection\nautomatically stays as is for now, until we have established tools\nto manually control the protection.\n\nChange-Id: Ie9a41b6404991075e2bf76bcffbd4e9887c62c79\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/193\n" }, { "commit": "4ac536bde43a1d64e11034cab34aabd7a6efd5dc", "tree": "ceb3d304075fadbe31ed8d0d25dc8d4b8b8e60fb", "parents": [ "b1d2baea270c1177a78d1672b4f8dd42ed246eb4" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 21 00:22:29 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25_statusreg: Allow to write (non-)volatile bits specifically\n\nThere\u0027s a subtle difference between prepending a write-status-register\ncommand with a write enable (WREN) or an enable write status register\n(EWSR): The former targets non-volatile bits, while the latter targets\nvolatile bits, i.e. register bits that do not survive a reset.\n\nSometimes bits are implemented as both volatile and non-volatile. Then,\nthe non-volatile state is loaded into the volatile registers after chip\nreset, and writes with a WREN target both. So far, we simply used WREN\nwhen possible. This can, however, lead to unnecessary wear of the non-\nvolatile bits. Flash datasheets do not mention any maximum write cycles\nfor them. However, it is unclear if this is an academic issue, i.e. the\nmanufacturers account for the wear and implement redundancy, or if they\nsimply don\u0027t expect that many configuration changes.\n\nFor a start, allow to specify explicitly which kind of register bits we\nwant to write. We keep the current behavior. However, the logic to dis-\nable block protections automatically should be revised to prefer vola-\ntile writes.\n\nChange-Id: I807a2c48f4eaa85d5a10b37362e71818359a4c93\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/190\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "930d421385aae5ca93d5963fba7926970d7702e8", "tree": "199e15c17260fabb8e422075230621a21e064531", "parents": [ "8d0f4650c73eb7bcda0b71e514c0effdf37d90b5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 04 18:59:15 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Introduce generic spi_prepare_io()/spi_finish_io()\n\nIntroduce two new functions to be hooked up in the chip database:\n* spi_prepare_io(), and\n* spi_finish_io().\n\nThese will be used to prepare multi-i/o and QPI operations. Hence,\nhook them up to all the chips that support those. spi_prepare_4ba()\nis wrapped to account for overlaps with 4BA support.\n\nChange-Id: I444f6322b6d6a26a040cb0ca972b2c411838d702\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/163\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "8d0f4650c73eb7bcda0b71e514c0effdf37d90b5", "tree": "f27db276221972c6451278fa41806260ebfa7046", "parents": [ "044c9dc9290565ab7b9866bb26a8d077d9c3a5d7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 04 18:52:51 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Extract 4BA preparations into new `spi25_prepare.c`\n\nWe will have more preparation steps for fast-read operations and\nQPI in the future. Better start a new file, as `spi25.c` already\nis rather long.\n\nChange-Id: I253b270ce6796fb09e6d74903bd65a6fbc06c7d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/162\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "7679b5ccf987e4999fefed6c6100a7a8f50d4350", "tree": "d904cf0a8e68feb831380054ce5956cb3b96fdca", "parents": [ "ca1c7fdd6bd6f61029492fb7a194bd47119e465f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 28 21:48:53 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "spi25: Replace spi_read_chunked() with more abstract version\n\nThe new flashprog_read_chunked() takes a low-level reading function as\nargument. This allows us to make use of the chunking with non-SPI read\nfunctions.\n\nChange-Id: Ica1b616e75e4e7682120928588e231c82cf4cf70\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74865\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "ca1c7fdd6bd6f61029492fb7a194bd47119e465f", "tree": "6e0063b18b7b8e9b3b1ddc4da95620213331efb6", "parents": [ "e36e3dc90f81fc2a718e4b367eebff900af21126" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 28 21:44:41 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "spi25: Normalize parameters of spi_nbyte_read()\n\nMost other reading functions have the destination buffer\nas second parameter.\n\nChange-Id: Id3f91f3d23132b0706b3b33bbf156356c9bf5ebc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74864\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "b197402042a065554234700b69057e9b6eedc39a", "tree": "62e4b15dff887d157ad18dd09b3d47dd2d7f8c1a", "parents": [ "0e76d99a7c0eda11515923c5457f0b5a4af9893f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 13:13:12 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_bus: Split register mapping into own function\n\nNow that we have a hook for the memory mapping, we don\u0027t need\nFEATURE_REGISTERMAP anymore and can clean up around it.\n\nChange-Id: If11ece9ce81ddf214b75764007a1006d271dc8af\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72523\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "0e76d99a7c0eda11515923c5457f0b5a4af9893f", "tree": "c914d5266909dad441bece2705593131f032c19c", "parents": [ "9eec40780207a110f3ba7ea70d11c042c6d86abf" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 20:22:55 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_bus: Move (un)map_flash_region into par master\n\nNow that the map/unmap_flash functions are only called from memory-\nmapped chip drivers, we can safely move the hooks into the parallel\nmasters.\n\nThis also allows us to move the code away from the globals in\n`flashprog.c` into a new `memory_bus.c`.\n\nChange-Id: Ic476cf4d96200232900537b997e1d07bb4e8b809\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72522\nReviewed-by: Riku Viitanen \u003criku.viitanen@protonmail.com\u003e\n" }, { "commit": "9eec40780207a110f3ba7ea70d11c042c6d86abf", "tree": "f48e0860e967bd720901e9cf12faaa82363bf2c8", "parents": [ "56b53dd4c892c6f400f6b05797eb6ed4b96179db" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 01:17:30 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Perform default mapping only for respective chips\n\nThe default memory mapping for the whole flash chip only makes sense\nfor chips that are directly connected to a bus serving memory cycles,\ni.e. parallel, LPC and FWH chips. Use the new `.prepare_access` and\n`.finish_access` hooks to map/unmap respective chips.\n\nGoing through the chip driver for this allows us to free the core\nflashprog code from this peculiarity.\n\nChange-Id: I54d1554b44b7e21fc18ef066103a9a26a2783b36\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72521\n" }, { "commit": "ab6b18f0e0d4f4b2b8348306576b701b63372bd2", "tree": "f9adeb7ab53e6fed6d940f852979b5da86dd7de1", "parents": [ "901fb957742edef9307948c397bdd28c8b5ebfac" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 23:38:20 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "spi25: Move 4BA preparations into spi_prepare_4ba() hook\n\nThese preparations are specific to 4BA SPI chips and don\u0027t have to\nclutter `flashprog.c`.\n\nChange-Id: I842244c57e575f93b9c505e16f1f20c7afd23733\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72517\n" }, { "commit": "1338936efbd5301880063461b74eaf883db6e363", "tree": "ec0fd82dbaafd435bd3784d13378b1c4334f9e93", "parents": [ "8d36db619b5bca0d5a1ddf05c26926b460605e31" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Mar 05 18:35:30 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 08 18:09:43 2024 +0000" }, "message": "Consider 4BA support when filtering erase functions\n\nWhen we decide which erase functions to use, we need to know exactly\nwhich functions are supported by the used programmer. We missed that\nsome programmers can\u0027t send 4-byte adddresses. As we already have a\nfeature flag for this, check it right away for all 4BA erase opcodes.\n\nThis affects mostly rare combinations of external programmers with\nmodern 4BA flash chips. For instance early versions of the Dediprog\nSF100.\n\nTests confirmed that this fixes the combination of a first protocol\ngeneration SF100 with a Winbond W25Q256JV.\n\nChange-Id: I51da2832a6a703058da57cdc0335b214653453ed\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/99\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b0be3200954bebf2431c4d7bd441096f157f621e", "tree": "f77f849073a8e0a8d0f6105c55ef06b969d3c982", "parents": [ "3561451faed250ced4a55e15d1abe5e3d94abfc4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Sep 20 00:07:23 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi.c: Add AT45 erasefn opcode mapping\n\nflashrom-stable: Dropped spurious/wrong function description.\n\nChange-Id: I798a91f1e20b63662715c68e6d43d03fc6005d51\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67717\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72542\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3561451faed250ced4a55e15d1abe5e3d94abfc4", "tree": "dd5c68bd13dee2adfb609540c64bac463848b941", "parents": [ "e2ff4e90125680a48623a2a908bff38d5b91e44e" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Sep 19 23:46:58 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcode\n\nThis function works only with spi25 chips\n\nChange-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67716\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72541\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ab9f25893f1fa87cbbaf656869e346391eccdb31", "tree": "f21fc6e6e4541cd6905a17bcf3ace937a6e9b5ac", "parents": [ "b725c0cd0e1c3fb56807c197b965620ac37b996b" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Thu Jun 23 16:21:23 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi25.c: Add function to return opcode of passed erase fucntion pointer\n\nThere is a function, spi_get_erasefn_from_opcode, which returns the\nerase function for given opcode. Add a function which does the opposite\ni.e. returns the opcode for given erase function.\n\nChange-Id: Ia3aefc9b9465efdd16b1678bb2ada9a23f00d316\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65355\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72538\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "58015c25eb05fa77966d1c53261a83b56a3cf6b3", "tree": "a1df11881a074c8c66de756f846be9030ce0443a", "parents": [ "e276765eca031c6900d37b22b89e686283f39c91" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Apr 14 13:50:55 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "Introduce an `include` directory for header files\n\nMove all header files to the new `include` directory.\nAdapt include directives and build systems to the new directory.\n\nChange-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf\nSigned-off-by: Felix Singer \u003cfelix.singer@secunet.com\u003e\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72322\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "d1fbc465c6625b1f84378c603c335f6f794a0ee1", "tree": "14b0a8b64ecb4b2bd8f3e917c5429292fb7c0093", "parents": [ "405e72abc3d1bc7db8c7e132457d148cbc8b3dc6" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Dec 19 11:57:30 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 22 00:55:18 2023 +0000" }, "message": "chipdrivers.h: Trivial fix style of write_28sf040() signature\n\nThis is correct on the Chromium side so fix the missing space\nhere.\n\nChange-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48744\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72165\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "39687acc6bf41b955a11e8a8fa3f0029342cbb3e", "tree": "36f702391d17eae36554a2064297284a14cbc10b", "parents": [ "081ffbae47cbebda5611de101b9dd53b3a58b6bb" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:23:25 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "writeprotect_ranges.c: add more range functions\n\nNot all chips follow the same pattern. There are differences in how CMP\nbit is treated or in block size used.\n\nChange-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71008\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "fffc48d247cef5102113d97538054066546b2297", "tree": "cdb49567c3d7c2291fa33221989516afb1b03abf", "parents": [ "3f3c1f3238dcede30d0d15d36da6326b428b8b12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 14:26:06 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L\n\nThese chips seem to be rather regular, supporting 2.7V..3.6V, the\ncommon erase block sizes 4KiB, 32KiB, 64KiB and the usual block-\nprotection bits.\n\nStatus/configuration register naming differs from other vendors,\nthough. These chips have 2 status registers plus 3 configuration\nregisters. Configuration registers 1 \u0026 2 match status registers\n2 \u0026 3 of what we are used from other vendors. Read opcodes match\ntoo, however writes are always done through the WRSR instruction\nwhich can write up to 4 bytes (SR1, CR1, CR2, CR3).\n\nS25FL256L supports native 4BA commands and entering a 4BA mode.\nHowever, it uses an unusual opcode (0x53) for the 32KiB 4BA block\nerase.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I356df6649f29e50879a4da4183f1164a81cb0a09\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb", "tree": "85191d34786a8297b7618919e50b64095fa2cee0", "parents": [ "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 28 16:18:28 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "spi25_statusreg: delete spi_read_status_register()\n\nDelete the spi_read_status_register() function because the generic\nspi_read_register() function can be used instead.\n\nThis patch also converts all call sites over to spi_read_register().\nA side effect is that error codes are now properly propagated and\nchecked.\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n Read SR1/SR2 with --wp-status and activated various WP ranges\n that toggled bits in both SR1 and SR2.\n\nChange-Id: I146b4b5439872e66c5d33e156451a729d248c7da\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70975\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c9feb1bdfa96745a200b9a62dc4234446db8ddb6", "tree": "b532df293904cb48d7efa7b127a0072f48801835", "parents": [ "da1c834e9899e5094377a33d19daa53c0d88640b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:35:13 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "flashchips,writeprotect_ranges: add range decoding function\n\nAllow chips to specify functions that map status register bits to\nprotection ranges. These are used to enumerate available ranges and\ndetermine the protection state of chips. The patch also adds a range\ndecoding function for the example chips. Many other chips can also be\nhandled by it, though some will require different functions (e.g.\nMX25L6406 and related chips).\n\nAnother approach that has been tried in cros flashrom is maintaining\ntables of range data, but it quickly becomes error prone and hard to\nvalidate.\n\nUsing a function to interpret the ranges allows compact encoding with\nmost chips and is flexible enough to allow chips with less predictable\nranges to be handled as well.\n\nTested: dumped range tables, checked against datasheets\n\nChange-Id: Id163ed80938a946a502ed116e48e8236e36eb203\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70969\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0167522794a2e66f00248347122c1bb8ce3b001d", "tree": "ac01ed9312b2946bdcdbe1abf1078b69f6117183", "parents": [ "236a38cc46ac810d0be679402bb21e83aebcb8b9" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:30:41 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "spi25_statusreg: make register read/write functions generic\n\nThis patch adds new spi_{read,write}_register() functions that take the\nsource/destination register as an argument. Currently they can only\naccess SR1, support for other registers will be added in another patch.\n\nSince we\u0027re refactoring things, this commit also makes\nspi_read_register() return an error code, making it possible to identify\nerror conditions that spi_read_status_register() concealed.\n\nThis also removes the initial 100ms delay between writing a register and\nthe first attempt to check the chip\u0027s status. An initial delay was added\nto avoid needing to read the status register multiple times, but that is\nunlikely to cause problems on modern flash chips.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70964\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3d8868c2b46548be6885198987492d91933c9ff7", "tree": "2277db98f8b19982802f812b2a984a2591009e37", "parents": [ "4a84ec273a487c27f91bd3df70cbdf8894af70e1" ], "author": { "name": "Konstantin Grudnev", "email": "grudnevkv@gmail.com", "time": "Tue Jul 23 00:48:54 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:41:01 2019 +0000" }, "message": "Add support for M95M02-A125\n\nAutomotive 2 Mbit (256KiB) serial SPI bus EEPROM\nPREW tested successfully with use of ch341a programmer\non Linux host 5.2.0-1-MANJARO x86_64\n\nSigned-off-by: Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nChange-Id: Ic29cd9051c7eac4822d620c299834134f987f01b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34496\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "7eb38aa7dbd45cbc040ac513ed4375995246aa93", "tree": "0b96573c7ec755ca09aa8799501e307284f337e6", "parents": [ "17890b37f362e551e886506f39e7bf7181419457" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Mar 21 15:42:54 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Jun 04 13:54:54 2019 +0000" }, "message": "dediprog: Implement 4BA EAR mode for protocol v1\n\nWith an SF100 and protocol version 1, using the extended address\nregister of the flash chip seems safe. Make use of that and remove\nthe broken 4BA modes flag.\n\nTested with SF100 V:5.1.9 and W25Q256FV.\n\nChange-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32016\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "25584de9d0108a5dde41e0296fdf0a7854390a81", "tree": "d505c037e5a2e729e1eb64882c60fd69fcb1b40e", "parents": [ "1b365931ea8a9d5766972c17c7cf91b9de595fb1" ], "author": { "name": "Wei Hu", "email": "wei@aristanetworks.com", "time": "Mon Apr 30 14:02:08 2018 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun May 06 20:56:02 2018 +0000" }, "message": "flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)\n\nThis patch seems to have originally been from\nhttps://patchwork.coreboot.org/patch/4126/ . The most recent version\nseems to be in OpenEmbedded (commit 503a572) which added support for\n16Mbit and 32Mbit variants.\n\nThe OpenEmbedded patch also makes changes to linux_spi.c to add some\ndebug prints which are omitted in this version.\n\nFrom the original commit message:\nDifferences between SST26 and SST25:\n1. The WREN instruction must be executed prior to WRSR [Section 5.31].\n There is no EWSR.\n2. Block protection bits are no longer in the status register. There\n is a dedicated 144-bit register [Table 5-6]. The device is\n write-protected by default. A Global Block-Protection Unlock\n command unlocks the entire memory [Section 4.1].\n\nChange-Id: Ib019bed8ce955049703eb3376c32a83ef607c219\nSigned-off-by: Wei Hu \u003cwei@aristanetworks.com\u003e\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@student.tuwien.ac.at\u003e\nReviewed-on: https://review.coreboot.org/25962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "80ae14e5105bb938679193906d1ee43b7a51c094", "tree": "629130fad3e6b0b731429bb90dc8e285a91ea8ab", "parents": [ "995f755ff569cbf6ed8d4eec5920b41628aa8ac9" ], "author": { "name": "Paul Kocialkowski", "email": "contact@paulk.fr", "time": "Mon Jan 15 01:07:46 2018 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 11 16:53:34 2018 +0000" }, "message": "Add support for the ENE Embedded Debug Interface EDI and KB9012 EC\n\nThe ENE Embedded Debug Interface (EDI) is a SPI-based interface for\naccessing the memory of ENE embedded controllers.\n\nThe ENE KB9012 EC is an embedded controller found on various laptops\nsuch as the Lenovo G505s. It features a 8051 microcontroller and\nhas 128 KiB of internal storage for program data.\n\nEDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)\nwhen flash direct access is not in use. Some firmwares disable EDI at runtime\nso it might be necessary to ground pin 42 to reset the 8051 microcontroller\nbefore accessing the KB9012 via EDI.\n\nThe example of flashing KB9012 at Lenovo G505S laptop could be found here:\nhttp://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate\n\nChange-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854\nSigned-off-by: Mike Banon \u003cmikebdp2@gmail.com\u003e\nSigned-off-by: Paul Kocialkowski \u003ccontact@paulk.fr\u003e\nReviewed-on: https://review.coreboot.org/23259\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c", "tree": "53bda4d3445a94505455ffb12a96da602ba97af6", "parents": [ "1cf407b4f8d56035816efaf936a40553441eca46" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 21:10:20 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:30 2018 +0000" }, "message": "spi25: Revise decision when to enter/exit 4BA mode\n\nInstead of arbitrarily deciding whether to enter 4BA mode in the flash\nchip\u0027s declaration, advertise that entering 4BA mode is supported and\nonly enter it if the SPI master supports 4-byte addresses. If not, exit\n4BA mode (the chip might be in 4BA mode after reset). If we can\u0027t assure\nthe state of 4BA mode, we bail out to simplify the code (we\u0027d have to\nensure that we don\u0027t run any instructions that can usually be switched\nto 4BA mode otherwise).\n\nTwo new feature flags are introduced:\n\n* FEATURE_4BA_ENTER:\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.\n* FEATURE_4BA_ENTER_WREN\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.\n\nFEATURE_4BA_SUPPORT is dropped, it\u0027s completely implicit now.\n\nAlso, draw the with/without WREN distinction into the enter/exit\nfunctions to reduce code redundancy.\n\nChange-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22422\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7e3c81ae7122120fe10d43fcba61a513e2461de9", "tree": "f505342cd2879b9cc77c2cbf66dda0231869ee9c", "parents": [ "0ee2dc06839d2f4f3197dd0ef51202e51e945bea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:56:50 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:48:28 2017 +0000" }, "message": "spi25: Merge remainder of spi4ba in\n\nChange-Id: If581e24347e45cbb27002ea99ffd70e334c110cf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22388\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ecbacbfca7f919f1780f5062c775d94c7869d81", "tree": "2f84f6406d00bc89dd13dfeff3e69f77671a8f9e", "parents": [ "a3140d0b18058610a2694fc3592031a849b0c92a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 16:50:43 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:42:49 2017 +0000" }, "message": "spi25: Use common code for nbyte read/write and block erase\n\nIntroduce spi_prepare_address() and spi_write_cmd() and use them in\nnbyte_program, nbyte_read and block-erase procedures. The former\nabstracts over the address part of a SPI command to make it exten-\nsible for 4-byte adressing. spi_write_cmd() implements a WREN + write\noperation with address and optionally up to 256 bytes of data. It\nprovides a common path to reduce overall redundancy.\n\nAlso, reduce the polling delay in spi_block_erase_c4() from 500s to\n500ms as the comment suggests.\n\nChange-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22383\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "d94d254262594b912c65511b5d0675c6ab900d60", "tree": "6e972f84e4bc74db8b76292aadbcc52fd1fba3d7", "parents": [ "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e" ], "author": { "name": "Ed Swierk", "email": "eswierk@skyportsystems.com", "time": "Mon Jul 03 13:02:18 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:55 2017 +0000" }, "message": "4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressing\n\nChange-Id: I553e7fb5028f35e14a3a81b3fa8903c1b321a223\nSigned-off-by: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nReviewed-on: https://review.coreboot.org/20509\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7fe85694c4a597abb2a83c2f0f3a62a1a22e130e", "tree": "0da033666d79e9b3dc471762d1b02ee41a7a7a8d", "parents": [ "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:03 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:35:08 2017 +0000" }, "message": "4BA: Support for new direct-4BA instructions + W25Q256.V update\n\nLarge flash chips usually support special instructions to work with\n4-bytes address directly from 3-bytes addressing mode and without\ndo switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)\nand 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these\ninstructions are supported by all large flash chips. Some chips\nsupport 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends\non the manufacturer of the chip.\n\nThis patch provides code to use direct 4-bytes addressing instructions.\n\nThis code should work but it tested partially only. My W25Q256FV has\nsupport for 4BA_Read (13h), but doesn\u0027t have support 4BA_Program (12h)\nand 4BA_Erase instructions. So, direct 4BA program and erase\nshould be tested after.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashchips.c\n+ modified definition of Winbond W25Q256BV/W25Q256FV chips\n\nflashrom.c\n+ modified switch to 4-bytes addressing for direct-4BA instructions\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for read/write/erase directly with 4-bytes address (from any mode)\n\nChange-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20508\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5de3b9b7263196b1d2bf41659ca44c7ea386b8ab", "tree": "f3480e7191c83965a9ab97d429f090e07f30a552", "parents": [ "aa6c37444c1d1a5944ea8bb3912bb0efe27dffce" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:02 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:33:37 2017 +0000" }, "message": "4BA: Support for 4-bytes addressing via Extended Address Register\n\nOn some flash chips data with addresses more than 24-bit field\ncan address may be accessed by using Extended Address Register.\nThe register has 1-byte size and stores high byte of 32-bit address.\nThen flash can be read from 3-bytes addressing mode with writing\nhigh byte of address to this Register. By using this way we have\naccess to full memory of a chip. Some chips may support this method\nonly.\n\nThis patch provides code use Extended Address Register.\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nflashrom.c\n+ modified switch to 4-bytes addressing to support extended address register\n\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for write Extended Address Register\n+ functions for read/write/erase with Extended Address Register\n\nChange-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20507\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "50a5660c9c11c77c794783cd9a3343bc3ff07b6e", "tree": "7095a74f39788084a14c3657bc3b868f923f5340", "parents": [ "f4d7772cee806d68a06db5394ab85a6e76904e88" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:28:59 2016 +0200" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sat Oct 14 00:46:41 2017 +0000" }, "message": "4BA: Basic support for 4-bytes addressing mode extensions\n\nIf flash chip is switched to 4-bytes addressing mode then all\nread/erase/program instructions will be switched from 3-bytes mode\nto 4-bytes mode. Then well known instructions like 03h (Read),\n02h (Program) and 20h,52h,D8h (Erase) will become one byte longer\nand accept 4-bytes address instead of 3-bytes.\n\nThis patch provides support for well known instructions in 4-bytes\naddressing mode. Also here is the code to enter 4-bytes addressing\nmode by execute the instruction B7h (Enter 4-bytes mode).\n\nPatched files\n-------------\nchipdrivers.h\n+ added functions declarations for spi4ba.c\n\nflash.h\n+ feature definitions added\n\nMakefile\n+ added spi4ba.c\n\nAdded files\n-----------\nspi4ba.h\n+ definitions for 4-bytes addressing JEDEC commands\n+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)\n\nspi4ba.c\n+ functions for enter 4-bytes addressing mode\n+ functions for read/write/erase in 4-bytes addressing mode\n\nChange-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20513\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bcf6109a76a873fc1227402d4b5b13a87dc3eb1a", "tree": "a3b5a06e4e58d208ecf22c956cd8c160b4d52ebc", "parents": [ "94d8665ea34cb9678c4b08ea340c4a292e520a1d" ], "author": { "name": "Ben Gardner", "email": "bgardner@wabtec.com", "time": "Sun Nov 22 02:23:31 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Nov 22 02:23:31 2015 +0000" }, "message": "Add support for SST SST25WF020A, SST25WF040B, SST25WF080B\n\nApart from the strange ID (using Sanyo\u0027s vendor ID 0x62) the main\ndifference from the plain SST25WF series is that they lack op codes\n0xAD (AAI Word program) and 0x52 (32K erase). The smallest version\ndoes not support dual I/O operations either.\n\nSST25WF080B was tested under Linux with spidev.\n\nCorresponding to flashrom svn r1901.\n\nTested-by: Ben Gardner \u003cbgardner@wabtec.com\u003e\nSigned-off-by: Ben Gardner \u003cbgardner@wabtec.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5859ced80f17217e7e829b61b02bb18b66b4f8e4", "tree": "16c9266af61435d7f2603998a3730ec7be1e09ed", "parents": [ "e814a9b6e83deea2bbc9d287e8a9ee0a409a969e" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 20 16:45:31 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 20 16:45:31 2014 +0000" }, "message": "Fix handling of write protection at register space address +2\n\nSince r1833 we added the offset of the virtual register in several\nfunctions, which produced segfaults. This patch renames a few\nparameters and reorganizes/fixes various parts of the\nchangelock_regspace2_block() function - hence the rather big diff.\n\nThanks to Roman Lebedev for reporting this issue and testing numerous\nrevisions of this patch.\n\nCorresponding to flashrom svn r1859.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a8cf3620a42ca5927253822a813e3fbae1d6e7bf", "tree": "64ff1e62b06ee89492c914e11c86b54ddf126b0c", "parents": [ "6697f71ade7b6428c7be6051c02dbb9768900e04" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Aug 08 08:33:01 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Aug 08 08:33:01 2014 +0000" }, "message": "Unify non-shifted and shifted JEDEC access\n\nSome Parallel bus chips have a 16-bit mode and an 8-bit mode. They use\nnormal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)\nfor 8-bit mode. Some programmers can access them in 16-bit mode, but on\nall flashrom-supported programmers so far, we access them in 8-bit mode.\nThis means we have to shift the addresses but apart from the addresses\nwe can share the code.\n\nThis patch makes this possible by checking the chip\u0027s FEATURE_ADDR_SHIFTED\nflag in common JEDEC functions and applying the right addresses respectively.\n\nCorresponding to flashrom svn r1840.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "6697f71ade7b6428c7be6051c02dbb9768900e04", "tree": "23a2f8596d493396b7d9571ee91888e3f49c49f9", "parents": [ "88b19257cb41c97123d832460c944abc588a8e89" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 06 15:09:15 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 06 15:09:15 2014 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 21\n\nTested mainboards:\nOK:\n - ASUS F2A85-M\n Reported by various corebooters\n - ASUS M2N-MX SE Plus\n Reported by Antonio\n - ASUS P5LD2\n Reported by François Revol\n - Lenovo ThinkPad T530\n Reported and partially authored by Edward O\u0027Callaghan\n - MSI MS-7502 (Medion MD8833)\n Reported by naq on IRC\n - Shuttle AB61\n Reported by olofolleola4\n - ZOTAC IONITX-F-E\n Reported by Bernardo Kuri\n\nFlash chips:\n - Atmel AT45DB021D to PREW (+PREW)\n Reported by The Raven\n - Atmel AT25F4096 to PREW (+PREW)\n Reported by 공준혁\n - GigaDevice GD25Q16(B) to PREW (+PREW)\n Reported by luxflow@live.com using a GD25Q16BSIG\n - Catalyst CAT28F512\n Mark erase and write as known bad (not implemented)\n\nMiscellaneous:\n - Various spelling corrections by Daniele Forsi.\n - Added and refined a bunch of chips originally investigated by Carl-Daniel.\n - Marked the ARM-USB-OCD-H programmer as tested\n (reported by Ruud Schramp).\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1839.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "03a9c3c1bbfd1548888ff6386c30165efc4c7c00", "tree": "f10ff5edf6a8424d672f6774a00d03b51308629b", "parents": [ "7de939325b1c984eefdc65d079b6fe4416c86a12" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Aug 03 14:15:14 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Aug 03 14:15:14 2014 +0000" }, "message": "Add support for a bunch of 29GL parallel flash chips\n\n29GL chips use a new 3-Byte device ID probing function at addresses\n0x01, 0x0E, 0x0F.\n\nFlash chip families supported by this method include...\n - EON EN29GL\n - Gigadevice GD29GL (if they really exist)\n - ISSI (PMC) IS29GL\n - Macronix MX29GL (+MX68GL1G0F)\n - Spansion S29GL (+S70GL02G)\n - Winbond W29GL\n\nThis patch adds respective flash chip definitions for chips up to 16 MB from\nEon, ISSI, Macronix and Winbond. Bigger chips as well as those from\nGigadevice and Spansion are left out.\n\nCorresponding to flashrom svn r1835.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "ef3ac8ac17eac9d2041ea9c9e711a9b059412b59", "tree": "e5fec0cda5a546133a7440f65da442329ec3db48", "parents": [ "2a41f0a2c0daeb0ee2a38a252ab96135d70a6b81" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Aug 03 13:05:34 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Aug 03 13:05:34 2014 +0000" }, "message": "Refactor unlocking of many chips with locking at register space address +2\n\nThis includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families.\nThe erase and write test status bits of all affected chips have been reset.\n\nCorresponding to flashrom svn r1833.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a60d408a78be0e0d34dda616977489a307cb98b6", "tree": "012c6fd5e70fa651b144f556c7e3a0b3f605d18a", "parents": [ "2a10e70cd3b3e974c173b035dae01bf53899c228" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Jun 04 16:17:03 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Jun 04 16:17:03 2014 +0000" }, "message": "Add support for Sanyo LE25FW106\n\nAlso, add spi_disable_blockprotect_bp1_srwd().\n\nOriginally written and tested by The Raven \u003coriginalraven@hotmail.com\u003e.\n\nCorresponding to flashrom svn r1818.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f2756fa240ccf5b2fe888c4abc9c4cdf33932e3a", "tree": "c35a280fcd8ce8bb56337f783a12eea34203cc6d", "parents": [ "1181ee251a831be43881d5a6403c33c4229d2ade" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 01 02:21:02 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 01 02:21:02 2014 +0000" }, "message": "Combine block_erase*_en29lv640b and block_erase*_m29f400bt respectively\n\nThis patch combines two identical block and chip erase functions respectively:\n - Merge block_erase_m29f400bt and block_erase_en29lv640b into\n erase_block_shifted_jedec.\n - Merge block_erase_chip_m29f400bt and block_erase_chip_en29lv640b into\n erase_chip_block_shifted_jedec.\n\nLeave their implementations in en29lv640b.c for now.\n\nCorresponding to flashrom svn r1808.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "0ab1e5d5e3d37aa97eb4ae36caac06a800c86654", "tree": "c5b314cb8b40888ee7cd4a2ef7d8bd8f7953aaeb", "parents": [ "618d8972019e12e6c7eadd5a330774900e1c2f0f" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu May 29 11:51:24 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu May 29 11:51:24 2014 +0000" }, "message": "jedec.c: constify a bit more\n\nAlso, include chipdrivers.h to find conflicting types between exported\ndeclarations and actual implementations.\n\nCorresponding to flashrom svn r1805.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "12f3d51a8eec91f04fdd67652114d6d8529dc8b8", "tree": "886fdfa5be8927d516c8922f537a59dc461c78e7", "parents": [ "85f09f72f18f14eb3b06dcfbc448e16145b75fd2" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue May 27 21:27:27 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue May 27 21:27:27 2014 +0000" }, "message": "Rename some spi_prettyprint_status_register_* functions\n\nSpi_prettyprint_status_register_default_bpX -\u003e\nspi_prettyprint_status_register_bpX_srwd\n\nWhy was the default in there anyway? :)\n\nCorresponding to flashrom svn r1802.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "85f09f72f18f14eb3b06dcfbc448e16145b75fd2", "tree": "72094e403ba57a0e9746ce6b7230b635d1198f52", "parents": [ "df64a42d6d6232af9aac20c7d2aedb4d527eaeef" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue May 27 21:27:14 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue May 27 21:27:14 2014 +0000" }, "message": "Add support for ESMT F25L32PA\n\nCorresponding to flashrom svn r1801.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f20b7beff054eb316088d590094d9efbc68dbee1", "tree": "6324be451385c9f9cea27381f35f300fbaa7f454", "parents": [ "20da4aa82cc11f25a6a4a52fd2bed219e6e1d829" ], "author": { "name": "Mark Marshall", "email": "mark.marshall@omicron.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "message": "Add \u0027const\u0027 keyword to chip write and other function prototypes\n\nCorresponding to flashrom svn r1789.\n\nInspired by and mostly based on a patch\nSigned-off-by: Mark Marshall \u003cmark.marshall@omicron.at\u003e\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "4404f73bd9ba7b4014bcd7a38e533f67027aa854", "tree": "6e759d9d533e8d1bd7e736607c411232412b18f8", "parents": [ "4c6d3a4b732732eb20bfb0fc9d857abaa4c41c88" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 12 08:28:56 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 12 08:28:56 2013 +0000" }, "message": "Cleanup ST M50 driver\n\nThere are two locking strategies used by this umbrella family, one uniform\nand one that matches the sector layout of the chip. Refactor the functions\ninvolved and rename the overly complicated file to just stm50.c and the\nfunctions accordingly.\n\nThis fixes unlocking of some of the non-uniform chips and gets rid of the\nabuse of page_size.\n\nCorresponding to flashrom svn r1736.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "1dd5d3aa6605ed8c6928d10f4fd48f3f0abf04c2", "tree": "3181bbab82b26b34181d4357033e28b9e85edf6c", "parents": [ "fdc4f7ebb9c8986e8244bcbc2c52c320c2112d45" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 27 18:02:19 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 27 18:02:19 2013 +0000" }, "message": "Add support for AT45CS1282\n\nThis one is even more strange than the AT45DB chips. Like the AT45DB321C\nit does not support any power-of-2 page sizes. There is only one asymmetrical\neraser and that uses two opcodes.\n\nCorresponding to flashrom svn r1725.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "fdc4f7ebb9c8986e8244bcbc2c52c320c2112d45", "tree": "8e559a495d0ba970d816133e36ad33ecc7372d24", "parents": [ "db4e87dccf040f29dca18571bc455ee23fb430eb" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 27 18:02:12 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 27 18:02:12 2013 +0000" }, "message": "Add support for AT45DB321C\n\nIt seems like this model is one-of-a-kind... it shares some properties\nwith the older versions of the AT45DB series as well as with new ones.\n\nCorresponding to flashrom svn r1724.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "db4e87dccf040f29dca18571bc455ee23fb430eb", "tree": "d88ea1cd6abaa3cbad69fb447eb6dc0092fbb78e", "parents": [ "6db8bad530612262a42c492f06816eb85b8598fc" ], "author": { "name": "Aidan Thornton", "email": "makosoft@gmail.com", "time": "Tue Aug 27 18:01:53 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 27 18:01:53 2013 +0000" }, "message": "Add support for Atmel AT45DB* chips\n\nCorresponding to flashrom svn r1723.\n\nSigned-off-by: Aidan Thornton \u003cmakosoft@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "6f59b0bc5124f47294e261bb20924f9a8e505d89", "tree": "4fb4121d32185587067e5d50723ec879d56b8dbe", "parents": [ "c80c4a35a0d4eb51c142fc53ee4ae6d82f4dc37a" ], "author": { "name": "Nikolay Nikolaev", "email": "evrinoma@gmail.com", "time": "Fri Jun 28 21:29:51 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:29:51 2013 +0000" }, "message": "Add support for remaining Numonyx (Micron) N25Q chips\n\nAdd...\n - N25Q128..3E\n - N25Q128..1E\n - N25Q256..1E (defunct due to addressing)\n - N25Q256..3E (defunct due to addressing)\n - N25Q512..1E (defunct due to addressing)\n - N25Q512..3E (defunct due to addressing)\n - N25Q00A..3G (defunct due to addressing)\n\nAlso, refine existing family members.\n\nCorresponding to flashrom svn r1693.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "c80c4a35a0d4eb51c142fc53ee4ae6d82f4dc37a", "tree": "51a1339cfa3b916613a092a2a50106c671b7916f", "parents": [ "0ec2f7e7e00d27c9551e7fe7c8f5497d87475be2" ], "author": { "name": "Nikolay Nikolaev", "email": "evrinoma@gmail.com", "time": "Fri Jun 28 21:29:44 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:29:44 2013 +0000" }, "message": "Add support for Spansion S25FL...S chips\n\nAdd...\n - S25FL128S\n - S25FL256S uniform version (defunct due to addressing)\n - S25FL512S uniform version (defunct due to addressing)\n\nMerge Intel S33 status register functions with this one\u0027s.\n\nCorresponding to flashrom svn r1692.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "d0e3ea1470eb7e16082a853aca5010d20dc0879b", "tree": "f381998972806961af753464911f93de9fd3ee47", "parents": [ "01dac17ec586e0476eaea3410d68d516fd6d6a61" ], "author": { "name": "Nikolay Nikolaev", "email": "evrinoma@gmail.com", "time": "Fri Jun 28 21:29:08 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:29:08 2013 +0000" }, "message": "Add support for Eon EN25S series\n\nAdd...\n - EN25S10\n - EN25S20\n - EN25S40\n - EN25S80\n - EN25S16\n - EN25S32\n - EN25S64\n\nCorresponding to flashrom svn r1687.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "579f1e0b67a49282684a39f6c08bcf0813bd3c5c", "tree": "d14c6dfdb3bebba760dc9d83e14f0d5d5641abbe", "parents": [ "278ba6e96766f1d17202642a720f4e4eac007c74" ], "author": { "name": "Nikolay Nikolaev", "email": "evrinoma@gmail.com", "time": "Fri Jun 28 21:28:37 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:28:37 2013 +0000" }, "message": "Introduce spi_block_erase_db()\n\nUsed for page erase on some chips (e.g. Numonyx M45PE and\nSanyo LF25FW series).\n\nCorresponding to flashrom svn r1682.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "278ba6e96766f1d17202642a720f4e4eac007c74", "tree": "f0520da2262238adda4fb28a94fda700722c5bf4", "parents": [ "682122bce7714e285d196be09d4c97666458c487" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:28:27 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:28:27 2013 +0000" }, "message": "Introduce additional SPI status register helpers\n\n - spi_prettyprint_status_register_default_welwip():\n It just prettyprints the plain hex value and the welwip bits.\n - spi_prettyprint_status_register_default_bp4():\n Prints the hex value, welwip, bp0-5 and srwd bits.\n - spi_disable_blockprotect_bp2_srwd(),\n - spi_disable_blockprotect_bp3_srwd() and\n spi_disable_blockprotect_bp4_srwd():\n Three new common block unprotection functions for the frequent\n cases where there is a status register lock bit at bit #7 and some\n block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively.\n\nCorresponding to flashrom svn r1681.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "cecb2c56d07ac45cde56cadc6416e653b0cfafb7", "tree": "81788790601ca10fea904cef17f4694134ecbc3d", "parents": [ "0466c819e248881e03a6ec98db5297565816859b" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jun 20 22:55:41 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jun 20 22:55:41 2013 +0000" }, "message": "Fix unlocking function for most Atmel AT2[56]D* chips\n\nI broke unlocking them correctly in r1635 while refactoring (NB: the\ncommit log including the overly selfconfident statement about the\n\"bug in spi_disable_blockprotect_at25df()\").\n\nAffected chips have per sector protection bits and the write protection bits\nin the status register do indicate if none, some or all sectors are protected.\nIt is possible to globally (un)lock all sectors at once but in a way that was\nnot anticipated when refactoring the spi25 unlocking functions into\nspi_disable_blockprotect_generic(). To globally unprotect not only the\nprotection bits (2 and 3) have 0 to be written to them but also bits 4 and 5\nwhich normally would not be touched by spi_disable_blockprotect_generic().\nSome of the chips also support a permanent lockdown with fuses which we\ndo not handle yet.\n\nTo fix this without copying the whole method I introduce another mask\nparameter to spi_disable_blockprotect_generic() namely unprotect_mask.\nSee verbose comments inline for details.\n\nAlso, prettyprint the status register after trying to disable the block\nprotection fails.\n\nCorresponding to flashrom svn r1679.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Chi Zhang \u003czhangchi866@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "730e7e74ebf11560d1c852934b18e98d1200ce53", "tree": "f9bc3f738776ff40df3d128e7dbc145ac580cb0c", "parents": [ "f44516121aecbd307a9398fe9bc1ec9ce25bfb09" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed May 01 14:04:19 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed May 01 14:04:19 2013 +0000" }, "message": "Update spi_get_erasefn_from_opcode()\n\nWe forgot to add a few SPI erase functions to the helper function that is\nused for SFDP. Also, sort the declarations in the header.\n\nCorresponding to flashrom svn r1672.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "3f5e35db4b22d36918adc7ee28b0d77ee50af568", "tree": "22d04b8a8c66a4f8be377c54b759215f12faf1bf", "parents": [ "e33c40eb7db5dc16763cd7c245578a968306a757" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Apr 19 01:58:33 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Apr 19 01:58:33 2013 +0000" }, "message": "Refine PMC Pm25LV series\n\n - Add missing bits and resort chips\n - Refine Pm25LV512(A) and Pm25LV010\n Due to manufacturer ID continuation this one needs a new probing\n function: probe_spi_res3() which should be refactored in the future.\n The datasheet describes a very weird order of ID bytes:\n Vendor byte, model byte, vendor continuation byte. Let\u0027s pretend we did\n not read that or the datasheet is bogus (although the datasheet of the\n successor series describes the same but luckily additionally to RDID).\n - Add Pm25LV010A\n This was tested by Chi Zhang:\n http://paste.flashrom.org/view.php?id\u003d1573\n\nCorresponding to flashrom svn r1670.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "57794ac1580fc5efee3ba01a0c3e4539bb58d088", "tree": "4212a02023a6a8c6dd0b03d234e66471ddb5d634", "parents": [ "54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:04:20 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:04:20 2012 +0000" }, "message": "Add support for Atmel\u0027s AT25F series of SPI flash chips\n\nThis adds support for the following chips:\n - AT25F512, AT25F512A, AT25F512B\n - AT25F1024, AT25F1024A\n - AT25F2048\n - AT25F4096\n\nBesides the definitions of the the chips in flashchips.c this includes\n- a dedicated probing method (probe_spi_at25f)\n- pretty printing methods (spi_prettyprint_status_register_at25f*), and\n- unlocking methods (spi_disable_blockprotect_at25f*)\n\nCorresponding to flashrom svn r1637.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4", "tree": "b394950b3bd52b2490e1da77a1c497516d6bfd06", "parents": [ "9530a02212bd48aca32752250c4e2ec91e24d3b6" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:04:12 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:04:12 2012 +0000" }, "message": "Add support for Intel S33 series flash chips\n\nThis includes:\nBottom boot block:\n* 16Mb/2MB:\n QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8\n* 32Mb/4MB:\n QB25F320S33B8, QH25F320S33B8\n* 64Mb/8MB:\n QB25F640S33B8, QH25F640S33B8\n\nTop boot block:\n* 16Mb/2MB:\n QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8\n* 32Mb/4MB:\n QB25F320S33T8, QH25F320S33T8\n* 64Mb/8MB:\n QB25F640S33T8, QH25F640S33T8\n\nAt least some seem to be marketed by other vendors (too?) but also with\nIntel\u0027s vendor ID.\n\nBesides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they\nsupport also erasing the top/bottom 8 8kB blocks with opcode 0x40.\nBut since this command fails for all addresses outside those ranges,\nit is not easily implemented with flashrom\u0027s current code base and\nhence left out.\n\nCorresponding to flashrom svn r1636.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "6ee37e28365f2a8ea498d03b08def0dcb1cc6494", "tree": "3328db4647bba505d32ebc5755c511728cec438e", "parents": [ "2c421199ab37e691a83ad09b542ed43ee5811603" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:03:51 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:03:51 2012 +0000" }, "message": "Improve SPI status register pretty printing\n\n - Move all functions related to SPI status registers to a new file\n spi25_statusreg.c. This includes the generic as well as the\n SST-specific functions from spi25.c and the chip-specific functions\n from a25.c and at25.c.\n - introduce helper functions\n * spi_prettyprint_status_register_hex()\n * spi_prettyprint_status_register_bpl()\n * spi_prettyprint_status_register_plain()\n Use the latter on every compatible flash chip that has no better printlock\n function set and get rid of the implicit pretty printing in the SPI probing\n functions.\n - remove\n * spi_prettyprint_status_register_common()\n * spi_prettyprint_status_register_amic_a25lq032() because it can be fully\n substituted with spi_prettyprint_status_register_amic_a25l032().\n * spi_prettyprint_status_register() (old switch, no longer needed)\n - promote and export\n * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1().\n * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2().\n * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3().\n - add #define TEST_BAD_REW and use it for a number of Atmel chips which\n had only TEST_BAD_READ set even though they dont have erasers or a write\n function set.\n\nCorresponding to flashrom svn r1634.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "c31243e1739a4ba21d45e3569341aa671939cb8d", "tree": "eb08f0981a4a4309725c4cb480c7a53e07d7504a", "parents": [ "78ffbeaa029fb827dcdf9c02262adbda4673e5eb" ], "author": { "name": "Kyösti Mälkki", "email": "kyosti.malkki@gmail.com", "time": "Sun Oct 28 01:50:08 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Oct 28 01:50:08 2012 +0000" }, "message": "Add support for Winbond W39F010/W39L010/W39L020\n\nW39F010 is a 128kB parallel 5V flash chip, 16k bootblocks.\nW39L010 is a 128kB parallel 3.3V flash chip, 8k bootblocks.\nW39L020 is a 256kB parallel 3.3V flash chip, 64k/16k bootblocks.\n\nThe W39F010 code was tested with a satasii programmer. The first write\nattempt after an erase returned with verify failure, but the second\nwrite attempt was succesful:\nhttp://paste.flashrom.org/view.php?id\u003d1418\n\nCorresponding to flashrom svn r1620.\n\nSigned-off-by: Kyösti Mälkki \u003ckyosti.malkki@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "94b39b47e475d3d8f153acea4a3fdcd6bbc81ea7", "tree": "42a78390b7e92346efe9c97c93e458eb91a75d86", "parents": [ "d956f822490e10be505355a59fc2498800d33c1d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Oct 27 00:06:02 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Oct 27 00:06:02 2012 +0000" }, "message": "Add support for Atmel AT26DF041\n\nWicked chip: No WRSR, no write enable command (but swallows our\ndefault one without a problem), supports an auto-erasing page write\n(but even without that page writes are recommended to write the\nwhole page i.e. operate on a completely erased page), mad\nrequirements on block refreshments if only partly written.\n\nFound on my Intel D946GZIS and tested with my serprog in situ.\nUsing the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using\nthe spi_chip_write_256 command greatly improves performance and works\nflawlessly.\n\nCorresponding to flashrom svn r1616.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5609f9d408645657ef0dd2ca986ada5aaad4c875", "tree": "61f34750e39b1c9ec0be45555a8ca5b4125bc75b", "parents": [ "eb58257b9650b9191d8b987e0b214fed1ad2b77a" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 22 01:38:06 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 22 01:38:06 2012 +0000" }, "message": "Generify a25.c\u0027s SRWD printing function and move it to spi25.c\n\nCorresponding to flashrom svn r1602.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "eb58257b9650b9191d8b987e0b214fed1ad2b77a", "tree": "8e37e169514dfba6083cc6f8c18943e69b81e9a4", "parents": [ "3c0fcd0f30f2b3c0df57b66e645859d923e68d16" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:52:50 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:52:50 2012 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 14\n\nTested Mainboards:\nOK:\n - ASUS M3A78-EH\n http://www.flashrom.org/pipermail/flashrom/2010-October/005297.html\n - ASUS P2B-LS\n http://www.flashrom.org/pipermail/flashrom/2010-November/005506.html\n - Biostar TA790GX A3+\n http://paste.flashrom.org/view.php?id\u003d1350\n - ECS 848P-A7\n http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html\n - GIGABYTE GA-G41MT-S2PT\n Reported on IRC\n - GIGABYTE GA-H77-D3H\n Reported and tested by Alexander Gordeev on IRC.\n - Gigabyte GA-X79-UD5\n http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html\n - Shuttle FN78S\n http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html\n - VIA EITX-3000\n Reported on IRC by Tuju\n\nNOT OK:\n - Dell PowerEdge C6220 (0HYFFG)\n http://www.flashrom.org/pipermail/flashrom/2012-September/009900.html\n - Foxconn Q45M\n http://www.flashrom.org/pipermail/flashrom/2012-September/009923.html\n - MSI MS-7309 (K9N6SGM-V)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009712.html\n - Supermicro X9QRi-F+\n http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html\n - ZOTAC H61-ITX WiFi (H61ITX-A-E)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009649.html\n\nASUS CUSL2-C has been tested to be working with the board enable once\nimplemented for the TUSL2-C board. They seem to have the same PCI IDs\nas shown in the links below. Since only the CUSL2-C board enable has been\ntested yet, we distinguish the two by DMI strings.\nhttp://paste.flashrom.org/view.php?id\u003d1393\nhttp://www.flashrom.org/pipermail/flashrom/attachments/20091206/ddca2c6c/attachment-0002.eml\n\nTested flash chips:\n - Set EMST F25L008A to PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html\n - Set GigaDevice GD25Q64 to PREW (+PREW)\n http://git.chromium.org/gitweb/?p\u003dchromiumos/third_party/flashrom.git;a\u003dcommit;h\u003d9e8ef49b1f626c2197e131fba6c5b65c8af4eeea\n - Set Macronix MX25L12805 to P (+P)\n http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html\n - Set SST SST49LF003A/B to PREW (+EW)\n http://paste.flashrom.org/view.php?id\u003d467\n - Set Winbond W49V002FA to PREW (+EW)\n http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html\n\nTested chipsets:\n - Intel X79 (0x1d41)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html\n\nBoard enables:\n - add ASUS P4P800-X\n Created by Idwer Vollering and tested by Mingsen Bao:\n http://paste.flashrom.org/view.php?id\u003d467\n - add DMI string to P4P800-VM\n\nMiscellaneous:\n - Add remaining Intel 7 series chipset (LPC) PCI IDs\n - Add generic SPI detection for chips from Winbond\n - Minor manpage changes\n - Minor other cleanups\n - Escape full stops after abbreviations in the manpage.\n - Add ICH9 and successors to spi_get_valid_read_addr\n\nCorresponding to flashrom svn r1601.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "3c0fcd0f30f2b3c0df57b66e645859d923e68d16", "tree": "55a94a70e9662a8558667c171b33bdfe99be483e", "parents": [ "14fbc4b40045c6fcb345da52ab048d961fc15c6c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:46:56 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:46:56 2012 +0000" }, "message": "Add spi_block_erase_62\n\nThis is used by the AT25F series (only?), but is generic enough to\nreside in spi25.c. The only currently supported chip is the AT25F512B.\nOther members of that series need some additional infrastructure code,\nhence this patch adds the erase function to the AT25F512B only.\n\nCorresponding to flashrom svn r1600.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "7bf4ed9277bb724e9a9aac762dc69f3e3c48f748", "tree": "7e62857578038b7f38bdced15abd7b869640ccc0", "parents": [ "62218c39de75bb19adaad16b843757adbe272aad" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Aug 26 21:04:27 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Aug 26 21:04:27 2012 +0000" }, "message": "Rename AT25F512B-specific code\n\nThe AT25F512B is quite different from the other (older and yet\nunsupported) chips in the AT25F* familiy, hence rename 512B-specific\nstuff to make room for the generic AT25F* code.\n\nCorresponding to flashrom svn r1583.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "1ba08f6d417921d9cb37b8b8823f4cb9d68f5895", "tree": "1dba91fd092949624eaaa4e73dd43719c06dc3f0", "parents": [ "cb30158fbf1a63d65de53080d0cdbcb23efd95d6" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 02 23:51:28 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 02 23:51:28 2012 +0000" }, "message": "Clean up a25.c, at25.c, spi25.c\n\n- introduce spi_prettyprint_status_register_atmel_at25_wpen()\n- use spi_prettyprint_status_register_bit() where possible\n- generify spi_prettyprint_status_register_bp3210 and use it in at25.c too\n\nCorresponding to flashrom svn r1560.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f5a30f65ad6d50706d3d92010c9d7e5b3c0782d0", "tree": "815a620645ca472bccc630476073106250f8ff2e", "parents": [ "47eff6b5b4e924627583f45f9b321119899a589c" ], "author": { "name": "David Borg", "email": "borg.db@gmail.com", "time": "Sun Apr 15 13:16:32 2012 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Sun Apr 15 13:16:32 2012 +0000" }, "message": "Add support for for the Atmel AT49F040 chip\n\nChip features an optional permanent boot block write protection.\n\nCorresponding to flashrom svn r1522.\n\nSigned-off-by: David Borg \u003cborg.db@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "47eff6b5b4e924627583f45f9b321119899a589c", "tree": "758809500d91966064fb5ba3cd4c598e9525db8e", "parents": [ "1525b2ad16e07f035b1de70fadd05a7018ea5756" ], "author": { "name": "Rudolf Marek", "email": "r.marek@assembler.cz", "time": "Sat Apr 14 22:51:40 2012 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Sat Apr 14 22:51:40 2012 +0000" }, "message": "Add support for the Eon EN29LV640B chip\n\nThis chip needs special command sequences in 8 bit mode. Also, 8 bit\nprogramming needs actually 16bit double byte program.\n\nThe chip is found on the Bifferos Bifferboard, for example.\n\nCorresponding to flashrom svn r1521.\n\nSigned-off-by: Rudolf Marek \u003cr.marek@assembler.cz\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "ac1b4c8bd707c07e9636bedbd823ed5cb46f89ad", "tree": "5553eec8f0f86f363220a979342d59e3c55eae58", "parents": [ "ac427b22c4fa45936fe94af31a5e0422dd95c152" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Feb 17 14:51:04 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Feb 17 14:51:04 2012 +0000" }, "message": "Add support for SFDP (JESD216)\n\nSimilar to modules using the opaque programmer framework (e.g. ICH Hardware\nSequencing) this uses a template struct flashchip element in flashchips.c with\na special probe function that fills the obtained values into that struct.\n\nThis allows yet unknown SPI chips to be supported (read, erase, write) almost\nas if it was already added to flashchips.c.\n\nDocumentation used:\nhttp://www.jedec.org/standards-documents/docs/jesd216 (2011-04)\nW25Q32BV data sheet Revision F (2011-04-01)\nEN25QH16 data sheet Revision F (2011-06-01)\nMX25L6436E data sheet Revision 1.8 (2011-12-26)\n\nTested-by: David Hendricks \u003cdhendrix@google.com\u003e\non W25Q64CV + dediprog\nTested-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\non a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog\n\nThanks also to Michael Karcher for his comments and preliminary review!\n\nCorresponding to flashrom svn r1500.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "8a3c60cdd0e5632173567923ae1927763e31e857", "tree": "3a5514d022392cf4d8fa368f9f02653da21a93ca", "parents": [ "63fd9026f1e82b67a65072fda862ba7af35839e1" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "message": "Add struct flashctx * parameter to all functions accessing flash chips\n\nAll programmer access function prototypes except init have been made\nstatic and moved to the respective file.\n\nA few internal functions in flash chip drivers had chipaddr parameters\nwhich are no longer needed.\n\nThe lines touched by flashctx changes have been adjusted to 80 columns\nexcept in header files.\n\nCorresponding to flashrom svn r1474.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "63fd9026f1e82b67a65072fda862ba7af35839e1", "tree": "7d9ffba077715cf9e75c9f4a36d0d7f11a3181f6", "parents": [ "83c92e983aaf11fb6f5bafb6744275c50add193c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Dec 14 22:25:15 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Dec 14 22:25:15 2011 +0000" }, "message": "Use struct flashctx instead of struct flashchip for flash chip access\n\nStruct flashchip is used only for the flashchips array and for\noperations which do not access hardware, e.g. printing a list of\nsupported flash chips.\n\nstruct flashctx (flash context) contains all data available in\nstruct flashchip, but it also contains runtime information like\nmapping addresses. struct flashctx is expected to grow additional\nmembers over time, a prime candidate being programmer info.\nstruct flashctx contains all of struct flashchip with identical\nmember layout, but struct flashctx has additional members at the end.\n\nThe separation between struct flashchip/flashctx shrinks the memory\nrequirement of the big flashchips array and allows future extension\nof flashctx without having to worry about bloat.\n\nCorresponding to flashrom svn r1473.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "c69c9c84e0341b701d9966fea8ce54d4e017bbb7", "tree": "2ea0b12abf9dd3483246423752239b88c6d7942e", "parents": [ "8ca4255d7968dbf6301367074cc7267d22a25658" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Nov 23 09:13:48 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Nov 23 09:13:48 2011 +0000" }, "message": "Unsignify lengths and addresses in chip functions and structs\n\nPush those changes forward where needed to prevent new sign\nconversion warnings where possible.\n\nCorresponding to flashrom svn r1470.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "532c717bccc95aa93bae7af8be0695bee83c32b5", "tree": "406d46e209a8a56f176c7afa20f14754800e77d9", "parents": [ "b992d3433974479909e6fd584dd798d4badf27b9" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Nov 04 21:35:26 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Nov 04 21:35:26 2011 +0000" }, "message": "Add opaque programmer registration infrastructure\n\nAn opaque programmer does not allow direct flash access and only offers\nabstract probe/read/erase/write methods.\nDue to that, opaque programmers need their own infrastructure and\nregistration framework.\n\nCorresponding to flashrom svn r1459.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "8c35745fcf3ed6eb2769beda0c8b941df07f6175", "tree": "2f3c43a3589edc55e7143b39d40df4a0cd039183", "parents": [ "e3185c0599d77c06b9665c9721649b96108c894f" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 22:42:18 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 22:42:18 2011 +0000" }, "message": "Revert \"Unsignify lengths and addresses in chip functions and structs\"\n\n- probe_timing was changed to unsigned although we use negative values\n for special cases\n- some code was not changed along hence did no longer compile:\n * dediprog\u0027s read and write functions\n * linux_spi\u0027s read and write functions\n- it introduced a number of new sign conversion warnings\n (http://paste.flashrom.org/view.php?id\u003d832)\n\nTo be safe this patch reverts all changes made in r1448, a corrected\npatch will follow later.\n\nThanks to idwer for pointing out the problem first!\n\nCorresponding to flashrom svn r1450.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "d196e7c1387b30ac35e7b0f605c79823ac9b5ec9", "tree": "e0f40df44cb94c62f150a84080bf7171f8623aa8", "parents": [ "75da80c17bbb992ce2b60ae15ef2fba7d23bfd8e" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 00:41:33 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 00:41:33 2011 +0000" }, "message": "Unsignify lengths and addresses in chip functions and structs\n\nCorresponding to flashrom svn r1448.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "fca3b012dae98c852e2dd492b191e2cecf728583", "tree": "8a7a9ab9f282b555bec39a58e833f3cb384cc8b7", "parents": [ "14ab8d456a994ec3d84aaa43cc5e20a580aac0c0" ], "author": { "name": "Mattias Mattsson", "email": "vitplister@gmail.com", "time": "Thu Aug 25 22:44:11 2011 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Thu Aug 25 22:44:11 2011 +0000" }, "message": "Add support for the Sharp LH28F008BJT-BTLZ1 chip\n\nTested by Mattias Mattsson \u003cvitplister@gmail.com\u003e on a PowerPC box.\n\nCorresponding to flashrom svn r1420.\n\nSigned-off-by: Mattias Mattsson \u003cvitplister@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "a63c7c449646147efe2bdeb80efeed479dc1d328", "tree": "da1a452c658ecb3120fffe6d084a46a85d5792a4", "parents": [ "082c8b559cd9f3262c9af58ac2f17f2cc8a09d8b" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 16 12:08:22 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 16 12:08:22 2011 +0000" }, "message": "Remove unneeded inclusions of chipdrivers.h\n\nThis is related to the spi split patch as discussed in:\nhttp://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364\nthe old commit (r914) log notes:\n\"Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c\n ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c\"\n\nthere still remain a few cases where chipdrivers.h is needed:\ndediprog.c (spi_read_chunked and spi_write_chunked)\nit87spi.c (due to spi_write_enable and spi_read_status_register)\nwbsio_spi.c (spi_programmer registration only)\n\nbesides that, there are also non-spi files that do not need it.\nalso, add flash.h to chipdrivers.h because it uses some types of it\nand remove flashchips.h from print.c\n\nCorresponding to flashrom svn r1414.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "7a3bd8f28f3b8dd854e453703efb702f07294ae5", "tree": "b2a63e7607e23f2f2913f7ec5b3d5b692d87c2c0", "parents": [ "c965c2de64b695ef18865ac8220abd57b56c364c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu May 19 00:06:06 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu May 19 00:06:06 2011 +0000" }, "message": "Refine status register and lock printing of Atmel and AMIC SPI chips\n\nAdd lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU,\nA25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU,\nA25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032\nto a25.c.\n\nAdd lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A,\nAT26DF321.\n\nMove Atmel AT25*/AT26* lock related functions originally added in r1115\nfrom spi25.c to at25.c.\n\nFor SPI chips the lock printing was handled by one common function, but\nsharing a common function which only is a big switch() statement doesn\u0027t\nmake sense, especially if we can define lock printing functions per\nflash chip anyway.\n\nThe printlock function pointer in struct flashchip is used to print\nstatus register and locking information, and serves as replacement for\nimplicit status register and lock printing during probe. That code will\nlater be changed to store locking info in a machine- accessible data\nstructure so flashrom can handle locked regions correctly.\n\nCorresponding to flashrom svn r1316.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "4b177369854b0f1b0f5769b809f2cf1b0ea4f347", "tree": "13f79018dc1bfb1da97f9b4fbd460e3e9448eaa3", "parents": [ "2842db315de428fca28db6bfae0585fe602e41c0" ], "author": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Thu Apr 14 23:43:19 2011 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Thu Apr 14 23:43:19 2011 +0000" }, "message": "Remove erase_chip_stm50flw0x0x\n\nAs the comment indicates, that function is not a chip erase function\nat all, but a function calling a block eraser in a loop. So it adds\nno extra value to what we already have in the block_eraser\ninfrastructure.\n\nFurthermore, that function assumes a uniform sector size layout, but\nis referenced from flash chip with non-uniform sector size layout, which\nis just wrong.\n\nCorresponding to flashrom svn r1287.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "19e0aacd636eac3fde02a8f5e2b87326656d5812", "tree": "de4ff2cc283b98d482fa09e1043dd7e3a306d3cb", "parents": [ "8262e82d1c215cc92b85a2c2abb16b4cbbba04bb" ], "author": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Sun Mar 06 17:58:05 2011 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Sun Mar 06 17:58:05 2011 +0000" }, "message": "Add W39L040\n\nCorresponding to flashrom svn r1268.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "ecc67072b63430877e160da628f69a2ef2f34735", "tree": "69685a03cdb842eecd5c89b12cbfc425f70b4627", "parents": [ "22e0532caf883b84743c80c4dce24f2ef1fcecae" ], "author": { "name": "Idwer Vollering", "email": "vidwer@gmail.com", "time": "Sun Dec 26 23:55:12 2010 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Sun Dec 26 23:55:12 2010 +0000" }, "message": "Enable unlocking (erasing/writing) W39V040FB chips\n\nAdd code for the unlocking (erasing/writing) of Winbond W39V040FB\nchips, enabling erasing/writing this type of chip.\n\nCorresponding to flashrom svn r1248.\n\nSigned-off-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "9188240a14d77a1ceb5ab07e61a8d3c602e7995d", "tree": "39b925cc2b32ac0ca975cbfe24d9cdf8a3c175c8", "parents": [ "dce73ae62212c7e22d28ee0d9e48aaccd1cab46a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 05 16:33:59 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 05 16:33:59 2010 +0000" }, "message": "Add support for Winbond W39V040FB and W39V040FC\n\nPrint lock status for all supported Winbond W39* chips:\nW39V040A, W39V040B, W39V040C, W39V040FA, W39V040FB, W39V040FC,\nW39V080A, W39V080FA, W39V080FA (dual mode).\n\nFill in correct probe timing for Winbond W39V040C and W39V080FA.\n\nPlease note that the W39V040B/W39V040FB pair has identical IDs,\nidentical read/write/erase, but locking differs. Same applies to\nW39V040C/W39V040FC. This causes double detection on chipsets which\nsupport LPC and FWH, making flashing more difficult because the user\nhas to select the correct chip. This is called the evil twin problem.\nA better evil twin handling (patch available) will resolve that problem.\n\nCorresponding to flashrom svn r1245.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "75a58f94cc641e8051169ec6bb9894a390a8e2bf", "tree": "eb3c0573cecfe70ded0b96003dc6f4d5e55975d4", "parents": [ "79e6757d269b91ee759bd569df7093225f4f3715" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 13 22:26:56 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 13 22:26:56 2010 +0000" }, "message": "Switch all flash chips to partial write\n\nThe inner write functions which handle partial write are renamed to the\noriginal name of their wrappers. The write wrappers are removed.\n\nCorresponding to flashrom svn r1211.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Maciej Pijanka \u003cmaciej.pijanka@gmail.com\u003e\nTested-by: Andrew Morgan \u003cziltro@ziltro.com\u003e\nTested-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nAcked-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nTested-by: Sean Nelson \u003caudiohacked@gmail.com\u003e \nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e \n" }, { "commit": "79e6757d269b91ee759bd569df7093225f4f3715", "tree": "d77c280e33ab45e549d2b7493eab7bf50da57d53", "parents": [ "184b95f449e4c314964b63c3170da216267d3b5e" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 13 21:49:30 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 13 21:49:30 2010 +0000" }, "message": "Refactor remaining write wrappers\n\nKill duplicated code.\n\nAnnotate write functions with their chunk size.\n\nMark Fujitsu MBM29F400BC and ST M29F400BB as untested because their\nwrite code no longer uses a broken layout.\n\nCorresponding to flashrom svn r1210.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\nTested-by: Maciej Pijanka \u003cmaciej.pijanka@gmail.com\u003e\nTested-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nAcked-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nTested-by: Sean Nelson \u003caudiohacked@gmail.com\u003e \nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e \n" }, { "commit": "b30a5ed4afead1592224009230ea23500f91b230", "tree": "0185573277197cab68874cedd1e00246ea2cf573", "parents": [ "b28349f8bc40dd55524113e258b3185711e80366" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Oct 10 14:02:27 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Oct 10 14:02:27 2010 +0000" }, "message": "Unify chip write functions\n\nThe currently used write functions (wrappers) all use helpers which\nperform the actual write (inner functions).\n\nThe signature of the write wrappers is: int write_chip(struct flashchip\n*flash, uint8_t * buf);\n\nThe signature of the inner write functions varied a lot. This patch\nchanges them to: int write_part(struct flashchip *flash, uint8_t *src,\nint start, int len);\n\nDid you know that flashrom has only 8 inner write functions for all\nflash chips? write_page_write_jedec_common write_sector_jedec_common\nwrite_sector_28sf040 spi_chip_write_256_new spi_chip_write_1_new\nspi_aai_write_new write_page_82802ab write_page_m29f400bt\n\nExport all inner write functions.\n\nChange the function signature of wait_82802ab to eliminate single-use\nvariables.\n\nRemove an error message in write_page_m29f400bt which was printed for\nevery byte written regardless of success.\n\nAdd sharplhf00l04.c to the list of flash chip drivers in the Makefile.\nWhile the functions in there are unused, I suspect we will need them\nlater, and by hooking the file up we ensure that compilation won\u0027t\nbreak.\n\nCorresponding to flashrom svn r1208.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "f52f784bb300ec0acbd6c6bd9e6c3e5b435c4a90", "tree": "957964a468245432abbd23cd06839898b64105ce", "parents": [ "92c8b0cec2ed06db9c24c4d93cf38a596edf23ab" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Oct 08 18:52:29 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Oct 08 18:52:29 2010 +0000" }, "message": "Move implicit erase out of chip drivers\n\nFlashrom had an implicit erase-on-write for most flash chip and\nprogrammer drivers, but it was not entirely consistent.\n\nSome drivers had their own hand-rolled partial update functionality\nwhich made handling partial updates from generic code impossible.\n\nMove implicit erase out of chip drivers, and kill some dead erase\nfunctions at the same time. A full chip erase is now performed in the\ngeneric code for all flash chips on write, and after that the whole chip\nis written.\n\nCorresponding to flashrom svn r1206.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "1db7a448b37f1f699bd9a64d2187f3883e0f4503", "tree": "90d10ef4b79f1e9fdeb2ad9cdb165f0d04f429c7", "parents": [ "738e252112271f63c8ad4c9a135cfe17ff98e87d" ], "author": { "name": "Helge Wagner", "email": "helge.wagner@ge.com", "time": "Tue Oct 05 22:29:08 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Oct 05 22:29:08 2010 +0000" }, "message": "Massive speedups for SST25VF032B and SST25VF064C\n\nUse AAI write for SST SST25VF032B.\nSpeedup from 228 to 113 seconds.\n\nUse page (256 byte) write for SST SST25VF064C.\nSpeedup from 3091 to 123 seconds.\n\nCorresponding to flashrom svn r1194.\n\nSigned-off-by: Helge Wagner \u003chelge.wagner@ge.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "fd7075ae75c04df49f61a7617e772c54e0b4984d", "tree": "c95adc0c593268590615032f0d297e7190bcf2a7", "parents": [ "f792c7d4cb43e8c34719e015f20e8049579e34af" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 29 13:09:18 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 29 13:09:18 2010 +0000" }, "message": "Add detailed status register printing and unlocking for all ATMEL AT25* chips\n\nAdd support for Atmel AT25DF081A and AT25DQ161.\n\nSome chips require EWSR before WRSR, others require WREN before WRSR,\nand some support both variants. Add feature_bits to select the correct\nSPI command, and default to EWSR.\n\nCorresponding to flashrom svn r1115.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Steven Rosario\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "420cf6f633f7697a8a709326c47b3cf0e6ea229d", "tree": "5bab2b53c558ffa2400ba9708659c2b9e049168a", "parents": [ "29a1c66a23bc8685f456d548361b735bf36dcf2b" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jul 16 22:07:20 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jul 16 22:07:20 2010 +0000" }, "message": "Mark Fujitsu MBM29F400BC write as broken (implicit eraseblock layout in write)\n\nUse full-chip write function on Fujitsu MBM29F400TC and ST M29F400BT.\nAdd support for ST M29F400BB.\n\nCorresponding to flashrom svn r1083.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "29a1c66a23bc8685f456d548361b735bf36dcf2b", "tree": "963d487fa71ce4b6ad998d89fde9e167ce11e6bb", "parents": [ "ca812d40d461e70a70df6079978e96642775e7b2" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 20:21:22 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 20:21:22 2010 +0000" }, "message": "Use generic unlocking infrastructure for SPI chips\n\nActually check if the unlock worked instead of just assuming it worked.\n\nCorresponding to flashrom svn r1082.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "9a795d83fbb8842a271d5e037dc983a57b0419fd", "tree": "a9049f708d0ab7d42d122fecd23855aaa819c5bc", "parents": [ "1748c5701f77ab7164ab3311f37abc356d825ccb" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 16:19:05 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 16:19:05 2010 +0000" }, "message": "Convert SPI chips to partial write\n\nHowever, wrap the write functions in a compat layer to allow converting\nthe rest of flashrom later. Tested on Intel NM10 by David Hendricks.\n\nCorresponding to flashrom svn r1080.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "3a25fea9e7726109df0c09aaacefb446ab1a9d0d", "tree": "7e0d39872f7c96eec1cc3be521eb99b33ac91fd2", "parents": [ "1b0ba893529cf93ae54b91607d93d3ad49c259e5" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 11:02:33 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 11:02:33 2010 +0000" }, "message": "The SPI opcode 0xd8 is not a chip erase opcode on any chip out there\n\nBesides that, the function as implemented just walks the chip and\nignores sector sizes.\nSector erase with SPI opcode 0xd8 is of course still supported.\nKill a declaration for a nonexisting function while we\u0027re at it.\n\nCorresponding to flashrom svn r1054.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n" }, { "commit": "dc1cda15d48cdbc7d53e4cf86cf39844e4af2a8b", "tree": "f7d7123a8b474227d45bd9f0eae5b819d499b3a8", "parents": [ "80f3d05e7356ec85f9ea27ae2e11245e0b6bb3c6" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri May 28 17:07:57 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri May 28 17:07:57 2010 +0000" }, "message": "Add support for two-byte RES probes\n\nSome chips implement the RES (0xab) opcode, but they use a non-standard\ntwo byte response instead of the usual one byte response. A two-byte\nresponse has the accuracy of REMS and RDID, so don\u0027t check for REMS/RDID\navailability before running a two-byte RES.\n\nCorresponding to flashrom svn r1017.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n" } ], "next": "5824fbff010076cc0d2a4387c1b2f54644ae5785" }