)]}' { "log": [ { "commit": "dfea68c563c4f23318e26897846fd2d79e27eefd", "tree": "e65d58355fbade12bc53832ed6893bc545256c76", "parents": [ "11136c210e382258a72df44ffe625260a6394a45" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 16:39:31 2026 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:28:06 2026 +0000" }, "message": "ichspi: Add Intel Wildcat Lake support\n\nLooks the same as Panther Lake except no 80 MHz options in the\nSPI guide nor the MFIT tool.\n\nChange-Id: I9d922687e5995ed34c9e8aee298554e976adfe0a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/403\n" }, { "commit": "f4d5f3294fd470830f2ec81d4bc803dccaeb9ae3", "tree": "a5408f9f92da87e86756af0b8951132dac22667b", "parents": [ "9c6b35f03ca30c60ee6d9d90b0a0309945e2714b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 08 18:42:55 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 10 15:56:47 2026 +0000" }, "message": "ichspi: Add Intel Panther Lake support\n\nPTL looks much like Lunar Lake. The only noticed differences so far are\na reserved frequency value that means 80MHz now, and that only 1.8V are\nsupported.\n\nTested `ich_descriptors_tool\u0027 output for the BIOS of an MSI Prestige 14\nFlip AI+ (D3MTG).\n\nDocuments used:\n * Intel® Core™ Ultra Processors (Series 3) Datasheet, Volume 1 of 2\n * Panther Lake H External Design Specification (EDS) Volume 2 of 2\n * Panther Lake-H Client Platform\n SPI Programming Guide\n\nChange-Id: Ifec90975cefc26bb7109d69fcdabcfe480516732\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/397\n" }, { "commit": "9c6b35f03ca30c60ee6d9d90b0a0309945e2714b", "tree": "7defede1317b0d76d0f9ff9c1a753fd5afd4ac44", "parents": [ "83d04387cfd38b2e286a7686c9373435665cea51" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 08 18:19:00 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 10 15:56:47 2026 +0000" }, "message": "ich_descriptors: Pretty print voltage on supported platforms\n\nSeems more and more important to have such clues about 1.8V parts.\n\nChange-Id: Ida9a447d840d63a9fed7c48b3a18546e67284a44\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/396\n" }, { "commit": "612519b2c54a008744891540407f2c8ff251083d", "tree": "f264bf5339ab332436dfd9acaa86d76b7492c1cf", "parents": [ "d5a61efe4e73675570eba7d537b4ec7e476946cb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 23:37:11 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Arrow Lake support\n\nARL looks much like a desktop version of Meteor Lake. Hardware registers\nseem to be the same, and the descriptor mostly differs in strap settings\n(as far as we are concerned).\n\nOdd enough, the old (pre 500 series) format for processor straps is used\nagain. For the descriptor detection, we shuffle the old default for Ibex\nPeak around, and make Arrow Lake the default for everything with over 80\nPCH traps.\n\nTested `ich_descriptors_tool\u0027 output for a GIGABYTE Z890M GAMING X BIOS.\n\nDocuments used:\n * Intel® Core™ Ultra 200S Series Processors Datasheet, Volumes 1 and 2\n * Arrow Lake-S and Arrow Lake-HX Client Platform\n SPI Programming Guide\n\nChange-Id: Ibaaeb896273eed3806561ba8c01d89770d27ff18\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/270\n" }, { "commit": "d5a61efe4e73675570eba7d537b4ec7e476946cb", "tree": "615c8bc476cf847c2d0bea4f7f1f154eede67e5a", "parents": [ "5e0d9b04a07f5646038020e1a45dd04c0b14e8f3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 23:55:44 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Lunar Lake support\n\nHardware looks much the same as Meteor Lake. The descriptor, however,\nknows 7 masters and regions are named a bit differently. Hence, add a\nnew enum entry for Lunar Lake.\n\nTested `ich_descriptors_tool\u0027 output for an MSI Prestige 13 A2VMG BIOS.\n\nDocuments used:\n * Intel® Core™ Ultra 200V Series Processors Datasheet, Volumes 1 and 2\n * Lunar Lake Client Platform\n SPI Programming Guide\n\nChange-Id: Ia377872cba56a3db6d853b7ce1bd495e5a03a868\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/271\n" }, { "commit": "5e0d9b04a07f5646038020e1a45dd04c0b14e8f3", "tree": "70386babe868ba7282cbbb0d8bc53880286025e8", "parents": [ "0ef2eb8f041ad6918dd41f4837d39be8811889c9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 21:44:52 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Meteor Lake SoC\n\nHardware looks the same as C740 series / Emmitsburg. The descriptor\nis somewhere between the latter and latest desktop platforms.\n\nOutput of `ich_descriptors_tool\u0027 with an image from Google/Rex looks\nreasonable.\n\nTested probing and reading on a Lenovo L16 ThinkPad.\n\nDocuments used:\n * Intel® Core™ Ultra Processor Datasheet, Volumes 1 and 2\n * Meteor Lake/Arrow Lake-U / H Client Platform\n SPI Programming Guide\n\nChange-Id: I7f1d162622a141fadcad715b064f92b1ccf7c72a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/189\n" }, { "commit": "0ef2eb8f041ad6918dd41f4837d39be8811889c9", "tree": "978d212a6cc5031e589162c49a36e4353e91c937", "parents": [ "42daab10a7704bfbe4a0af1a07748b8858649301" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 21:38:17 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Snow Ridge SoC\n\nHardware looks the same as C740 series / Emmitsburg. The descriptor,\nhowever, has very different frequency settings and different regions\nand masters.\n\nThe output of `ich_descriptors_tool\u0027 tested with an image from Intel\nlooks reasonable.\n\nChange-Id: I9f9dc4414af63cbe48d22ef2955df28e297d7e4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/188\n" }, { "commit": "42daab10a7704bfbe4a0af1a07748b8858649301", "tree": "9a9aa5465db9f58aa9d0c55f9807a2f694a98e05", "parents": [ "af26008fbabdd780bc6966acca4ad2481520b304" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 16 00:27:27 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Properly add Emmitsburg PCH\n\nThe Emmitsburg or C740 series PCH is actually ahead of all the other,\ncurrently supported chipsets. Finally, Intel added new registers that\ncarry the read and write access permissions for all 16 regions.\n\nThe old FRAP register seems to be still around, so we print both new\nand old registers. For the detailed report we use the new registers,\nthough.\n\nWe also adapt the descriptor detection slightly: We check for `NM \u003d\u003d 6`\njust like we did for Lewisburg. This way we won\u0027t treat a huge range of\nISL (ICH/PCH strap length) values as Emmitsburg, which should result in\nless false positives.\n\nThe output of `ich_descriptors_tool\u0027 tested on some Supermicro firmware\nlooks reasonable. Also tested read/erase/write in `swseq\u0027 and `hwseq\u0027\nmodes with 7 series PCH, reading with ADL-P. All logs still report FRAP\nsettings correctly.\n\nChange-Id: Ibf5ebe2e2edfe5e5ae26bf1136648bf6354b0aa9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/187\n" }, { "commit": "82fe12380a10ce24680ef7e4e4ea682ecc58a20c", "tree": "79dad3c3ba40a89360bab43d786ef8b3c0c44b9a", "parents": [ "157b81865725e9c544c9da323ab8ff93ff2c1ae5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 17:28:47 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ich_descriptors: Hard code number of masters for newer gens\n\nThe number of masters (NM) field is ignored by the hardware and often\nnot updated in Intel\u0027s tooling. Since PCH100 / Skylake, it\u0027s always\nbeen 2 masters for the small core, 5 for the big core, and 6 for the\nserver platforms.\n\nChange-Id: I4975f5b55981791fa5b10c4731af8f330cbbefa8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/185\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "157b81865725e9c544c9da323ab8ff93ff2c1ae5", "tree": "7c41dfdb3639efd6f68edcfe1b4841fb8f33bd88", "parents": [ "db878fb03658e560b9b19728d11c99ccbb961165" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 17:48:12 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ich_descriptors: Guard MCH strap handling by chipset version\n\nAt some point, Intel abandoned the classic MCH/processor strap layout\nidentified by the FMSBA/MSL fields. Avoid misinterpreting the fields\nthat replaced them by guarding all FMSBA/MSL references.\n\nChange-Id: Ib1ce357bd4db85282903cb7aa5ad6d6066b62c2d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/184\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "db878fb03658e560b9b19728d11c99ccbb961165", "tree": "c8b65acbd471be943b66ef4ace420d8be638f266", "parents": [ "b3cc2c6d3b39cc3c97d4130257b805a152a79b4c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 17:37:09 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ich_descriptors: Drop chipset detection based on `freq_read`\n\nFinish what commit 72a9dc0db4e6 (ich_descriptors: Don\u0027t base chipset\ndetection on `freq_read`) started: This was the original check that\n`ifdtool\u0027 used to distinguish pre/post PCH100 descriptors. Bringing\nthis into flashrom never helped, on better days it was only a mainte-\nnance burden, sometimes it even triggered the wrong path. Let\u0027s drop\nit before adding more platforms.\n\nChange-Id: Ic76f36df91e2816281a51fea1e693113b1d3db9c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/183\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "b3cc2c6d3b39cc3c97d4130257b805a152a79b4c", "tree": "a8175496af3d776dcd5b528a045bc8853d5f3455", "parents": [ "8e4151ddb5b4533aa004594e5009ad92159b0651" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 15 00:45:17 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ich_descriptors: Unify pretty printing of PCH100+ masters\n\nThe newer platforms mostly differ in names and numbers of masters and\nregions. Make that obvious, and write a generic printing loop. Hope-\nfully this will make future additions easier.\n\nChange-Id: I3e616064743e9558f799159ef8b702f2bbd8ec89\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/182\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "dfd064759b416463244aafea80a5b7120ef8e4e1", "tree": "b1b636199d652391f66e7af12b306877d77b1aee", "parents": [ "b2ad9fd9186a0f6fea3e5b64415c1e5d1a19baa4" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 23:45:05 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ich_descriptors: Refactor component density handling\n\nIntroduce a new marker CHIPSET_HAS_NEW_COMPONENT_DENSITY and order\nthe actual chipset values around it. This move Bay Trail up before\nall 8-series PCHs.\n\nChange-Id: I1f4d724e2e2ef038aa6a56feb1578208afbbcd99\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/181\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "b2ad9fd9186a0f6fea3e5b64415c1e5d1a19baa4", "tree": "c1c6ea1be6e93dbc787ba023f391c8e140d3112d", "parents": [ "140e22f260f7d96054207839bedf73aaae670d65" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 23:18:53 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ich_descriptors: Make use of SPI_ENGINE_PCH100 marker\n\nTested reading on ADL-P, log output stays consistent. Also compared\noutput of `ich_descriptors_tool\u0027 for various descriptors.\n\nChange-Id: I9f47ac571afd481998f56da0bd9481931353324a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/180\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "3f75d4476da015ae1ee033c1de1ad4dc08f66b0d", "tree": "f4c241b0df2bc758fc91c999f1326a06d0edec34", "parents": [ "2862011212da1745e4238381bfe16f0dab3fd7c1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 19:17:56 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ich_descriptors: Remove `Dual Output Fast Read\u0027 for newer gens\n\nThis is queried via SFDP since the Cannon Point PCH / Gemini Lake.\n\nAvoid using a relational comparison so we don\u0027t have to worry when\nchanging the enum order.\n\nTested `flashprog\u0027 on ADL-P and `ich_descriptors_tool\u0027 with various\ndescriptors.\n\nChange-Id: I4c60e8c01a019303a830d46561c80e6ad462bb7c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/172\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77", "tree": "ae3340f0a563d1d9ed48285cc861e7e90e2343ef", "parents": [ "a6b45c4516e15aeb405028e5095e86259fcd9e34" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Jan 17 15:11:43 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move mmio functions into hwaccess_physmap\n\nThe mmio_le/be_read/writex functions are used for raw memory access.\nBundle them with the physmap functions.\n\nChange-Id: I313062b078e89630c703038866ac93c651f0f49a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72278\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "671c0f006770588881ea5162a2bcc79001356fa7", "tree": "acba42f4e71562450455acc083c1b3d5fc46ce74", "parents": [ "49258610ebd4cec764c2d01e8fdf713b7067c96a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 16 20:17:19 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Drop `count` parameter of flashrom_layout_new()\n\nChange-Id: I22c180c9971068b1ae101845ce88484c6842b852\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/33544\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72218\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5bd990c2ab8ceb263d598a2348d7020ce774784f", "tree": "0ee2bdd6b6aa9af15becf68d7afd4142df0bf99c", "parents": [ "92e0b62fc37a6d89975ced41f5ec3c3715404f33" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 16 19:46:46 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Introduce flashrom_layout_new()\n\nIt initializes an empty layout. Currently the maximum number of entries\nhas to be specified, which will vanish once we use dynamic allocation\nper entry.\n\nWe replace the two special cases `single_layout` and `ich_layout` with\ndynamically allocated layouts. As a result, we have to take care to\nrelease the `default_layout` in a flashctx once we are done with it.\n\nChange-Id: I2ae7246493ff592e631cce924777925c7825e398\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72214\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "92e0b62fc37a6d89975ced41f5ec3c3715404f33", "tree": "9a9426d80db30846f31b2de2788df143fe75aa2d", "parents": [ "3a97fd5d46fe4d0f6f1be7a99123fd80645fe736" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 15:55:11 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Introduce flashrom_layout_add_region()\n\nAdds a region to an existing layout, as long as there is space.\n\nChange-Id: I50d473d0d5d1fb38bd6f9ae3d7127e9ea66a94e1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/33517\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Peter Marheine \u003cpmarheine@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72213\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3a97fd5d46fe4d0f6f1be7a99123fd80645fe736", "tree": "ebe7f7e1c92890374084f03ebaeee0efb99f5ea9", "parents": [ "354766b2fcc53d621a2c9f9c0b9f5f4c71ca0c8b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 15:44:39 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "layout: Add `capacity` field\n\nUse it to keep track of the size of the `entries` array. An interim\nsolution until we have dynamic allocation.\n\nChange-Id: Ib5f431bc0a72a79a53fa1376c3417942b19dd3a0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/33516\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Peter Marheine \u003cpmarheine@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72212\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ac90af6cdc747bfe3dc38c83c0b7272addf37659", "tree": "ec67fd7c4d01db82b5a1ffd8c8ed36a7229108dd", "parents": [ "bb4f3b06dcfb60a6ab84750c9b149482dc5ee579" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 18 00:22:47 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:34:15 2023 +0000" }, "message": "Change references to flashrom-stable\n\nAdapt all mentions of the mailing list and also the version print.\n\nChange-Id: Ib4a3271422ee6cf4d0efb8c3fa858b66a22c0a33\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70922\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d68a0ece50b2250ba25be67d27e8606247d5306c", "tree": "97d0a03f0b60954a0463ed2d1be9fc3237a867fb", "parents": [ "085572812789076e05faffd677264470dcea14c6" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 03:23:35 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "ich_descriptors.c: Retype variable `has_forbidden_opcode` with bool\n\nUse the bool type instead of an integer for the variable\n`has_forbidden_opcode`, since this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I6214956e377547b894fc76237832b6f7b2db41dd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66899\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71488\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f6c1cb1a856e67b8cf7eaf7a90b09bc3923a3718", "tree": "9776b733a8f851fe90b582068baae97e64425e40", "parents": [ "137f02f887144eae222e44adb675cb299fd00337" ], "author": { "name": "Martin Roth", "email": "gaumless@gmail.com", "time": "Tue Mar 15 10:55:25 2022 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Global cleanup: Fix a few spelling errors\n\nJust a trivial patch to fix a few errors found by codespell.\n\nHere\u0027s the command I used:\ncodespell -S subprojects,out \\\n-L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun\n\nSigned-off-by: Martin Roth \u003cgaumless@gmail.com\u003e\nChange-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71455\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "756b6b32e2a49c487d4bbc42d370e8826b41c922", "tree": "ce4db0712ab0fba0c5bed684ca67e012a2f2807d", "parents": [ "15095dbb7b9d7f1938d43e5ff3b99054b0798803" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 21 17:15:13 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Add Intel Jasper Lake support\n\nLoosely based on commit b01d7e9f (ichspi: Add Jasper Lake support)\non flashrom master.\n\nBesides a little change in descriptor detection, no difference to\nCannon Point was found. Hence, add new PCI IDs as 300 series.\n\nChange-Id: I9c715c1a5f1ceea32dc51669453d89b315ba8ca2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71453\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ac29566c7a4a8977875b65497904f05e5ceeb47", "tree": "d66b2fc87a4bb4cda966e0c9b68b3e1d4338efd8", "parents": [ "c9c7d52a98558075b0e52d8ace559e0e5b0923e4" ], "author": { "name": "aarya", "email": "aarya.chaumal@gmail.com", "time": "Sun Mar 13 15:35:12 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "ich_descriptors.c: Ensure unsigned types \u003e\u003d0 on to prevent underflow\n\nUnsigned types show undefined behaviour if they are subtracted by a\nvalue greater than their own (mostly it wraps to the max value). Using\nthis value for left shifting could be even more dangerous.\n\nflashrom-stable:\nThe actual issue here was that a static-analyzer didn\u0027t realize that\nthe second loop would only run, if ever, with `j \u003e\u003d 12`. So we made\nthat explicit.\n\nChange-Id: I5921cc571f3dca5188ca1973dba6ececbcbe2f39\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62764\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71451\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "29c23dd08474b2457ffd8a72ee3d8587676cd999", "tree": "73ccbc237df969f57ad5c9f7e044e0d4b9ca2656", "parents": [ "8efb0b337a46aaa5f2da902aa862d30e6a1305be" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 21 15:25:09 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Add Alder Lake support\n\nLoosely based on commit 11680db4 (ichspi: Add Alder Lake support)\non flashrom master.\n\nBeside a little change in descriptor detection, no difference to\nTiger Lake was found. Hence, add new PCI IDs as 500 series.\n\nChange-Id: Icc1278755ff64f03128d8faadbca85a4ff76864d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71448\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d3e8fd9dd50f45028d9cd987c649229c78b0e5e1", "tree": "bc2932802bae29104495956ca3c9a4d3c4d64246", "parents": [ "e57d4e49fd2556f0fe267833d35cc57b7e252c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Tue Jan 25 07:02:49 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors.c Invert the meaning of \u0027dual_output\u0027 bit\n\nIn the Flash Component description register (FLCOMP) bit 30 reports the\ncapability of using dual output for fast read operation on the flash\ncomponent. According to various SPI Programming Guides (checked for\nPanther Point, Lewisburg C620, Apollo Lake and Elkhart Lake) the dual\noutput is enabled when this bit is set and disabled if not. Currently the\nlogic displays it the other way around when parsing the descriptor.\n\nThis patch changes this so now if bit 30 in FLCOMP is not set, dual read\nsupport for fast read operation is shown as disabled.\n\nChange-Id: If6282ac8326ab0b92e9c70c09dba0299bf0deb6f\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61362\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71444\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e57d4e49fd2556f0fe267833d35cc57b7e252c06", "tree": "ef260430367f0d2025fd6c5c12c101f37639613e", "parents": [ "672bdcfd4ffeb065b7056042769e3cc512d87c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Mon Jan 03 09:44:29 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Elkhart Lake support\n\nElkhart Lake has a chipset called Mule Creek Canyon which is quite\ncompatible with 300 series chipsets. There are a few differences though,\ne.g. different encoding for the SPI clock values for read and write in\nthe FLCOMP register. In addition Elkhart Lake has a new PCI device ID\nfor the SPI controller which is added, too.\n\nTested: Read and flash complete flash on Siemens MC EHL1\n\nChange-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937", "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744", "parents": [ "cce1e5b8636ebef59dd509680594e17b0a207857" ], "author": { "name": "Michał Żygowski", "email": "michal.zygowski@3mdeb.com", "time": "Wed Jun 16 15:13:54 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cce1e5b8636ebef59dd509680594e17b0a207857", "tree": "5f50e5444c3d46b785af7e086ff60159bdf72250", "parents": [ "fa959bacf06a1db31cc82b5d601cc208faf11859" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Nov 02 20:33:35 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "hwaccess.c: move function declarations from programmer.h to hwaccess.h\n\nMove declarations for functions implemented in hwaccess.c from\nprogrammer.h to hwaccess.h.\n\nChange-Id: I075fd86211c766ae3d5f29c76adbd7c5b9bdbd80\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58865\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71436\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3bf7cfba9fca9b18d4ad5b843399bc00a3be1f49", "tree": "cc4c65492591a94835ad9a0c9617084ec8ab006e", "parents": [ "66565a7953b27a55cd963bb4f608c08f7d5237f0" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Mon Aug 30 23:25:06 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add support for Intel Emmitsburg PCH\n\nThis patch does the following:\n- Add PCIe ID for Intel Emmitsburg PCH\n- Based on ICH descriptor content, choose CHIPSET_C620_SERIES_LEWISBURG\n if ISL/PSL is 80.\n\nTested: tried on a server with Intel Emmitsburg PCH, flash update\nwas successful. This server, however, does not have flash chip\ninstalled, it instead has em100 emulator connected.\n\nChange-Id: I2a1bb7467e693d1583aa885fa0e277075edd4a3e\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nSigned-off-by: David Hendricks \u003cddaveh@amazon.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54965\nOriginal-Reviewed-by: Christian Walter \u003cchristian.walter@9elements.com\u003e\nOriginal-Reviewed-by: Johnny Lin \u003cJohnny_Lin@wiwynn.com\u003e\nOriginal-Reviewed-by: Tim Chu \u003cTim.Chu@quantatw.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71419\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "66565a7953b27a55cd963bb4f608c08f7d5237f0", "tree": "69f52540e49bbb94456a1961a308b3ab133c78f9", "parents": [ "fea5aa13d2845835f798c4709ee074433568d714" ], "author": { "name": "David Hendricks", "email": "ddaveh@amazon.com", "time": "Mon Sep 20 21:56:40 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Add explicit checks for all chipsets\n\nThis partially undoes changes made in commit cd9b7b427\n(ich_descriptors: Normalize chipset detection) to re-add explicit\nmatching of each chipset with one or more strap length values.\n\nSince ranges are checked explicitly, the `warn_if` parameter to\nwarn_peculiar_desc() is no longer necessary and is removed.\n\nChange-Id: Ica49477492876810a6fa212768b1ab9e8c12001f\nSigned-off-by: David Hendricks \u003cddaveh@amazon.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57793\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71418\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "81965f3c5acc663fab9efdaa0a48a814bcadad4e", "tree": "b4a30b0b936db08f7147b6c93f0f6840ae25bf79", "parents": [ "72a9dc0db4e6aa2a520f17015ecde93595286fbf" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 17 23:25:35 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Normalize chipset detection\n\nNormalize the fallback paths:\n* Always end with the newest, assumed compatible chipset.\n* Perform tighter checks when it\u0027s about warnings only.\n* If two chipsets seem compatible, always return the same\n (this is currently the case for 8/9 series and 300/400\n series which we can\u0027t distinguish).\n\nChange-Id: Ic5a5fee870202173b3a9813b03ec261e8ee45155\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55651\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71401\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "72a9dc0db4e6aa2a520f17015ecde93595286fbf", "tree": "b21529ac872a096419da8784630e4f73b22753f3", "parents": [ "3ad9aad483029c8b4c7c9f0b8dd362faf1c12ef3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 17 22:47:00 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Don\u0027t base chipset detection on `freq_read`\n\nOnly warn if the `freq_read` setting looks odd but don\u0027t override\nour previous guess. The `freq_read` check was taken from `ifdtool`\nbut seems less reliable than our own detection scheme.\n\nChange-Id: I658d76ec2567d1d660a18d0b0ae71c744e603e8f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55650\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71400\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ad9aad483029c8b4c7c9f0b8dd362faf1c12ef3", "tree": "74ad9724b0ab7db87fe06ba4323a16707107bf61", "parents": [ "66e04562f48cfb1f2266c316c81693ea73371a60" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 17 22:05:00 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Revise detection for chipsets w/ ICCRIBA\n\nDetection based on ICCRIBA and FMSBA became a little messy lately.\nHowever, there\u0027s a new static difference: Since 300 series (Cannon\nPoint), there is an MDTBA field in FLUMAP1 that has always been 0\n(reserved) before. Taking this into account, we can relax the checks\non ICCRIBA.\n\nChange-Id: I587ad1abe390843d4a9e74431b6fc4b63f8ba512\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55647\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71399\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8a03c90f41a6ca79c7bf183ad07e2b30702bfd46", "tree": "9acfb7f68e05f0d7166357ab6f37c07adea669a3", "parents": [ "83b01c8a0f67143594a3befbb2668775e1d28aba" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 17 21:23:29 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Refactor read_ich_descriptors_from_dump()\n\nProcess the \"upper map\" early as it doesn\u0027t depend on the descriptor\ngeneration. This way, we can use it to guess the generation.\n\nChange-Id: Ia2786b762ccefdce31b63397119bd89879e887ff\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55646\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71386\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "83b01c8a0f67143594a3befbb2668775e1d28aba", "tree": "d9ae99bfbeef9e73b47177ef9d606cb82f2fd7bf", "parents": [ "964007ad72a8a9be9c462ff4e03d73c0d9f7c577" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 17 21:20:09 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Drop some unnecessary `else` after `return`\n\nChange-Id: Id739bc12832e3b441e8e7e1dcdcc4c05b260d7ad\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55645\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71385\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "964007ad72a8a9be9c462ff4e03d73c0d9f7c577", "tree": "8125ec38d11a6c72f4d45a0dfdacfdaa50527936", "parents": [ "40d3233e17e07f7616702b9968468816f4db9520" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 17 21:12:47 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "ich_descriptors: Revise descriptor messages\n\nCorrect \"firmware descriptor\" to \"flash descriptor\". And also\nmove the check for peculiar descriptors and the message into an\ninline function.\n\nChange-Id: I7f15780e03d2fa17ca6d8328275cae5af13ae424\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55644\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71384\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113", "tree": "5866347a6c5e63477f8e05cc32443085319c2df3", "parents": [ "771bb7952a91722d2d9f100e19b0566f06298126" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 10 17:04:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4f29bb799b4672eebcc0bdfc6fb544b2b5544b6f", "tree": "8a27542cc468d103319c7c36afe894f57870f59a", "parents": [ "c753c40971c1481943e8a18dc24b33037e2a579d" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@gmail.com", "time": "Wed Aug 12 12:48:06 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "Add support for Comet Lake-U/400-series PCH\n\nAdd enum CHIPSET_400_SERIES_COMET_POINT and treat it identically\nto CHIPSET_300_SERIES_CANNON_POINT.\n\nAdd PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT.\n\nTest: read/write unlocked CML-U board\n\nflashrom-stable:\nAs suggested above, treat it the same as 300 series. But don\u0027t add a\nnew enum.\n\nChange-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71325\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e19a41b5411c1a693ad81e9b138ac7d474bad495", "tree": "5d906d491859296f784ec0255beebabf07242077", "parents": [ "3531123fda54237b096ec67a932ce2ff8f544a1f" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Wed Aug 19 12:19:06 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG\n\nIntel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA.\n\nFix guess_ich_chipset_from_content() accordingly.\n\nPrint status info of read_ich_descriptors_from_dump() to facilitate\ndebugging upon failure.\n\nTested: run flashrom successfully from OCP Yosemite V3 DeltaLake server.\n\nChange-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44621\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71322\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "961f4a1f29787cbb6bd9a8a43b6ac4f3f0d024c0", "tree": "13023be2c6cc0140cbfa97dee108a441e696b638", "parents": [ "b417c0c2d2616feff30cc87316a278055da8c64a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:34:22 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:26:25 2019 +0000" }, "message": "Fix more sign-compare issues\n\nThe one in the `dummyflasher` is a little peculiar. We actually never\nknew the type of the `st_size` field in `struct stat`. It happens to\nbe `signed` in some systems (e.g. DJGPP).\n\nChange-Id: If36ba22606021400b385ea6083eacc7b360c20c5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35800\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "d2d3993a25c3236d397209f9c2118c3b17ce4f95", "tree": "8c91f0f2d588e66963c13e48dd972de555985bf4", "parents": [ "3750986348cb99b8f0d828b73972b545a2f9c878" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 16:49:37 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:23:53 2019 +0000" }, "message": "ichspi: Add Apollo Lake support\n\nIt\u0027s almost identical to 100 series PCHs and later. There are some\nadditional FREGs (12..15). To not clutter the `if` conditions further,\nmake more use of `switch` statements.\n\nTested on Kontron mAL10. Mark it as DEP as usually the last sector\nis not covered by the descriptor layout and can\u0027t be read.\n\nChange-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30995\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "beeb8bc925bef6973e1c9fa6c4fd26a4113a1777", "tree": "30c63cf4ae4bb14a19849b1680622ad6eed86d63", "parents": [ "cb44eb7dad17522f47792dca4fc499310ff7d6f3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:24:17 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:39:31 2019 +0000" }, "message": "tree: Make internal functions static\n\nNone of these functions are used outside of the files they are defined\nin, so make them all static.\n\nChange-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33667\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "70461a9524fc84ec5c095f11927cffa0429a6267", "tree": "0df6b67aec1d936bf8b39a86d5d9ed97ef5aa125", "parents": [ "4f213285d78974c4b8915b311aff88449279f554" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jun 15 14:56:19 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 17 08:32:43 2019 +0000" }, "message": "layout: Make `romentry.name` a pointer\n\nThis should provide more flexibility while we don\u0027t have to allocate\n256B extra per layout entry.\n\nChange-Id: Ibb903113550ec13f43cbbd0a412c8f35fe1cf454\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33515\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "129e938e4c79caccc376d05869d2b2d08a0664ec", "tree": "9500d1d8476aaaf5ffb34f157a1e2862e55f028e", "parents": [ "32b9f5c665f4fd65d9ba742e72ae8e762f33762f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:43:27 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 07 12:32:14 2019 +0000" }, "message": "ich_descriptors: Drop line numbering comments\n\nChange-Id: Ia895e35edfc86b6955395c4570d67477da70e2c7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33256\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "db7482bb72035fab8386226d1720cde09e0c700e", "tree": "8a2114a45c22a44e01d8494f224b38c35b17cb71", "parents": [ "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 12:04:30 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 11 23:50:12 2019 +0000" }, "message": "Fix several -Wno-implicit-fallthrough warnings\n\nGCC is picky about the comment being where the break should go.\n\nChange-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30406\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4d440a7c4102faae21b16204e667ea74c1dc8e52", "tree": "7122caef5133c365278a24d93cb7991a49aa36ae", "parents": [ "8e76230dfbcc7720c5565a70daff650496556702" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Aug 15 11:26:48 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Aug 16 17:01:59 2017 +0000" }, "message": "Include \u003csys/types.h\u003e wherever ssize_t is used\n\n`ssize_t` is a POSIX type (cf. IEEE Std 1003.1).\n\nChange-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21015\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "67d71792929f94d4638a3663f2fc19aea4918681", "tree": "ea1f35914191ac66f66734777a1e1542ea20b403", "parents": [ "500263434b69594dc01b3ccfe5e2c4c498d87656" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Jun 17 03:10:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:31:58 2017 +0000" }, "message": "ich_descriptors: Pretty print an assumed chipset\n\nChange-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20247\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa62294536a3ce5070e8d9065aaa1aa45031f910", "tree": "66152f87787e5c3c6ce2c9db903f8e1a70bd9311", "parents": [ "1dc3d420831b0ee482aede5f46ba53a0d2de4b74" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 24 17:25:37 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:30:21 2017 +0000" }, "message": "ich_descriptors: Update for Intel Skylake\n\nInterpretation of component clocks changed. Also more regions and more\nmasters are supported now. The number of regions (NR) is now static per\nchipset (10 in the 100 Series case) and not coded into the descriptor\nany more.\n\nv2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().\n o Update region extraction in `ich_descriptors_tool`.\n\nTEST\u003dRun `ich_descriptors_tool` over a 100 Series dump and checked\n that output looks sane. Run `ich_descriptors_tool` over dumps\n of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,\n 1 x Haswell). Beside whitespace changes, regions not accounted\n by `NR` are not printed any more.\n\nChange-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18973\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1dc3d420831b0ee482aede5f46ba53a0d2de4b74", "tree": "2c42e68012e89e5dec203874eaa0b3e6e6e086e6", "parents": [ "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Jun 17 00:09:31 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:26:01 2017 +0000" }, "message": "ich_descriptors: Add function to guess chipset version\n\nAdd guess_ich_chipset() that takes fields from a descriptor dump and\nreturns the lowest possible chipset version.\n\nIntel did several incompatible changes to the descriptor through the\nyears. However, they forgot to add a version number. So we have to\napply some heuristics to detect the chipset version in case of exter-\nnal flashing.\n\nChange-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20246\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9", "tree": "1bd56eecff210a628c148c836e2dfce13ebfd5f8", "parents": [ "d54e4f467753a247552bfb629f007f8931b0caa7" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 16:44:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:24:06 2017 +0000" }, "message": "ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()\n\nThe condition `base \u003e limit` is still valid since `base` is always at\nleast 4096 greater than `limit` in this case.\n\nChange-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19046\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d54e4f467753a247552bfb629f007f8931b0caa7", "tree": "0a7bb8254865783ad1fa1dc958e74e1a57936953", "parents": [ "93c306939b732fb05f6d8a692acc3fca78bc0f9f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 23 23:45:47 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:22:58 2017 +0000" }, "message": "ichspi: Add support for Intel Skylake\n\nThe Sunrise Point PCH, paired with Skylake, has some minor changes\nin the HW sequencing interface:\n\n * Support for more flash regions moved PR* registers\n * Only 4KiB erase blocks are supported by the primary erase command\n * A second erase command for 64KiB pages was added\n * More commands were added for status register access etc.\n * A \"Dedicated Lock Bits\" register was added\n\nNo support for the new commands was added.\n\nThe SW sequencing interface seems to have moved register location and\nis not supported any more officially. It\u0027s also untested.\n\nChanges are loosely based on the Skylake support commit in Chromium OS\nby Ramya Vijaykumar:\n\n commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1\n Author: Ramya Vijaykumar \u003cramya.vijaykumar@intel.com\u003e\n\n flashrom: Add Skylake platform support\n\nChange-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "8d494992176abe0877c88f06fdbc9c8d8826ae87", "tree": "f1755cda3f7c271c5510b98d9a11785b715eb360", "parents": [ "e8e7a80e6b876710bebaa9f5a0b6f5e083d47516" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:18:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 13:27:13 2017 +0200" }, "message": "fixup! Make read_ich_descriptors_from_dump() available in flashrom\n\nAdd a guard around read_ich_descriptors_via_fdo() which uses raw\nhardware access and is only called from `ichspi`.\n\nFixes linking in case `NEED_RAW_ACCESS !\u003d 1`.\n\nChange-Id: I5a35c607df44cdbcbacb960f8922c1bf9f1f2002\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20265\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "512059118e9ff56d2b4f3c324db5e764e288ac68", "tree": "7c3c384d1579b467135fd85dd9cfbb88abb4771c", "parents": [ "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 17 17:59:54 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:47:49 2017 +0200" }, "message": "Handle Intel Wildcat Point *LP* like Lynx Point LP\n\nThe subtle difference was ignored when adding these chipsets. The\nintegrated Wildcat Point LP PCH is documented in [1].\n\nI\u0027m not sure how to account for \"Broadwell H\" which seems not publicly\ndocumented. Maybe it\u0027s an unreleased HM9*, in which case the non-LP\npath should be correct.\n\n[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,\n Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor\n Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet\n Revision 004\n Document Number: 330837\n\nChange-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18883\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359", "tree": "3f7ac3cbf792ad89f581ff7884e6bff4a4577ca0", "parents": [ "7258cf5197d2f1502430ad1c64027af2b341b7a6" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 16:31:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:47:24 2017 +0200" }, "message": "ich_descriptors: Fix more odd +1s\n\n+1 on everything doesn\u0027t make software greater per se.\n\nv2: o Fix another +1.\n o Amend style of similar (not +1 suffering) code, too.\n\nChange-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19044\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "305f417ea565a18c1e87dcf5d97307369b721c6c", "tree": "75fd4a1087415f99a64d0a5f26eaddcb54969883", "parents": [ "ad18631b59d814b38bb6757df93fac17937a6bc9" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jun 14 11:55:26 2013 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 11:43:32 2017 +0200" }, "message": "Add option to read ROM layout from IFD\n\nAdd an option --ifd to read the ROM layout from an Intel Firmware\nDescriptor (IFD). Works the same as the -l option, if given, -i\nspecifies the images to update.\n\nv2: o Rebased on libflashrom, use libflashrom interface.\n o Use functions from ich_descriptors.c.\n\nv3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent\n of arch and programmers.\n o Bail out if we aren\u0027t compiled for little endian.\n o Update flashrom.8.tmpl.\n\nv4: o Incorporated David\u0027s comments.\n o Removed single-character `-d` option.\n\nv5: Changed region names to match the output of `ifdtool --layout ...`\n\nChange-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17953\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "ad18631b59d814b38bb6757df93fac17937a6bc9", "tree": "64a5fde5ab5bc0432fa74e3c263291e931330e3e", "parents": [ "3828b39263d008fb6cc5ebdbe7fb49bc6f926566" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon May 02 15:15:29 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jun 14 11:32:36 2017 +0200" }, "message": "Make read_ich_descriptors_from_dump() available in flashrom\n\nI didn\u0027t really know what I was doing and hope removing the #ifdefs\ndoesn\u0027t have negative side effects.\n\nThe idea is to make the functions generally available for external\nflashing (e.g. you might want to flash an Intel machine using an ARM\ndevice as programmer).\n\nBeware of big endian trouble, I guess. :-P\n\nChange-Id: Ib3d38a622a581afee87b49777e775942cc901fc8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/17952\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "9e14aeda6464b2ecb391186e5b21bf5985141499", "tree": "0eec081e85ff96879d2f9b101212974b6d33cbcd", "parents": [ "d2a03b3e43043b596a79803bcb93f70e513bbb50" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Mar 28 17:08:46 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu May 04 12:45:57 2017 +0200" }, "message": "ich_descriptors: Fix range checks for dumps\n\nThese explicit off-by-one calculations were... off-by-one.\n\nChange-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19031\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "60dead4aee579f9da86549ce33d7de29de4e043b", "tree": "5ede315815890d8f8ff89c6f28590403d502c824", "parents": [ "80e647158800d927c776d1278d8817f0ed8f17cd" ], "author": { "name": "Tai-Hong Wu", "email": "thwu@lunartoday.com", "time": "Mon Jan 05 23:00:14 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Jan 05 23:00:14 2015 +0000" }, "message": "Fix wrong density encoding on Intel Silvermont\n\nSilvermont (Bay Trail, Rangeley, Avoton) seems to still use the old\ndensity encoding with 3 bits per chip. Documentation is unavailable\n(held concealed by Intel) but thanks to the efforts of Tai-Hong\n(Type) Wu the layout is clear now. This patch is based on his one\nbut solves the issue differently thus reducing the code complexity.\n\nCorresponding to flashrom svn r1861.\n\nSigned-off-by: Tai-Hong Wu \u003cthwu@lunartoday.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "823096e5270dc7ccd8b0315377428556d1987dcf", "tree": "53fbf8653802401b1a35a6046aa8c54e0f8b0d1a", "parents": [ "4095ed797f87c92b52e15d9f6fdc0b895c414cc9" ], "author": { "name": "Duncan Laurie", "email": "dlaurie@chromium.org", "time": "Wed Aug 20 15:39:38 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:38 2014 +0000" }, "message": "Add support for Intel Wildcat Point PCH\n\nThe Wildcat Point PCH can be paired with Broadwell or Haswell.\nThis patch was essentially backported from ChromiumOS commit 9bd2af8.\n\nCorresponding to flashrom svn r1845.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "4095ed797f87c92b52e15d9f6fdc0b895c414cc9", "tree": "deaca4de25e5bafc24fe0a48a401a8d4f062a170", "parents": [ "2ba9f6ebe56b208a1fb0b0ce5edf81097a0158be" ], "author": { "name": "Duncan Laurie", "email": "dlaurie@chromium.org", "time": "Wed Aug 20 15:39:32 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:32 2014 +0000" }, "message": "Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton\n\nThe core of this patch to support Bay Trail originally came from the\nChromiumos flashrom repo and was modified by Sage to support the\nRangeley/Avoton parts as well.\nBecause that was not complicated enough already Stefan Tauner refactored\nand refined everything. Bay Trail seems to be the first Atom SoC able to\nsupport hwseq. No SPI Programming Guide could be obtained so it is\nhandled similarly to Lynx Point which seems to be its nearest relative.\n\nCorresponding to flashrom svn r1844.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Martin Roth \u003cgaumless@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Marc Jones \u003cmarcj303@gmail.com\u003e\nTested-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Thomas Reardon \u003cthomas_reardon@hotmail.com\u003e\nTested-by: Wen Wang \u003cwen.wang@adiengineering.com\u003e\nAcked-by: Marc Jones \u003cmarcj303@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "2ba9f6ebe56b208a1fb0b0ce5edf81097a0158be", "tree": "06741544f702c84fa5fcbc5edb8a888530917481", "parents": [ "9e3a6984da1bb38af37ce4bb54af8f7475b7c766" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:19 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:19 2014 +0000" }, "message": "Refine Flash Component descriptor handling\n\nPossible values as well as encodings have changed in newer chipsets as follows.\n - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all\n operations\n - Since Cougar Point the chipsets support dual output fast reads (encoded\n in bit 30).\n - Flash component density encoding has changed from 3 to 4 bits with Lynx\n Point, currently allowing for up to 64 MB chips.\n\nCorresponding to flashrom svn r1843.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "0554ca5cd33fe2cc599cfdbe91fff03c8fa752c5", "tree": "1d37d76b5b3d810c6b2a1286a5de7c2b60ce69a0", "parents": [ "305e0b999a7d452a845709d5558c17a31afe178c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jul 25 22:54:25 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jul 25 22:54:25 2013 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 18\n\nTested mainboards:\nOK:\n - ASUS C60M1-I\n http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html\n - ASUS P8H77-I\n http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html\n - ASUS P8H77-M\n http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html\n - ASUS P8P67 LE (B2)\n http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html\n - Elitegroup GeForce6100PM-M2 (V3.0)\n http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html\n - GIGABYTE GA-P55A-UD7\n http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html\n - MSI B75MA-E33 (MS-7808)\n http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html\n - MSI H77MA-G43 (MS-7756)\n http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html\n - MSI KA780G (MS-7551)\n http://paste.flashrom.org/view.php?id\u003d1617\n - SAPPHIRE IPC-E350M1\n Reported by xvilka on IRC\n - Supermicro X8DTG-D\n http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html\nNOT OK:\n - ASRock Fatal1ty Z77 Performance\n http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html\n - ASRock Z68 Extreme4\n http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html\n - ASUS P8B75-M LE\n http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html\n - ASUS P8P67-M PRO\n http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html\n - ASUS P8Z68-V LE\n http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html\n - Intel DQ77MK\n http://paste.flashrom.org/view.php?id\u003d1603\n - Supermicro X9DRD-7LN4F\n http://paste.flashrom.org/view.php?id\u003d1582\n - Supermicro X9SCE-F\n http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html\n - Supermicro X9SCM-F\n http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html\n - Tyan S7066\n http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html\n\nChipsets:\n - Marked Intel B75 as tested\n http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html\n - Marked Intel H77 as tested\n http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html\n - Removed 10de:03e2 because it is apparently the MCP61 host bridge.\n It was reclassified to Host Bridge in the PCI device ID database and there\n is at least one report suggesting this configuration too:\n http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html\n - Added MCP89 which hopefully works with the code for previous versions.\n Thanks to James Laird for submitting this change.\n\nTested flash chips:\n - Atmel AT25DF641(A) to PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html\n - Atmel AT25F512 to PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html\n Also, change its ID according to Modification of PCN SC040401A:\n \"There has been a change in the returned value of the Product Identification\n (RDID) command, the AT25F512A RDID code is 65h compared to 60h from\n the AT25F512 product.\"\n It seems to be quite likely that all AT25F512 are fully functional relabeled\n AT25F1024 chips. There are even some hints in the datasheet:\n in table 6 they stress that address pin 16 needs to be low under all circum-\n stances; while continuous reads can wrap around on the AT25F1024 the DS\n notes \"For the AT25F512, the read command must be terminated when the\n highest address (00FFFF) is reached.\" OTOH the lock bit semantics are\n different, but this has not been tested thoroughly\n - Atmel AT25F512A to PREW (+PREW)\n http://paste.flashrom.org/view.php?id\u003d1569\n - Eon EN25F05 to PREW (+PREW)\n http://paste.flashrom.org/view.php?id\u003d1571\n - Macronix MX25L12805(D) to PREW (+REW)\n http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html\n - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P)\n Tested by Stefan Tauner\n - Micron/Numonyx/ST M25PX80 to PREW (+PREW)\n Tested by Stefan Tauner\n - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW)\n Tested by Stefan Tauner\n - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P)\n Tested by Stefan Tauner\n - SST SST25VF040B to PREW (+PREW)\n http://paste.flashrom.org/view.php?id\u003d1574\n - SST SST25VF040B.REMS to PREW (+EW)\n http://paste.flashrom.org/view.php?id\u003d1575\n - ST M25P05-A to PREW (+PREW)\n http://paste.flashrom.org/view.php?id\u003d1576\n - ST M29W512B to PREW (+W)\n http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html\n - Winbond W25Q64.W to PREW (+PREW)\n Tested by the chromiumos guys.\n - Winbond W25Q128.V to PREW (+REW)\n http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html\n - Winbond W25X20 to PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html\n\nMiscellaneous:\n - Add Lenovo X201 to the laptop whitelist.\n - Add chip IDs for the ESMT F25L..QA family.\n - Add chip IDs for a few Macronix MX25 models.\n - The list of flashchips is not sorted strictly alphabetically and should not be\n either. Refine the comment explaining the scheme on top of the list.\n - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb).\n - Use z length modifier in (more) prints for size_t types.\n - Remove chips \u003e16MB again because our current implementation of memory mapping\n the flash chip violates common rules by mapping a window as large as the chip.\n This leads to failing mmaps as can be seen here:\n http://paste.flashrom.org/view.php?id\u003d1695\n - Document spispeed parameter of linux_spi (and fix some leaks).\n - Rephrase the \"multiple chips detected\" message because it was confusing.\n - Skip verification step if the image is equal to the flash contents.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1702.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "67d163d2fa6e7db9673e8ec820b8ef21bca5e907", "tree": "3cfa28408caa64594638f4a5cad7f5deafa8506a", "parents": [ "8225868465f6ad75958a1f81514d9c4978487184" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Jan 15 17:37:48 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Jan 15 17:37:48 2013 +0000" }, "message": "Fix duplicate \u0027const\u0027 declaration specifiers\n\nThanks to Idwer and clang for noticing these problems.\n\nCorresponding to flashrom svn r1646.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nSigned-off-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a1a14ec5d2a087937ce6e16a4462fcfeb838fa12", "tree": "7a9d855a9df6e78d31b0d9842b7c3f1d31711825", "parents": [ "37e8686284eb45bdb1717088227e3fe485fb0fc4" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Aug 13 08:45:13 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Aug 13 08:45:13 2012 +0000" }, "message": "Clean up ICH descriptor code\n\n - allows for compilation with -Werror\u003dshadow,\n - use extended line limit to fix the most awful line breaks.\n\nCorresponding to flashrom svn r1570.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "2abab94c18721181c8d517b8e31ffada22145ea9", "tree": "5942453208bdb73ff2bfeadc94fbacf79d5bf023", "parents": [ "23bb6d579f0e8d76905ee108b85db10b0cf11f90" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Apr 27 20:41:23 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Apr 27 20:41:23 2012 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 12\n\nTested Mainboards:\nOK:\n - ASUS M4A785T-M\n http://www.flashrom.org/pipermail/flashrom/2012-April/009118.html\n - ASUS P5VD2-MX\n http://www.flashrom.org/pipermail/flashrom/2012-March/009014.html\n - ASUS P8Z68-V PRO/GEN3\n http://www.flashrom.org/pipermail/flashrom/2012-April/009086.html\n - Bachmann electronic OT200\n http://www.flashrom.org/pipermail/flashrom/2012-April/009094.html\n - Biostar N61PB-M2S\n http://www.flashrom.org/pipermail/flashrom/2012-March/008958.html\n - GIGABYTE GA-H61M-D2-B3\n http://www.flashrom.org/pipermail/flashrom/2012-March/009002.html\n - MSI MS-7740 (H61MA-E35(B3))\n http://www.flashrom.org/pipermail/flashrom/2012-March/008985.html\n - Tyan S2875 (Tiger K8W)\n http://www.flashrom.org/pipermail/flashrom/2012-March/008986.html\n - ZOTAC nForce 630i Supreme (N73U-Supreme)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009073.html\n - ZOTAC ZBOX AD02 (PLUS)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009047.html\nNOT OK:\n - ASRock H67M\n http://www.flashrom.org/pipermail/flashrom/2012-March/008909.html\n - ASUS P8P67 LE\n http://paste.flashrom.org/view.php?id\u003d1097\n - ASUS Maximus IV Extreme\n http://www.flashrom.org/pipermail/flashrom/2012-March/009033.html\n - Biostar H61MU3\n http://www.flashrom.org/pipermail/flashrom/2012-February/008832.html\n - Biostar M7VIQ\n http://www.flashrom.org/pipermail/flashrom/2012-February/008863.html\n - Dell Inspiron 580\n http://www.flashrom.org/pipermail/flashrom/2012-March/008888.html\n - Dell Vostro 460\n http://www.flashrom.org/pipermail/flashrom/2012-April/009144.html\n - Fujitsu-Siemens CELSIUS W410 (D3062-A1)\n http://www.flashrom.org/pipermail/flashrom/2012-March/008987.html\n - EPoX EP-3PTA\n http://www.flashrom.org/pipermail/flashrom/2012-April/009043.html\n - HP XW6400\n http://www.flashrom.org/pipermail/flashrom/2012-March/009006.html\n - HP XW9300\n http://www.flashrom.org/pipermail/flashrom/2012-February/008862.html\n - Intel DG965OT\n http://paste.flashrom.org/view.php?id\u003d1096\n - Intel DN2800MT (Marshalltown)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009095.html\n - Lenovo T420\n http://paste.flashrom.org/view.php?id\u003d1095\n - Lenovo X1\n http://www.flashrom.org/pipermail/flashrom/2012-April/009135.html\n - MSI GF615M-P33\n http://www.flashrom.org/pipermail/flashrom/2012-March/008956.html\n\nTested flash chips:\n - mark EN25Q32(A/B) as TEST_OK_PROBE (+P)\n http://www.flashrom.org/pipermail/flashrom/2012-February/008832.html\n - mark S25FL032A as TEST_OK_PR (+PR)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009105.html\n - mark AT25DF161 as TEST_OK_PROBE (+P)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009095.html\n - mark SST as TEST_OK_PREW (+EW)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009094.html\n\nTested chipset enables:\n - H61 (various reports)\n - SiS 755\n http://www.flashrom.org/pipermail/flashrom/2012-April/009072.html\n\n - Fix compilation of ich_descriptor_tool which was broken since r1492.\n - Add Documentation regarding unlocking the ME region on Intel chipsets.\n - Fix reading the flash descriptor via FDOC/FDOD and prettyprinting of the\n descriptor on boards with 5 active regions.\n - Reorder some boards in print.c.\n - Add Intel 7 Series (Panther Point) PCI IDs.\n - Add preliminary PCI IDs for future Intel chipsets (DH89xxCC and Lynx Point)\n see https://lkml.org/lkml/2012/2/20/467\n - Change the message for untested chipsets to send only after an attempt to\n update the firmware with flashrom.\n - Fix warnings in ich_descriptor_tool\u0027s build.\n\nCorresponding to flashrom svn r1524.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "b3850964f6a87f107e7eaae16d75299f32cc6e76", "tree": "9af3d08c6dfd14c5ef741db24abcc1507b5f045c", "parents": [ "222bf1013f39808e42479cd2f1cc2687cc59e657" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 24 00:00:32 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 24 00:00:32 2011 +0000" }, "message": "Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file\n\nThis patch adds an external utility that shares most of the existing descriptor\ndecoding source code. Additionally to what is available via FDOC/FDOD this\nallows to access:\n - the softstraps which are used to configure the chipset by flash content\n without the need for BIOS routines. on ICH8 it is possible to read those\n with FDOC/FDOC too, but this was removed in later chipsets.\n - the ME VSCC (Vendor Specific Component Capabilities) table. simply put,\n this is an SPI chip database used to figure out the flash\u0027s capabilities.\n - the MAC address stored in the GbE image.\n\nIntel thinks this information should be confidential for ICH9 and up, but\nreferences some tidbits in their public documentation.\nThis patch includes the human-readable information for ICH8, Ibex Peak\n(5 series) and Cougar Point (6 series); the latter two were obtained from\nleaked \"SPI Flash Programming Guides\" found by google. Data regarding ICH9\nand 10 is unknown to us yet. It can probably found in:\n\"Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide\"\nInformation regarding the upcoming Panther Point chipset is also not included.\n\nCorresponding to flashrom svn r1480.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Matthias Wenzel \u003cbios@mazzoo.de\u003e\n" }, { "commit": "d0c5dc23e25f33439dd6166a5798ffbcaabf67f8", "tree": "46817260e91768863e9815741486d0f1b0a804bc", "parents": [ "836b26a423c5dad86646bc6bc24560d444181405" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Oct 20 12:57:14 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Oct 20 12:57:14 2011 +0000" }, "message": "ichspi: add (partially) dead support code for Intel Hardware Sequencing\n\nThis was done to ease the review. Another patch will hook up (and\nexplain) this code later.\n\nCorresponding to flashrom svn r1452.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "1e14639f4268c21a9200fe45a8c8235472cde1c2", "tree": "522d54a0740bb86c1e3307823a09c37098dfe667", "parents": [ "c93f5f123239121fdeba03c02f9e448ed97c52a4" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 15 23:52:55 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 15 23:52:55 2011 +0000" }, "message": "ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD\n\nBased on the work of Matthias \u0027mazzoo\u0027 Wenzel this patch adds pretty\nprinting of those ICH/PCH flash descriptor sections that are\ncached/mapped by the chipset (and which are therefore reachable via\nFDOC/FDOD registers).\n\nthis includes the following:\n- content section:\n describes the image and some generic properties (number of\n sections, offset of sections, PCH/ICH and MCH/PROC strap\n offsets and lengths)\n- component section:\n identify the different SPI flash chips and their capabilities.\n- region section\n similarly to a partition table this describes the different regions.\n the content of FLREG* is derived from this section.\n- master section\n defines SPI master (host, ME, GbE) access rights of the\n individual regions. the content of PR* is derived from this section.\n\nthis is only a part of the data included in the descriptor. other\ninformation can be retrieved from a complete binary dump of the\ndescriptor region only.\n\nthis patch also adds macros and pretty printing for \"Vendor Specific\nComponent Capabilities\" registers: there are two of them: lower and\nupper. they describe the properties of the address space divided by\nFPBA (which allows to use multiple flash chips or partitions with\ndifferent properties). the properties of all supported flash chips\n(together with their RDIDs) are stored in the same format in table\nin a descriptor section (which is used by the ME apparently). a\nlater patch will use the macros outside of ichspi.c which is the\nreason why the prettyprinting function and the register bit macros\nare not defined in ichspi.c but ich_descriptors.h (else they would\nbe moved in the follow-up patch).\n\nbecause this patch relies on (compiler) implementation-specific\nlayouting of bit-fields, it checks for correct layout before taking\nany action on runtime.\n\nCorresponding to flashrom svn r1443.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" } ] }