)]}' { "log": [ { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "2f75379fa20f5415c70b837001473ff8ba070ab7", "tree": "0f549c33c16f70f1c619926d91ce217e95eccd6a", "parents": [ "b1d4b1d6b8a7876496af6b8af422d1c8058d5f4e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 28 00:46:50 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 04 09:59:35 2023 +0000" }, "message": "internal: Don\u0027t try linux_mtd on x86\n\nWe assume that the first MTD device found represents the \"internal\"\nfirmware flash. This is true on many architectures, and assumed to\nbe working. On x86, however, there is traditionally no MTD device.\nOne exception is the `spi-intel` driver, but this one is tagged\n\"DANGEROUS\" and often makes trouble if a Linux distribution enabled\nit nevertheless.\n\nSo, let\u0027s disable the internal/MTD automatism on x86. Flashrom has\nbetter drivers, and if somebody runs into a situation where the MTD\ndriver would work but the internal one doesn\u0027t, they can still use\n`linux_mtd` explicitly.\n\nChange-Id: I813980786a09fe64f541906e1963b0abd8b93cb5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73987\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "618994707d5ba556704ad9555191379cf46df6ae", "tree": "ad771fb01ca88cbf4ed3e93da0576f4a831a3929", "parents": [ "28790a23f71d942f7ec9aa03c5ec90fb90503d0f" ], "author": { "name": "Steve Markgraf", "email": "steve@steve-m.de", "time": "Mon Jan 09 23:06:52 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 04 12:33:03 2023 +0000" }, "message": "programmer: Add bitbanging programmer driver for Linux libgpiod\n\nWith this driver, any single board computer, old smartphone, etc. with\na few spare GPIOs can be used for flashrom.\n\nTested by reading of a 2048 kB flash chip on a Qualcomm MSM8916 SoC\n@800 MHz, ran the following command:\n\ntime flashrom -p linux_gpiod:gpiochip\u003d0,cs\u003d18,sck\u003d19,mosi\u003d13,miso\u003d56 -r test.bin\n\nThis command uses /dev/gpiochip0 with the specified GPIO numbers for the\nSPI lines. All arguments are mandatory.\n\nOutput:\n[...]\nFound GigaDevice flash chip \"GD25LQ16\" (2048 kB, SPI) on linux_gpiod.\n[...]\nreal 1m 33.96s\n\nChange-Id: Icad3eb7764f28feaea51bda3a7893da724c86d06\nSigned-off-by: Steve Markgraf \u003csteve@steve-m.de\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73290\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0e78818c2c818aa860a976524cfdf552792cfeba", "tree": "0bd2c0ba9086639ba4c49259bfef7777ce95a82a", "parents": [ "a447c12ecf71954f40a2b07817b3933b7bd3e495" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Wed May 26 09:54:08 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 04 12:33:03 2023 +0000" }, "message": "bitbang: Extend bitbang_spi_master functions to accept spi data\n\nThis way every bitbang spi master has access to its own spi data,\nand can use this data in all its functions.\n\nThis patch only changes the signatures of functions.\n\nflashrom-stable: Adapted new function signatures in `nicintel_spi`.\n\nChange-Id: Id5722a43ce20feeed62630ad80e14df7744f9c02\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54991\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73268\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a447c12ecf71954f40a2b07817b3933b7bd3e495", "tree": "073037c43b3dc9b5f6c0204cc5ea8ef0161b7271", "parents": [ "cbc5ba049f7d6ce4744eae836221b0fb35a9ac69" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Mon May 31 11:20:01 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 04 12:33:03 2023 +0000" }, "message": "bitbang: Extend register_spi_bitbang_master() API with spi data\n\nThis allows the users of register_spi_bitbang_master() API to pass\ntheir spi data into the API, and then the data can go further, into\nregister_spi_master() API.\n\nflashrom-stable: Removed unnecessary if.\n\nChange-Id: I13e83ae74dbc3a3e79c84d1463683d360ff47bc0\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54990\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4d51e07242459f86d00eaf522786695e46ec2511", "tree": "a513666f34cc601d6a9e9bf4f506383dbf69bcb2", "parents": [ "e3c305dfd234503faa23c5491962db8f52d0134c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:56:29 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_imc/sb600spi: Move handle_imc() into amd_imc.c\n\nMove handle_imc() to make it easier to share it with other drivers.\n\nChange-Id: I72dff5feda199e1d258c067e230abdf33c451249\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72575\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e3c305dfd234503faa23c5491962db8f52d0134c", "tree": "b86a019224a05586e18b98eae8ff0c9b51a1c701", "parents": [ "070587892b4af723bf8f1f423d0b26e12e061084" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 21:45:56 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Implement memory-mapped reads\n\nQuery the RomRange2 register for the memory range (usually top below 4G)\nand try to map that. Reads outside this range will still be served via\nthe command engine.\n\nChange-Id: I21aa67d550ccda0f55a9cf3ff14545a881624d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72583\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "735b186eeffb997a957075d7e610b9700b53cbe1", "tree": "1e27f0dc7f2cae492459530df208859221a1d3ca", "parents": [ "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 18:28:45 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Add new driver for AMD SPI100 controllers\n\nStart with a very simple PIO driver. Reads are slow this way, but\nwe can optimize that later. A factor of 2 is possible simply by\naligning the FIFO reads, and another factor of 3 (at least) with\nmemory-mapped reads.\n\nWe override the SPI speed but choose a conservative value to be\non the safe side. Flashrom only supports normal read commands,\nhence we won\u0027t go over 33MHz. Also, if the firmware set a lower\nspeed for normal reads, we use that. We can\u0027t use dual/quad I/O\nwith the SPI command engine, and tests have shown that increasing\nthe SPI speed lifts the read speed only marginally. It seems to\nbe limited by the FIFO reads.\n\nChange-Id: I403d5f103b3ae72f3a91829d562984c54c2e2d00\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72577\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb", "tree": "bf6b57efe06c818f4dbec5d54466930930fa52c0", "parents": [ "dafd51e22b30b7e13e79567c065e55d30c788fa2" ], "author": { "name": "Nicholas Chin", "email": "nic.c3.14@gmail.com", "time": "Sun Oct 23 13:10:31 2022 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 25 00:42:12 2023 +0000" }, "message": "ch347_spi: Add initial support for the WCH CH347\n\nAdd support for the WCH CH347, a high-speed USB to bus converter\nsupporting multiple protocols interfaces including SPI. Currently only\nmode 1 (vendor defined communication interface) is supported, mode 2\n(USB HID communication interface) support will be added later. The code\nis currently hard coded to use CS1 and a SPI clock of 15 MHz, though\nthere are 2 CS lines and 6 other GPIO lines available, as well as a\nconfigurable clock divisor for up to 60MHz operation. Support for these\nwill be exposed through programmer parameters in later commits.\n\nThis currently uses the synchronous libusb API. Performance seems to be\nalright so far, if it becomes an issue I may switch to the asynchronous\nAPI.\n\nTested with a MX25L1606E flash chip\n\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nChange-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "019810f3fd083df5f6f61d19dda2d252709d02fe", "tree": "d9f2f1e6f8e10b6bb1d4b7f56f431f9073942fbc", "parents": [ "6d98aece44f6f3458c79160adf4dddc7f8500378" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:11:24 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Optionally check PCI revision field\n\nWe used to match compatible chipset devices by vendor and device ID\nonly. On some chipsets, e.g. AMD southbridges / SoCs, this is not\nenough, though, as the device IDs are rarely updated.\n\nIn the case of AMD chipsets, we can identify the chipset with the\nrevision ID of the SMBus device. So we add that field to the chipset\nenable list.\n\nChange-Id: I4021cf8e83c605fde4360c274b39481b1e0ff070\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72573\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e7a41e3cec25165b6564b62b6aa64f90bd2dab71", "tree": "a635e566992d379fa1acca5de7fd7517e5c13580", "parents": [ "b0be3200954bebf2431c4d7bd441096f157f621e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Nov 28 17:40:56 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "tree/: Make probe_opcode() flashctx argument const\n\nProbing an opcode generally shouldn\u0027t involve mutating the flashctx\nstate and currently no probe_opcode functions do that.\n\nMake the flashctx arg const so that call sites don\u0027t need to have a\nnon-const pointer.\n\nTested: ninja test\n\nChange-Id: I19e98be50d682de2d2715417f8b7b8c62b871617\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72543\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0cea753aff33b78051febadf8786df83144b5ee7", "tree": "8972ea6cf44e249659ddad7ea3d9aa2dedffc0b6", "parents": [ "ab9f25893f1fa87cbbaf656869e346391eccdb31" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Mon Jul 04 18:21:50 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi: Add function to probe erase command opcode for all spi_master\n\nAdd a field, probe_opcode, to struct spi_master which points to a\nfunction returning a bool by checking if a given command is supported by\nthe programmer in use. This is used for getting a whitelist of commands\nsupported by the programmer, as some programmers like ichspi don\u0027t\nsupport all opcodes.\n\nMost programmers use the default function, which just returns true.\nICHSPI and dummyflasher use their specialized function.\n\nflashrom-stable: Added `.probe_opcode` for `dirtyjtag_spi`, `ich7`.\n\nChange-Id: I6852ef92788221f471a859c879f8aff42558d36d\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72539\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aba3658513da245a61ba59cfab9dba5facdb1054", "tree": "5924d8009154e6b59aa2e10a2f66a263fcf2d358", "parents": [ "00ea3898669aa35bb3f208c1d17f34e3a5c50795" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Sep 05 11:09:28 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "flashrom.c: Move count_max_decode_exceeding() to cli\n\nThe count_max_decode_exceeding() function is only ever called\nwithin the cli_classic logic so move it there and make it\nstatic. This further cleans up the flashrom.c symbol namespace.\n\nChange-Id: If050eab7db8560676c03d5005a2b391313a0d642\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68438\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72362\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b8db74a9b2bc91bb43942f7487c151bd598483b1", "tree": "8e2fdcf8c3bb95124ae1870bd7830fab6f415ee1", "parents": [ "f2a1e073434485d54172e95fc88845a2bd917636" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 00:19:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "internal.c: Retype appropriate variables with bool\n\nUse the bool type instead of an integer for the variables\n`force_laptop`, `not_a_laptop`, `force_boardenable` and\n`force_boardmismatch` since this represents their purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I159d789112d7a778744b59b45133df3928b8445e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66870\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72353\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "63f6a37984cf361229b433343ea9146c57a87f18", "tree": "0ebdaca6bbf8168b6bbb93da3b3be9dcc0336fe3", "parents": [ "ee3fbd7c7c05efbdea2ded8484bcfe96238f0124" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Aug 12 12:56:43 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "parallel.c: Consoldiate parallel master registration logic\n\nThis is analogous to spi.c and opaque.c however parallel\nlogic was previously never consoldiated.\n\nThis free\u0027s up flashrom.c from namespace pollution.\n\nTested: builds with both make and meson.\n\nChange-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72349\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "58015c25eb05fa77966d1c53261a83b56a3cf6b3", "tree": "a1df11881a074c8c66de756f846be9030ce0443a", "parents": [ "e276765eca031c6900d37b22b89e686283f39c91" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Apr 14 13:50:55 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "Introduce an `include` directory for header files\n\nMove all header files to the new `include` directory.\nAdapt include directives and build systems to the new directory.\n\nChange-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf\nSigned-off-by: Felix Singer \u003cfelix.singer@secunet.com\u003e\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72322\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "17affdcd24896b6bb7e73137e9d026ad66a36dfd", "tree": "4d09ab543ef7867c7f6a2fa2910be951d1e2f906", "parents": [ "4925d02f2b128d5fa79a00d434fb9298fcb6180a" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 15 12:55:40 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "NEED_PCI: remove macro\n\nThe NEED_PCI macro is only used to guard prototypes. This is not needed.\n\nChange-Id: I6895b795bc96b3e251700bff4b0054407aac789a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62834\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72320\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "19ce50d3746fb1d9e5238bac49cf88ffe654848e", "tree": "90852ac71da4bc563f5bda33dd2954cd990f1d4b", "parents": [ "6c73e27aa68e0e100f6573cd0910f6f54bff271d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:59:18 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_dev_find() from internal to canonical place\n\nAlso rename to `pcidev_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: Ie21f87699481a84398ca4450b3f03548f0528191\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72310\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6c73e27aa68e0e100f6573cd0910f6f54bff271d", "tree": "1aaa6f7595791fc24ee9601245607786ffd6c66d", "parents": [ "4c39c439cbe3bf1e17ca115a8571e7cfc3d8bec9" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:56:20 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_card_find() from internal to canonical place\n\nAlso rename to `pcidev_card_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: I026bfbecba114411728d4ad1ed8969b469fa7d2d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59279\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72309\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48a946673fa770a9224c2b79a8f8440c51b109ed", "tree": "62f3bd1fee1f4e6cf45d42011d2dcbb435ca028e", "parents": [ "15004ba11d6c3b86c7824bb30a630c81e94cc9a4" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Feb 26 11:36:17 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move scandev_inclass logic from internal to pcidev\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: I1978e178fb73485f1c5c7e732853522847267cee\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "15004ba11d6c3b86c7824bb30a630c81e94cc9a4", "tree": "8b6e88754b57846124a67a8d171d7bfa9647e68b", "parents": [ "d58496b41eec27f52804c0dc6573a8612f2f0ec6" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 13:14:06 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Avoid internal programmer relying on pacc global\n\nMake progress towards the goal of removing pacc from global\nstate as noted in the FIXME of programmer.h\n\nTested: ```sudo ./flashrom -p internal --flash-size\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\n16777216\n```\n\nChange-Id: Id83bfd41f785f907e52a65a6689e8c7016fc1b77\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59275\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72300\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "74b4aa0b15439a2ab2474889a7abed978439757a", "tree": "a3e6d01052b04bbae7c71af7c1148d3619ba1ab1", "parents": [ "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:52:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "physmap: rename to hwaccess_physmap, create own header\n\nLine up physmap with the other hwaccess related code.\n\nChange-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4", "tree": "5432e2d6675b9f389ad95bf47f4e2e7decd5807f", "parents": [ "a065520a7c7eedcca961de1fc891cc0b04e6df77" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:25:49 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess physmap: move x86 msr related code into own files\n\nAllow x86 msr related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nflashrom-stable: Squashed fixup for FreeBSD\n\nChange-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60111\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72266\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a065520a7c7eedcca961de1fc891cc0b04e6df77", "tree": "f7a4c280f6d3114b98a52e147f988c4ae293271b", "parents": [ "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 16:36:05 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move x86 port I/O related code into own files\n\nAllow port I/O related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nChange-Id: I372b4a409f036da766c42bc406b596bc41b0f75a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60110\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72265\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e6953e56ffd5149c721a9bfcae01bf978d8b2d51", "tree": "4811713ce12d2e608852f005aba5631a3bf41d2b", "parents": [ "c63d9184aaef45d5a970f045ae901bf9f7221108" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Thu Aug 26 10:10:32 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "par_master: Add shutdown function in par_master struct\n\nWith this, register_par_master can take care of register_shutdown\nas well, and every par master only needs to call\nregister_par_master instead of calling both register_par_master\nand register_shutdown.\n\nNext patches in the chain convert par masters to use new API.\n\nTested: builds and ninja test\n\nChange-Id: I0fee15d548cdd16678e551eeb351e659812ddf76\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57154\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72232\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1fed9ffe3bf81d7a605c2be9e979b0e0804d28b", "tree": "62c1523995763a4c1705ad8e21141a2033dd2bce", "parents": [ "fd3a225fa747f56402a942c1111db2d379df4421" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Tue Aug 03 14:08:02 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "opaque_master: Add shutdown function in opaque_master struct\n\nWith this, register_opaque_master can take care of register_shutdown\nas well, and every opaque master only needs to call\nregister_opaque_master instead of calling both register_opaque_master\nand register_shutdown.\n\nNext patches in the chain convert opaque masters to use new API.\n\nTested: builds and ninja test from CB:56413\n\nChange-Id: I34183e6bafc787eec54ee4a26b73a40803f3ce99\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56823\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72229\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7783f2f39397cc3fad701f6bc5eaf8fa80e2e3ca", "tree": "e6334627f11526c27e3e1d77da367e7e2caf5e69", "parents": [ "f48ede4eb133f9cd44b3a2a4a98ea821611d74ae" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Mon Jul 05 09:18:06 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "spi_master: Add shutdown function in spi_master struct\n\nWith this, register_spi_master can take care of register_shutdown\nas well, and every spi master only needs to call register_spi_master\ninstead of calling both register_spi_master and register_shutdown.\n\nTesting:\nIn dummyflasher, comment out free(data) in shutdown. Test fails with error:\n../dummyflasher.c:949: note: block 0x55e0727a6e40 allocated here\nERROR: dummy_init_and_shutdown_test_success leaked 1 block(s)\nMeans, shutdown function is invoked for drivers with \"old\" API\n(so, transitioning from old to new API is not breaking anything).\n\nNext patches in the chain converts spi masters to use new API.\n\nTested: builds and ninja test\n\nChange-Id: I2dc80dceca2f8204bcd0dad1f51753d7e79f1af5\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55932\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72226\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "21b20218a6128c1880eceb634101df176b56692d", "tree": "84402bf4e4ac933b023ac6e1c56f4a693ef522bc", "parents": [ "b91a203091fc43824bc57f3c8e2db0bcc311da59" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Thu May 13 12:28:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_opaque_master() API\n\nIt was impossible to register a const struct opaque_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: Id3adb4cf04ae04dbe87ddb96f30871cb5f7c8ff0\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54170\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72202\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b91a203091fc43824bc57f3c8e2db0bcc311da59", "tree": "8fffff062afae6b9ce853c69a6636bc33bcabbbc", "parents": [ "03f3a6d13e8bd62ef84ef6a4a6f21d6fb8b2a7b8" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Fri May 21 09:40:58 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_par_master API\n\nIt was impossible to register a const struct par_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: I95bc92f6c54c5bcdac1c522ca87054aaffed0f40\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54169\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72201\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5e08e3e829e3f736e18cef7b8f4a8929c9e06257", "tree": "cfe9483275582e2ff2a50628824cf8e842c1feef", "parents": [ "6c33185c81f4aab0d048be7c4b68dca1a91800c2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 11 17:38:14 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_spi_master() API\n\nIt was impossible to register a const struct spi_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72179\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e28d8e4e2332054fb4b7f61e8ce03f316e3a63f3", "tree": "dcd1df2c485d8da20c2845e584bd157e0e4f63fb", "parents": [ "6a2ebebfabff9ae72f8f03076b015a6b21bf8b90" ], "author": { "name": "Jean THOMAS", "email": "virgule@jeanthomas.me", "time": "Tue Oct 11 17:54:30 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "dirtyjtag: Add DirtyJTAG programmer\n\nAdd a new programmer driver for the DirtyJTAG project (a USB-JTAG\nfirmware for STM32 MCUs).\n\nSuccessfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103\ndevelopment board and a SST25VF020B SPI flash chip.\n\nChange-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913\nSigned-off-by: Jean THOMAS \u003cvirgule@jeanthomas.me\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67878\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71492\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1ab7d2bb0c4ea7be2e251caa564ab91d27ee7ea", "tree": "905816b92fb3759fcb82767cb94b49d6e0f02594", "parents": [ "8cfc7377ffa880659660b344e97333986aba9130" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 03:03:47 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `laptop_ok` with bool\n\nUse the bool type instead of an integer for the variable `laptop_ok`,\nsince this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I5d9fc3516bc2d29f11b056e35b3e5e324ce93423\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66891\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "980d6b8d712d26711dcd5a71007e4626c7198cd5", "tree": "38e926243e6a10734971066fd1602d373fd04784", "parents": [ "f25447e5724bd8664338b69b12399f101abed76b" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 02:48:15 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `programmer_may_write` with bool\n\nUse the bool type instead of an integer for the variable\n`programmer_may_write`, since this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I69958527ae018a92f1c42734a7990d0c532dee0c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71483\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2ab6bba5602a8a2f7e0a99cc94ccc9fe6a412723", "tree": "65cb4b8a6c7de64b6dbf1a41cc333ac4259831a1", "parents": [ "43040f297e68cd4d826d58f57566581ef902d179" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Jun 24 16:48:09 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "it85spi: EOL support\n\nThis code was originally introduced by ITE for now exceedingly old\nChromebooks. The code has had very little attention to maintain it,\nunlikely tested for a long time and now seems to be just a technical\nburden to the flashrom project.\n\nIf someone is later interested it could be resurrected for reference\nfrom git history. However, it needs quite a bit of work to bring it back\ninto maintainable order.\n\nTested: tree builds under meson+make and unit tests pass.\n\nChange-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378\nOriginal-Reviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71467\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e57d4e49fd2556f0fe267833d35cc57b7e252c06", "tree": "ef260430367f0d2025fd6c5c12c101f37639613e", "parents": [ "672bdcfd4ffeb065b7056042769e3cc512d87c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Mon Jan 03 09:44:29 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Elkhart Lake support\n\nElkhart Lake has a chipset called Mule Creek Canyon which is quite\ncompatible with 300 series chipsets. There are a few differences though,\ne.g. different encoding for the SPI clock values for read and write in\nthe FLCOMP register. In addition Elkhart Lake has a new PCI device ID\nfor the SPI controller which is added, too.\n\nTested: Read and flash complete flash on Siemens MC EHL1\n\nChange-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937", "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744", "parents": [ "cce1e5b8636ebef59dd509680594e17b0a207857" ], "author": { "name": "Michał Żygowski", "email": "michal.zygowski@3mdeb.com", "time": "Wed Jun 16 15:13:54 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cce1e5b8636ebef59dd509680594e17b0a207857", "tree": "5f50e5444c3d46b785af7e086ff60159bdf72250", "parents": [ "fa959bacf06a1db31cc82b5d601cc208faf11859" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Nov 02 20:33:35 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "hwaccess.c: move function declarations from programmer.h to hwaccess.h\n\nMove declarations for functions implemented in hwaccess.c from\nprogrammer.h to hwaccess.h.\n\nChange-Id: I075fd86211c766ae3d5f29c76adbd7c5b9bdbd80\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58865\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71436\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1535db44bdc06e6cf52defc519af86197ca414e5", "tree": "a7dc07bfbbf2236cab7941ebb5e7909fae124de9", "parents": [ "8a03c90f41a6ca79c7bf183ad07e2b30702bfd46" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Mon Jun 14 13:20:09 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer.h: sort programmer entries alphabetically\n\nChange-Id: Ie419eac2719aceb3aea803fac8ce85de294c88e5\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55495\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71387\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "40d3233e17e07f7616702b9968468816f4db9520", "tree": "b6b11594742374e50aee4b6afe45a4492c7fa904", "parents": [ "ab69629daab4c091870b3f7d27f80085a415b286" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Thu Jun 10 15:17:53 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer.h: remove compile guard from programmer drivers\n\nThe definition of external structs doesn\u0027t have to be guarded.\nSee discussion under review.coreboot.org/52946.\n\nChange-Id: I01e6a785269c3e0bd648eeaee217a7a855ab0853\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55387\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71383\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3795c9d43d0b6ea71fb7ec499f6fdbb5e5bf0960", "tree": "95c8c787f2e7010cd2c293767b8ffe94b7f259f1", "parents": [ "84e9c913082ce2d243593e3659ec3a0af22ea9cd" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Jun 01 16:25:52 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "enum programmer: not needed anymore. Remove\n\nChange-Id: I53cdb160616911a4beea6b5e8e56d582621818a4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55124\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71381\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e0e93cf59fe2fb45f1e325e0dcc939cc054cbfa8", "tree": "38f1faaae8d2a12dba5a80bad703e3d2c8d68c9e", "parents": [ "9163b814032c566b224ee8e58742448a99a3b73d" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Jun 01 14:37:12 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_init: use struct programmer_entry*\n\nChange-Id: Iacf0f25abc94a84c5d52c8d69a3e8640817b060a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55121\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71378\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cc853d84ed2f8ecafc1f6daa443f8baa4c871805", "tree": "8e5f3e0b7a75d272a109e20af5aeeeec11dfebf7", "parents": [ "7e1345602641114c8eeb5cfef992bf1da8d7fa6a" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue May 04 15:32:17 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_table: move each entry to the associated programmer source\n\nChange-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71373\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "633d6db1b5718305cf4daf87cf4a93d17bc3821e", "tree": "59ec962a28ab34ea99554db9b44ec804fead7e2d", "parents": [ "bbfacffca88042d7f85d910b732bf88253573c76" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Wed Mar 31 19:09:44 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_table: convert entries to pointers\n\nAllows us to move the individual entries into their respective\ndriver files.\n\nChange-Id: Ifbb0ee4db5a85b1cd2afeafe4dca838579f79878\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52945\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71369\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d0fcce2507d7a5ada93902cc7522ee06e91c4872", "tree": "52643af250240e68608a311a51b54cd8cc4b91fb", "parents": [ "b7076368df57398d36146d0234f924b0be9db881" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Wed May 19 13:53:34 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "programmer_table: add table size constant\n\nMakes the array size known to other compilation units.\n\nChange-Id: Idacb4b7b0dd98af8bc7cbecf567d33daafb4b24d\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55116\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71367\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113", "tree": "5866347a6c5e63477f8e05cc32443085319c2df3", "parents": [ "771bb7952a91722d2d9f100e19b0566f06298126" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 10 17:04:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0b1fb92b5e6e3a057709ab3b82032f81f2b564ec", "tree": "3609203b1b63c9c38c3b32a6e87a4e95344b39f4", "parents": [ "c14e3f6bd806c193741bb17815ad8d5d98b7ee38" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Jan 08 09:08:54 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "programmer: remove unused noop_shutdown function\n\nFunction appears to be vestigial.\n\nflashrom-stable: Squashed fixup\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I1b67223aed8be54b60771aa1b2d498836ed28060\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49631\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71337\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "0a84d0d6950fef06ea0c0b0d220f9a97d2a958f0", "tree": "71dd9f05f2cd069305f7d2cb1877ad5ba9f8ed5d", "parents": [ "3b3fc9344d6cfd29007545826ecaf1e483b4bed4" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Tue Nov 24 18:05:02 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "programmer.h,c: Drop dead noop_chip_writeb() fn\n\nDrop dead code.\n\nTested: `git grep noop_chip_writeb`\n\nChange-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47894\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71331\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "13f90e64821fb8af412c7d692c72d2663dc9ce04", "tree": "9093a2c7001756fb3d5fde006f6fddfbb1664867", "parents": [ "e19a41b5411c1a693ad81e9b138ac7d474bad495" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Jan 06 14:10:52 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "tree/: Drop const from opaque data ptr in master definitions [alt]\n\nThe opaque data pointer need not necessarily have constant\ndata for the life-time of the specific master. This is because\nthe data field purpose is for the master to use as it sees fit\nfor managing its own internal state and therefore we should not\nconstrain this as being RO data at init time.\n\nflashrom-stable:\nAdd cast in bitbang_spi to avoid compiler warning.\n\nChange-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71336\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "324929c3d725ce264b2390525dbc9070f6029cc4", "tree": "73ee656c8bc1933329e4239214e4b0eaaadb36f8", "parents": [ "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Thu Aug 01 19:14:10 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 31 17:25:41 2019 +0000" }, "message": "Add support for STLINK V3 debugger/programmer via its SPI bridge\n\nChange-Id: Icffab87ac8f2c570187ed753ec70f054541873a4\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34661\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2d20d6db39547f013b66230f378ceb8e21fa36e3", "tree": "7816f91833c2540ec74f97fe5de4ad4dd81165e0", "parents": [ "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d" ], "author": { "name": "Miklós Márton", "email": "martonmiklosqdev@gmail.com", "time": "Tue Jan 30 20:20:15 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 14 22:40:21 2019 +0000" }, "message": "Add support for National Instruments USB-845x devices\n\nChange-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549\nSigned-off-by: Miklós Márton \u003cmartonmiklosqdev@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/25683\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1c091d1aebb055149c89f88fd5766ca4e33b7b3e", "tree": "1ca7c754bcaaf1b9e8150af14af58a8a609838bf", "parents": [ "15f539c8c978e002f2b6397a7a74e1af817d5cb3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Mon Aug 12 11:14:14 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 19:02:48 2019 +0000" }, "message": "internal: Fix board vendor and model memory leaks\n\nThe board vendor and model are sometimes specified as arguments during\nan internal flash, so make sure they are freed at the end of\ninitialization.\n\nChange-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nFound-by: Coverity CID 1230664, 1230665\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34846\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "3750986348cb99b8f0d828b73972b545a2f9c878", "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315", "parents": [ "908adf4589d34eaf3bd8395afa52aed8c8887cfd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 14:23:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:15:58 2019 +0000" }, "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "deeac7e41a311a0806af0e65a2ce5c6673f9cf92", "tree": "2ff1082bf9ed049c2863deff9a6d66b6980b1812", "parents": [ "959aafa53eeae4f22766b9d098e5ca952af8c070" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:25:15 2019 +0000" }, "message": "spi: Drop spi_controller type\n\nNot needed anymore. Drop it fast before it encourages anyone to\nviolate layers again!\n\nChange-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33651\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "cb44eb7dad17522f47792dca4fc499310ff7d6f3", "tree": "026822102436ac0dcda8d8d007f16757ad73488b", "parents": [ "712ba3a0659a70c2e93a55d9e194b2fae6db28d1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 13:06:51 2019 +0000" }, "message": "bitbang_spi: Drop bitbang_spi_master_type\n\nIt only existed to make maintenance harder and waste our time.\n\nChange-Id: I7a3b5d9ff1e99d2d4f873c6f19fb318f93762037\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33638\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "dc5af547df8b2f852deb5ddad86bb90ff0fc50c0", "tree": "3b23dcce1e43e520ca0a6db314d6920a89b1f72a", "parents": [ "3d7b1e3b5c04304d3680bd950e7672f6336b01d6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 16:54:59 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 02 16:55:43 2019 +0000" }, "message": "dediprog: Disable 4BA completely\n\nThis is an interim solution. We\u0027ll have to enable 4BA step-by-step for\neach dediprog protocol version.\n\nChange-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30386\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "3578ec6a3d7187438c4093f4bb7ac2bb6d4184cb", "tree": "53c7ccc03fa21dcd4664e6fb1b48a9ec1661e023", "parents": [ "9cecc7e25dc3fe27a801a745410825cfc2cfaac3" ], "author": { "name": "Marc Schink", "email": "flashrom-dev@marcschink.de", "time": "Thu Mar 17 16:23:03 2016 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 05 16:25:04 2019 +0000" }, "message": "Add initial J-Link SPI programmer\n\nTested with SEGGER J-Link EDU, Flasher ARM and flash chip W25Q16.V.\n\nChange-Id: Ie03a054a75457ec9e1cab36ea124bb53b10e8d7e\nSigned-off-by: Marc Schink \u003cflashrom-dev@marcschink.de\u003e\nReviewed-on: https://review.coreboot.org/c/28087\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "1d507a07a919f49e74aa05803bf37919ac95adb1", "tree": "24d460c41877990f4a6724c0e8b4513e2d679daa", "parents": [ "ccfa8f9d9a68b1e4238d2dbbc4e9c8bcf9bae8a6" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Thu Jul 12 11:02:28 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 30 09:53:58 2018 +0000" }, "message": "usbdev: Extract libusb1 device discovery into a separate file\n\nCurrently there is a TODO-like comment in the dediprog driver: \"Might be\nuseful for other USB devices as well\". Act on this comment by collecting\nall the device discovery code for libusb1 devices into a separate file.\n\nChange-Id: Idfcc79371241c2c1dea97faf5e532aa971546a79\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/27443\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "45e91a278cd31019ad6ed5a465661001fbaee065", "tree": "c8cf0b31e69ff5efae8c283369fc67aeab4a6e5c", "parents": [ "455a6fc86e833d1165c68d9dbaef8b0188875bc5" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Mon Jun 04 13:46:29 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:17:13 2018 +0000" }, "message": "programmer: Add Developerbox/CP2104 bit bang driver\n\nThe 96Boards Developerbox (a.k.a. Synquacer E-series) provides a CP2102\ndebug UART with its GPIO pins hooked up to the SPI NOR FLASH. The\ncircuit is intended to provide emergency recovery functions without\nrequiring any additional tools (such as a JTAG or SPI programmer). This\nwas expected to be very slow (and it is) but CP2102 is much cheaper than\na full dual channel USB comms chip.\n\nRead performance is roughly on par with a 2400 baud modem (between 60\nand 70 minutes per megabyte if you prefer) and write performance is 50%\nslower still. The full recovery process, with backup and verification of\n4MB data written takes between 14 and 15 hours. Thus it is only really\npractical as an emergency recovery tool, firmware developers will need\nto use an alternative programmer.\n\nChange-Id: I2547a96c1a2259ad0d52cd4b6ef42261b37cccf3\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/26948\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "b623f403a00a6ce796fe632d4c1ff3fc4f5a5e40", "tree": "a2f753c253a18afe6cb09134b9a15d26eca3233b", "parents": [ "9891b75d96a199d1740fbd7df805abf23ae8f347" ], "author": { "name": "Daniel Thompson", "email": "daniel.thompson@linaro.org", "time": "Tue Jun 05 09:38:19 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 17 21:16:12 2018 +0000" }, "message": "bitbang_spi: Add functions to optimize xfers\n\nOn systems where the overhead of getting/setting pins is much greater\nthan the half period (for example, USB bit banging) it significantly\nboosts performance if we can bang more than one bit at the same time.\nAdd support for setting sck at the same time as mosi or miso activity.\n\nThe speed up varies depending on how much the overhead of\ngetting/setting pins dominates execution time. For a USB bit bang driver\nrunning on a 7th generation Core i5, the time to probe drops from ~9.2\nseconds to ~7.7 seconds when set_clk_set_mosi() is implemented.\n\nChange-Id: Ic3430a9df34844cdfa82e109456be788eaa1789a\nSigned-off-by: Daniel Thompson \u003cdaniel.thompson@linaro.org\u003e\nReviewed-on: https://review.coreboot.org/26946\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Georgi \u003cpgeorgi@google.com\u003e\nReviewed-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b2154e8a1d456875122cbbff2a18e5e1c55ef4d2", "tree": "ee5cf1e29adf35b89d6078ba117638b4009cfd89", "parents": [ "ac01baa073b0f154ffd3ffdc7c9e75987f8b525c" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Sun Jan 14 17:35:33 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 26 10:02:38 2018 +0000" }, "message": "digilent_spi: add a driver for the iCEblink40 development board\n\nThis is driver that supports the Lattice iCE40 evaluation kits. On the\nboard is a SPI flash memory chip labeled ST 25P10VP.\n\nTested to work read/write/erase with \"-p digilent_spi -c M25P10\" or\nwith a patch that resets the part beforehands (in which case it gets\ndetected as a M25P10-A and is way faster due to paged writes).\n\nChange-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23338\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f9a30554803a670f9b95a7794be00f03929d6ecd", "tree": "46da1dafce0c76ab5730540540aaf4093463f551", "parents": [ "291764a70e6d8b212680e311bfb0825abf2b9a2f" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Sat May 23 20:30:30 2015 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Thu May 17 16:49:16 2018 +0000" }, "message": "linux_mtd: Import driver from ChromiumOS\n\nThis imports a series of patches from chromiumos for MTD support.\nThe patches are squashed to ease review and original Change-Ids have\nbeen removed to avoid confusing Gerrit.\n\nThere are a few changes to integrate the code:\n- Conflict resolution\n- Makefile changes\n- Remove file library usage from linux_mtd. We may revisit this and use\n it for other Linux interfaces later on.\n- Switch to using file stream functions for reads and writes.\n\nThis consolidated patch is\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThe first commit\u0027s message is:\nInitial MTD support\n\nThis adds MTD support to flashrom so that we can read, erase, and\nwrite content on a NOR flash chip via MTD.\n\nBUG\u003dchrome-os-partner:40208\nBRANCH\u003dnone\nTEST\u003dread, write, and erase works on Oak\n\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/272983\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 2nd commit message:\n\nlinux_mtd: Fix compilation errors\n\nThis fixes compilation errors from the initial import patch.\n\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\n\nThis is the 3rd commit message:\n\nlinux_mtd: Suppress message if NOR device not found\n\nThis just suppresses a message that might cause confusion for\nunsuspecting users.\n\nBUG\u003dnone\nBRANCH\u003dnone\nTEST\u003dran on veyron_mickey, \"NOR type device not found\" message\nno longer appears under normal circumstances.\nSigned-off-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nReviewed-on: https://chromium-review.googlesource.com/302145\nCommit-Ready: David Hendricks \u003cdhendrix@chromium.org\u003e\nTested-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Shawn N \u003cshawnn@chromium.org\u003e\n\nThis is the 4th commit message:\n\nlinux_mtd: Support for NO_ERASE type devices\n\nSome mtd devices have the MTD_NO_ERASE flag set. This means\nthese devices don\u0027t require an erase to write and might not have\nimplemented an erase function. We should be conservative and skip\nerasing altogether, falling back to performing writes over the whole\nflash.\n\nBUG\u003db:35104688\nTESTED\u003dZaius flash is now written correctly for the 0xff regions.\n\nSigned-off-by: William A. Kennington III \u003cwak@google.com\u003e\nReviewed-on: https://chromium-review.googlesource.com/472128\nCommit-Ready: William Kennington \u003cwak@google.com\u003e\nTested-by: William Kennington \u003cwak@google.com\u003e\nReviewed-by: Brian Norris \u003cbriannorris@chromium.org\u003e\n\nThis is the 5th commit message:\n\nlinux_mtd: do reads in eraseblock-sized chunks\n\nIt\u0027s probably not the best idea to try to do an 8MB read in one syscall.\nTheoretically, this should work; but MTD just relies on the SPI driver\nto deliver the whole read in one transfer, and many SPI drivers haven\u0027t\nbeen tested well with large transfer sizes.\n\nI\u0027d consider this a workaround, but it\u0027s still good to have IMO.\n\nBUG\u003dchrome-os-partner:53215\nTEST\u003dboot kevin; `flashrom --read ...`\nTEST\u003dcheck for performance regression on oak\nBRANCH\u003dnone\n\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/344006\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\n\nThis is the 6th commit message:\n\nlinux_mtd: make read/write loop chunks consistent, and documented\n\nTheoretically, there should be no maximum size for the read() and\nwrite() syscalls on an MTD (well, except for the size of the entire\ndevice). But practical concerns (i.e., bugs) have meant we don\u0027t quite\ndo this.\n\nFor reads:\nBug https://b/35573113 shows that some SPI-based MTD drivers don\u0027t yet\nhandle very large transactions. So we artificially limit this to\nblock-sized chunks.\n\nFor writes:\nIt\u0027s not clear there is a hard limit. Some drivers will already split\nlarge writes into smaller chunks automatically. Others don\u0027t do any\nsplitting. At any rate, using *small* chunks can actually be a problem\nfor some devices (b:35104688), as they get worse performance (doing an\ninternal read/modify/write). This could be fixed in other ways by\nadvertizing their true \"write chunk size\" to user space somehow, but\nthis isn\u0027t so easy.\n\nAs a simpler fix, we can just increase the loop increment to match the\nread loop. Per David, the original implementation (looping over page\nchunks) was just being paranoid.\n\nSo this patch:\n * clarifies comments in linux_mtd_read(), to note that the chunking is\n somewhat of a hack that ideally can be fixed (with bug reference)\n * simplifies the linux_mtd_write() looping to match the structure in\n linux_mtd_read(), including dropping several unnecessary seeks, and\n correcting the error messages (they referred to \"reads\" and had the\n wrong parameters)\n * change linux_mtd_write() to align its chunks to eraseblocks, not page\n sizes\n\nNote that the \"-\u003epage_size\" parameter is still somewhat ill-defined, and\nonly set by the upper layers for \"opaque\" flash. And it\u0027s not actually\nused in this driver now. If we could figure out what we really want to\nuse it for, then we could try to set it appropriately.\n\nBRANCH\u003dnone\nBUG\u003db:35104688\nTEST\u003dvarious flashrom tests on Kevin\nTEST\u003dReading and writing to flash works on our zaius machines over mtd\n\nChange-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599\nSigned-off-by: Brian Norris \u003cbriannorris@chromium.org\u003e\nReviewed-on: https://chromium-review.googlesource.com/505409\nReviewed-by: David Hendricks \u003cdhendrix@chromium.org\u003e\nReviewed-by: Martin Roth \u003cmartinroth@chromium.org\u003e\nReviewed-by: William Kennington \u003cwak@google.com\u003e\nReviewed-on: https://review.coreboot.org/25706\nTested-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Philipp Deppenwiese \u003czaolin.daisuki@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2b5adfb1b656dd6a6efbf45a7a411c87840c5394", "tree": "cfc4bf09d45d4ad59b645c0cadaec9507ba5c152", "parents": [ "25fde40f8594b1c13ba7a4c3a605b96b200a4e11" ], "author": { "name": "Shawn Anastasio", "email": "shawnanastasio@yahoo.com", "time": "Sun Dec 31 00:17:15 2017 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:23:10 2018 +0000" }, "message": "buspirate_spi: Add support for variable serial speeds\n\nThis patch sets the default baud rate for communication between\nthe host device and the Bus Pirate for hardware versions 3.0\nand greater to 2M baud.\n\nIt also introduces the ability to manually set the baud rate via\nthe added \u0027serialspeed\u0027 programmer parameter.\n\nThis is done in two parts. Firstly, the requested serial speed is looked up\nin a table to determine the appropriate clock divisor and the divisor is sent\nto the bus pirate. Then, the system\u0027s baud rate for the selected serial port\nis set using serial.c\u0027s \u0027serialport_config\u0027. This function\u0027s prototype had to\nbe added to programmer.h.\n\nIn testing, using the 2M baud rate was able to significantly decrease\nflash times (down from 20+ minutes to less than 2 minutes for an 8MB flash).\n\nChange-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf\nSigned-off-by: Shawn Anastasio \u003cshawnanastasio@yahoo.com\u003e\nReviewed-on: https://review.coreboot.org/23057\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1cf407b4f8d56035816efaf936a40553441eca46", "tree": "c8e41e1172aaeb567af161a9763521c53073bdc4", "parents": [ "ed098d62d66d91cf7330a37f9b83e303eb7f56d8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 20:18:23 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:14:34 2018 +0000" }, "message": "spi_master: Introduce SPI_MASTER_4BA feature flag\n\nAdd a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises\nprogrammer-side support for 4-byte addresses in generic commands (and\nread/write commands if the master uses the default implementations). Set\nit for all masters that handle commands address-agnostic.\n\nDon\u0027t prefer native 4BA instructions if the master doesn\u0027t support them.\n\nChange-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22421\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a54ceb1dbe76e76ca8701dbda3e5baf011b16d6d", "tree": "f27ce3b104511a8b1598e77858cb42b41cb5e515", "parents": [ "67d71792929f94d4638a3663f2fc19aea4918681" ], "author": { "name": "Youness Alaoui", "email": "kakaroto@kakaroto.homelinux.net", "time": "Wed Jul 26 18:03:36 2017 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 10 15:18:11 2017 +0000" }, "message": "rpci: Use pci_dev struct pointer to avoid API breaks\n\nThe pci_dev structure is never meant to be used as is, but always as a\npointer. By using the struct itself in undo_pci_write_data, we are risking\ndata corruption, or buffer overflows if the structure size changes.\n\nThis is especially apparent on my system where flashrom segfaults\nbecause I compile it with pciutils 3.3.0 and I run it on a system\nwith pciutils 3.5.2. The struture size is different and causes a\nstruct with the wrong size to be sent to the library, with invalid\ninternal field values.\n\nThis has been discovered and discussed in Change ID 18925 [1]\n\n[1] https://review.coreboot.org/#/c/18925/\n\nChange-Id: Icde2e587992ba964d4ff92c33aa659850ba06298\nSigned-off-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/20784\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93c306939b732fb05f6d8a692acc3fca78bc0f9f", "tree": "197478ba299562a8044c7d998c24e365af61b295", "parents": [ "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Mar 20 14:25:09 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:13:59 2017 +0000" }, "message": "chipset_enable: Add support for Intel Skylake / Kabylake\n\nAll publicly known Skylake / Kabylake / Sunrise Point PCH variants\nshare the same register interface [1..6]. Although all SPI configu-\nration is now done through the SPI PCI device 1f.5, we can\u0027t probe\nfor it directly since its PCI vendor and device IDs are usually hid-\nden.\n\nTo work around the hidden IDs, we use another PCI accessor that doesn\u0027t\nrely on the OS seeing the PCI device.\n\nThis handles SPI flashes only. While booting from LPC is still sup-\nported, it seems nobody uses it any more.\n\nSome additional PCI IDs were gathered from driveridentifier.com.\n\nTEST\u003dCompiled with B150 set to NT (instead of BAD) and checked for\n sane register readings.\n\n[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002EN\n Document Number 332995\n\n[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms\n Volume 2 of 2\n Revision 001EN\n Document Number 332996\n\n[3] 7th Generation Intel® Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002\n Document Number 334658\n\n[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms\n Datasheet - Volume 2 of 2\n Revision 002\n Document Number 334659\n\n[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform\n Controller Hub (PCH)\n Datasheet - Volume 1 of 2\n Revision 004EN\n Document Number 332690\n\n[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)\n Datasheet - Volume 2 of 2\n Revision 001EN\n Document Number 332691\n\nChange-Id: I000819aff25fbe9764f33df85f040093b82cd948\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18925\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "560111e2ce506b75b112f0d10b5f9b99f007bfa5", "tree": "d9a568d1b4c092a80c9252a648f7ea7ce79bff01", "parents": [ "512059118e9ff56d2b4f3c324db5e764e288ac68" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 26 12:27:17 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:48:06 2017 +0200" }, "message": "ichspi: Drop `dev` parameter from init functions\n\nIt\u0027s never used and has no clear contract (e.g. will the pointer stay\nvalid beyond the call?).\n\nChange-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19460\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "512059118e9ff56d2b4f3c324db5e764e288ac68", "tree": "7c3c384d1579b467135fd85dd9cfbb88abb4771c", "parents": [ "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 17 17:59:54 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:47:49 2017 +0200" }, "message": "Handle Intel Wildcat Point *LP* like Lynx Point LP\n\nThe subtle difference was ignored when adding these chipsets. The\nintegrated Wildcat Point LP PCH is documented in [1].\n\nI\u0027m not sure how to account for \"Broadwell H\" which seems not publicly\ndocumented. Maybe it\u0027s an unreleased HM9*, in which case the non-LP\npath should be correct.\n\n[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,\n Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor\n Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet\n Revision 004\n Document Number: 330837\n\nChange-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18883\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b4d8a2a64b72d65e447161179279c108709c0ac3", "tree": "6b1d6c7c1756dd716614f43f26f358448b7ba25f", "parents": [ "f84df9a78d35eb458ab19c6dac8a0d5f00013886" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 17 17:19:15 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 25 18:51:46 2017 +0200" }, "message": "hwaccess: Constify `addr` argument of MMIO read functions\n\nChange-Id: I1419241a8332b74103b3921df2c615bdf91346a7\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18881\nTested-by: build bot (Jenkins)\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "441d2a4f33a911e47299c350e321084c59a68ddf", "tree": "22d8dce7176b505e4d34e3c3ba59f2b531434958", "parents": [ "40ba6fd0486b9845a951dbe042b1121687353c1a" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon May 02 11:39:35 2016 +0200" }, "committer": { "name": "Martin Roth", "email": "martinroth@google.com", "time": "Fri Jan 13 17:32:32 2017 +0100" }, "message": "Make image parameter of cb_check_image const\n\nChange-Id: I811b3d6f1710154e055b03d5f27b1a8d9b3c0a43\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/17943\nReviewed-by: Martin Roth \u003cmartinroth@google.com\u003e\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "fdec7475bf9e321a3729d5ba2100e30e110870ea", "tree": "fa61a001405821df55486cd6d8a0058ccc9127f1", "parents": [ "f31fe841d78a01cd85b86b5fd9cb7e5bb64dfc4c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Feb 22 08:59:27 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Feb 22 08:59:27 2016 +0000" }, "message": "dediprog: use ordinary USB devs array\n\nEven though there is currently only one USB device ID in the wild using our\nstandard way to define the devices creates nicer output for -L and -z.\n\nCorresponding to flashrom svn r1942.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "f31fe841d78a01cd85b86b5fd9cb7e5bb64dfc4c", "tree": "9f953f0e2f4f36c96cf16214e5ce303b7ea7b777", "parents": [ "2a0feae6997c987899d7fb165a4d3d2175b2c8f5" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Feb 22 08:59:15 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Feb 22 08:59:15 2016 +0000" }, "message": "pickit2_spi: use ordinary USB devs array\n\nEven though there is currently only one USB device ID in the wild using our\nstandard way to define the devices creates nicer output for -L and -z.\n\nCorresponding to flashrom svn r1941.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "0870b02516ec9ef90364c3feeb5d0d7dc9c0e785", "tree": "016c2ebed9c5ee0cc0f5e5d13b5e1859f4ca0258", "parents": [ "e49edbb8989abe206d144e4ae7bc9f7ae636bada" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Sun Jan 31 22:10:29 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jan 31 22:10:29 2016 +0000" }, "message": "Add support for WCH CH341A as an SPI programmer\n\nCorresponding to flashrom svn r1921.\n\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Urja Rannikko \u003curjaman@gmail.com\u003e\n" }, { "commit": "23e10b87801c22f34642895de8b0b726265eb016", "tree": "2d62c23191801afaecbf98925effb8b8c7a44ab6", "parents": [ "c2644a3fc14088a2535c05edbd56c041b3a7370d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jan 23 16:16:49 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jan 23 16:16:49 2016 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 24\n\nTested mainboards:\nOK:\n - ASRock G31M-GS\n Reported by Александр Трубицын\n - ASRock G41M-VS3\n Reported by Александр Трубицын\n - ASRock N68C-S UCC\n Reported by Alexey Belyaev\n - ASRock AMCP7AION-HT (ION 330HT(-BD))\n Reported by Stefan Tauner\n - ASUS P5K SE\n Reported by Александр Трубицын\n - ASUS P5KPL-VM\n Reported by Marin Vlah\n - ASUS RAMPAGE III GENE\n Reported by stevessss on IRC\n - GIGABYTE GA-945GM-S2\n Reported by Александр Трубицын\n - GIGABYTE GA-945GCM-S2 (rev. 3.0)\n Reported by Александр Трубицын\n - GIGABYTE GA-965P-S3\n Reported by Александр Трубицын\n - GIGABYTE GA-EG43M-S2H\n Reported by Александр Трубицын\n - GIGABYTE GA-EP31-DS3L (rev. 1.0)\n Reported by Александр Трубицын\n - GIGABYTE GA-G33M-S2\n Reported by Александр Трубицын\n - GIGABYTE GA-G33M-S2L\n Reported by Александр Трубицын\n - GIGABYTE GA-H55M-S2\n Reported by Александр Трубицын\n - GIGABYTE GA-J1900N-D3V\n Reported by Marcos Truchado and Guillermo von Hünefeld\n - GIGABYTE GA-K8NS\n Reported by nicolae788\n - GIGABYTE GA-M56S-S3\n Reported by Estevo Paz Freire\n - GIGABYTE GA-P31-DS3L\n Reported by Александр Трубицын\n - GIGABYTE GA-P31-S3G\n Reported by Александр Трубицын\n - MSI MS-7336\n Reported by Benjamin Bellec\n - MSI X79A-GD45 (8D) (MS-7760)\"\n Reported by mortehu on IRC\n - Supermicro A1SAi-2550F\n Reported by Bernard Grymonpon\n - Supermicro X7DWT\n Reported by Steven Stremciuc\n\nLaptop:\n - ASUS U38N\n Reported by Ultra on IRC\n - Dell Latitude D630\n Reported by Márton Miklós\n - Fujitsu Amilo Xi 3650\n Reported by Elmar Stellnberger\n - Lenovo T400 (whitelisting only)\n\nChipsets:\n - Mark 8086:1f38 (Intel Avoton/Rangeley) as tested\n Reported by Jeremy Porter and Bernard Grymonpon\n - Add Intel Sunrise Point IDs but no support yet.\n\nFlash chips:\n - Atmel AT45DB321D to PREW (+PREW)\n Reported by The Raven\n - Eon EN25QH32 to PREW (+PREW)\n Reported by Josua Mayer\n - Eon EN25QH64 to PREW (+EW)\n Reported by David s. Alessio\n - GigaDevice GD25LQ64(B) to PREW (+PREW)\n Reported by Greg Tippit\n - Intel 28F001BN/BX-T to PREW (+EW)\n Reported by Lu Xie\n - Micron M25P10-A to PREW (+W)\n Reported by the Raven\n - Micron M25PE40\n Reported by David Wood\n - Micron N25Q128..3E to PREW (+PREW)\n Reported by Miklós Márton\n - Macronix MX25L3273E to PREW (+PREW)\n Reported by Roklobsta on IRC\n - Macronix MX23L6454 to PR (+PR)\n Reported by Steven Honeyman\n - Macronix MX25U6435E/F to PREW (+PREW)\n Reported by Marcos Truchado and Guillermo von Hünefeld\n - PMC Pm25LQ032C to PREW (+EW)\n Reported by Dirk Knop\n - Spansion S25FL016A to PREW (+EW)\n Reported by Márton Miklós\n - Spansion S25FL128S......0 to PREW (+PREW)\n Reported by Jim Houston\n - Spansion S25FL204K to PR (+PR)\n Reported by Thomas Debrunner\n - SST SST49LF016C to PREW (+EW)\n Reported by Steven Stremciuc\n - SST SST39VF040 to PREW (+PREW)\n Reported by Xavier Bourgeois\n - SST SST49LF040B to PREW (+EW)\n Reported by Rikard Åhlund\n - ST M25P10-A to PREW (+W)\n Reported by Martijn Schiedon\n - Winbond W39V040FA to PREW (+EW)\n Reported by Евгений Черкашин\n - Winbond W39V080FA to PREW (+EW)\n Reported by protagonist0 on IRC\n - Winbond W25Q80.W to PREW (+PREW)\n Reported by Miklós Márton\n - Winbond W25X64 to PREW (+REW)\n Reported by Johannes Krampf and Manuel Dejonghe\n - Fix ID of AMIC A25LQ64\n Reported by Roman Titov\n - Fix page size of Spansion S25FL129P......1\n Copy and paste error from the 128S uniform 256kB variant, probably.\n - Add Micron/Numonyx phase-change memory IDs\n\nMiscellaneous:\n - Detect Android target OS.\n No changes are required to build flashrom (excluding programmers\n with NEED_PCI) on Android.\n - Update rayerspi (spipgm) URL\n - Fix max_data_write handling of at45db.\n - Minor refinement of the README\n - Mark board enable for the GA-K8NS variants as tested.\n Tested by \"nicolae788\" on a board with socket 754.\n - Mark \"Multi-system\" chassis as non-laptop case.\n - Remove W836xx log requests.\n We got enough (and no one is looking at them for the time being anyway).\n - serprog: improve invalid reply error message, contributed by Urja Rannikko.\n - Remove default include paths for MinGW.\n - Disable implicit rules in the Makefile because we don\u0027t need them and they\n just make the build (imperceptibly) slower.\n - Enable our own strnlen() implementation not only on DJGPP but also if\n HAVE_STRNLEN is not defined. This is needed to get older BSDs\n (e.g. NetBSD 6.0, FreeBSD \u003c 8.0) to work.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1917.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "c2644a3fc14088a2535c05edbd56c041b3a7370d", "tree": "1d1e9e3e05d2fa18a228ef22ef0f99873c767ab4", "parents": [ "a3712817a2eff0173e664162fc441ee7846f6ea0" ], "author": { "name": "Joseph C. Lehner", "email": "joseph.c.lehner@gmail.com", "time": "Sat Jan 16 23:45:25 2016 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jan 16 23:45:25 2016 +0000" }, "message": "Add atapromise programmer\n\nSupported controllers are Promise PDC20262 (FastTrak66/Ultra66),\nPDC20265 (FastTrak100 Lite/Ultra100), PDC20267 (FastTrak100/Ultra100).\nAt least the Ultra100 only has address lines A0-A14 wired up, limiting\naddressable chip size to 32 kB. The flash chips mounted on those\ncontrollers usually is 128 kB, i.e. parts of the flash chip are\ninaccessible. As a workaround, the driver implicitly truncates the\nsize of all flash chips to 32 kB. Works well for the factory installed\nflash.\nDo NOT use as a generic programmer for chips \u003e32 kB.\n\nCorresponding to flashrom svn r1916.\n\nSigned-off-by: Joseph C. Lehner \u003cjoseph.c.lehner@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Urja Rannikko \u003curjaman@gmail.com\u003e\n" }, { "commit": "72587f85ec0f85719c163905933e31a946f54bdf", "tree": "65b772847d7325b0739a7a74a455644cca8db997", "parents": [ "631bb021359e8bc85c40d4700ca276667c0f97ed" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Jan 04 03:05:15 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Jan 04 03:05:15 2016 +0000" }, "message": "serprog: allow to omit specifying a baud rate\n\nOn USB-based serial connections (VCP) the requested baud rate usually\ndoes not matter (much). Remove the arbitrary restriction and use whatever\ndefault values the OS/hardware provides.\n\nCorresponding to flashrom svn r1907.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Urja Rannikko \u003curjaman@gmail.com\u003e\n" }, { "commit": "0b4ffd58aaca065c55a7933df286dbe275d9ebd7", "tree": "2efb5b97da732f7bb35990a4eb86cd1bf59f13e2", "parents": [ "25e9f40e21e715e4ee6183a42c8521406f91b258" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Mon Jun 29 23:24:23 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Jun 29 23:24:23 2015 +0000" }, "message": "serprog: Fix FWH/LPC by implementing serprog_map\n\nThe serprog protocol does only transmit 24 bit-wide address and ignores the\ntop 8 bit. This is fine as long as the underlying hardware ignores the latter\nanyway (which is the case for parallel chips that even lack the respective pins).\nFWH/LPC chips, however, operate on a full 32-bit (LPC) or 28-bit (FWH) address\nspace and would fail with the fallback mapping to NULL.\n\nCorresponding to flashrom svn r1895.\n\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "66e554bc88a29ec6bc55c86320799c31b5b0e6c1", "tree": "597dd6c02ecd223e56d3088682e1c5314409af1f", "parents": [ "5673450316b0624f3b0a763babdcaf9f13fde12c" ], "author": { "name": "Justin Chevrier", "email": "jchevrier@gmail.com", "time": "Sun Feb 08 21:58:10 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:58:10 2015 +0000" }, "message": "Add support for the Microchip PICkit2 as an SPI programmer\n\nThis patch was inspired by the code in AVRDude (open source Atmel AVR\nprogrammer) to support the PICkit2 written by Doug Brown [1]. The\nDediprog code in flashrom was used as the template for this code with\nsome reference to the ft2232 code as well.\n\n[1] - https://github.com/steve-m/avrdude/blob/master/pickit2.c\n\nCorresponding to flashrom svn r1881.\n\nSigned-off-by: Justin Chevrier \u003cjchevrier@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5c316f954941241ed75a1f00f00bf1bff318488a", "tree": "ce836bcb29d7d9da86ee583a88236b020985ba36", "parents": [ "dc627931848ed6af40be4f7d5bdb8e33d28b8333" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 22\n\nTested mainboards:\nOK:\n - AOpen UK79G-1394 (used in EZ18 barebones)\n Reported by Lawrence Gough\n - ASUS M4N78 SE\n Reported by Dima Veselov\n - ASUS P5LD2-VM\n Mark board enable as tested (reported by Dima Veselov)\n - GIGABYTE GA-970A-UD3P (rev. 2.0)\n Reported by trucmar on IRC\n - GIGABYTE GA-990FXA-UD3 (rev. 4.0)\n Reported by ROKO__ on IRC\n - GIGABYTE GA-H77-DS3H (rev. 1.1)\n Reported by Evgeniy Edigarev\n - GIGABYTE GA-P55-USB3 (rev. 2.0)\n Reported by Måns Thörnqvist\n - MSI MS-7817 (H81M-E33)\n Reported by Igor Kolker\n\nChipsets:\n - Marked Intel Bay Trail (0x0f1c) as tested OK\n Reported by Antonio Ospite\n - Refine Intel IDs\n * Add IDs for Braswell\n * Add IDs for 9 Series PCHs (e.g. H97, Z97)\n * Rename Wellsburg devices slightly\n\nFlash chips:\n - Atmel AT25DF041A to PREW (+PREW)\n Reported by Tai-hwa Liang\n - Atmel AT26DF161 to PREW (+EW)\n Reported by Steve Shenton\n - Atmel AT45DB011D to PREW (+PREW)\n Reported by The Raven\n - Atmel AT45DB642D to PREW (+PREW)\n Reported by Mahesh Mokal\n - Eon EN25F32 to PREW (+PREW)\n Reported by Arman Khodabande\n - Eon EN25F40 to PREW (+REW)\n Reported by Jerrad Pierce\n - Eon EN25QH16 to PREW (+EW)\n Reported by Ben Johnson\n - GigaDevice GD25Q20(B) to PREW (+PREW)\n Reported by Gilles Aurejac\n - Macronix MX25U6435E/F to PR (+PR)\n Reported by Matt Taggart\n - PMC Pm25LV512(A) to PREW (+PREW)\n Reported by The Raven\n - SST SST39VF020 to PREW (+PREW)\n Reported by Urja Rannikko\n - Winbond W25Q40.V to PREW (+EW)\n Reported by Torben Nielsen\n - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).\n - Add MX25L6465E variant.\n - There was never a MX25L12805 AFAICT.\n - Split MX25L12805 from models with the same ID but an additional 32 kB\n eraser: MX25L12835F/MX25L12845E/MX25L12865E.\n - Add a bunch of ST parallel NOR flash chip IDs.\n\nMiscellaneous:\n - Whitelist ThinkPad X200.\n - Constify master parameter of register_master().\n - Remove FEATURE_BYTEWRITES because it was never used at all.\n - Refine hwseq messages and make them less prominent.\n - Fix the yet unused PRIxCHIPADDR format string thingy.\n - Fix copy\u0026paste error in spi_prettyprint_status_register_bp().\n Spotted by Pablo Cases.\n - Add an additional SMBus controller revision to identify another Yangtze\n model. Thanks to Dan Christensen for reporting this issue.\n - dediprog: add missing include for stdlib.h.\n This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.\n - Remove references to struct pci_filter from programmer.h.\n It is only needed in internal.c where it has a complete type. Having\n it in programmer.h provokes a warning by some old versions of gcc.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1879.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "b0eee9b8d649efc3db9a6c5f333b0fff5204a979", "tree": "fcba10fdf1451557f3bc58de6f39d669e5106c46", "parents": [ "be62d3fc07194ec13f091aa06beff0a032f1a418" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jan 10 09:32:50 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jan 10 09:32:50 2015 +0000" }, "message": "Unify target OS and CPU architecture checks\n\nWe do CPU architecture checks once for the makefile in arch.h and\nonce for HW access abstraction in hwaccess.c. This patch unifies\nrelated files so that they can share the checks to improve\nmaintainability and reduce the chance of inconsistencies.\nFurthermore, it refines some of the definitions, which\n - adds \"support\" for AARCH64 and PPC64,\n - adds big-endian handling on arm as well as LE handling on PPC64,\n - fixes compilation of internal.c on AARCH64 and PPC64.\n\nAdditionally, this patch continues to unify all OS checks in\nflashrom by adding a new helper macro IS_WINDOWS.\n\nThe old header file for architecture checking is renamed to platform.h\nto reflect its broader scope and all new macros are add in there.\n\nCorresponding to flashrom svn r1864.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "80e647158800d927c776d1278d8817f0ed8f17cd", "tree": "b5b0f8f09acac5f114c80ac1ed2ff316c7c0eb12", "parents": [ "5859ced80f17217e7e829b61b02bb18b66b4f8e4" ], "author": { "name": "Alexandre Boeglin", "email": "alex@boeglin.org", "time": "Sat Dec 20 20:25:19 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 20 20:25:19 2014 +0000" }, "message": "Add support for the MSTAR I2C ISP protocol\n\nBasically, among other chips, MSTAR manufactures SoCs that equip TV sets\nand computer screens, and it seems that all of their products use the\nsame in-system programming protocol. Basically, they use the DDC channel\nof VGA or DVI connectors, which is actually an I2C bus, to encapsulate\nSPI frames (the flash chip is connected to the SoC through an SPI bus).\n\nI wrote this patch since the screen I bought had a software bug, and the\nmanufacturer only released a new firmware binary, but no tool or\ninstructions on flashing it.\n\nMore details can be found here:\nhttp://boeglin.org/blog/index.php?entry\u003dFlashing-a-BenQ-Z-series-for-free(dom)\n\nI only read code from Linux kernel archives published by Acer to figure\nout the protocol (for a touchscreen controller and an NFC chip, both by\nMSTAR, that share the same ISP protocol), so I don\u0027t think there are\nany legal problems with it.\n\nCompilation is currently disabled by default in the Makefile.\nIf in doubt, additional Makefile bugs were added by Stefan.\n\nCorresponding to flashrom svn r1860.\n\nSigned-off-by: Alexandre Boeglin \u003calex@boeglin.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "823096e5270dc7ccd8b0315377428556d1987dcf", "tree": "53fbf8653802401b1a35a6046aa8c54e0f8b0d1a", "parents": [ "4095ed797f87c92b52e15d9f6fdc0b895c414cc9" ], "author": { "name": "Duncan Laurie", "email": "dlaurie@chromium.org", "time": "Wed Aug 20 15:39:38 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:38 2014 +0000" }, "message": "Add support for Intel Wildcat Point PCH\n\nThe Wildcat Point PCH can be paired with Broadwell or Haswell.\nThis patch was essentially backported from ChromiumOS commit 9bd2af8.\n\nCorresponding to flashrom svn r1845.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "4095ed797f87c92b52e15d9f6fdc0b895c414cc9", "tree": "deaca4de25e5bafc24fe0a48a401a8d4f062a170", "parents": [ "2ba9f6ebe56b208a1fb0b0ce5edf81097a0158be" ], "author": { "name": "Duncan Laurie", "email": "dlaurie@chromium.org", "time": "Wed Aug 20 15:39:32 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:32 2014 +0000" }, "message": "Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton\n\nThe core of this patch to support Bay Trail originally came from the\nChromiumos flashrom repo and was modified by Sage to support the\nRangeley/Avoton parts as well.\nBecause that was not complicated enough already Stefan Tauner refactored\nand refined everything. Bay Trail seems to be the first Atom SoC able to\nsupport hwseq. No SPI Programming Guide could be obtained so it is\nhandled similarly to Lynx Point which seems to be its nearest relative.\n\nCorresponding to flashrom svn r1844.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Martin Roth \u003cgaumless@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Marc Jones \u003cmarcj303@gmail.com\u003e\nTested-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Thomas Reardon \u003cthomas_reardon@hotmail.com\u003e\nTested-by: Wen Wang \u003cwen.wang@adiengineering.com\u003e\nAcked-by: Marc Jones \u003cmarcj303@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "9e3a6984da1bb38af37ce4bb54af8f7475b7c766", "tree": "409e4bf78b9d726f6aa413933987055b6a1c0439", "parents": [ "9b32de94f5104cb7fa12816b7fa561b804df6ed8" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Aug 15 17:17:59 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Aug 15 17:17:59 2014 +0000" }, "message": "Refine handling chips that exceed maximum programmer sizes\n\n - Change check_max_decode() to return the number of (common) busses\n where the flash chip exceeds the supported size of the programmer.\n - Refine its signature to use a flashctx pointer only.\n - Move CLI-related bits to cli_classic.c.\n - Rename check_max_decode() to count_max_decode_exceedings() to\n better reflect what it (now) really does.\n - Refine the messages printed by the caller to better integrate with the new\n setup, and simplify them.\n\nCorresponding to flashrom svn r1842.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "9b32de94f5104cb7fa12816b7fa561b804df6ed8", "tree": "9501e463b76abf831d62bfd1a9a9ac2f8939476e", "parents": [ "a8cf3620a42ca5927253822a813e3fbae1d6e7bf" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Aug 08 23:52:33 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Aug 08 23:52:33 2014 +0000" }, "message": "Refactor some CLI-relevant parts\n\nBegin to move functions that clearly belong to the (command line)\nuser interface out of flashrom\u0027s core files like flashrom.c.\n\n - Refine messages within check_chip_supported(), rename it to\n print_chip_support_status() and move it to newly created cli_common.c.\n - Move flashbuses_to_text() to cli_common.c as well.\n - Move global verbosity variables to cli_output.c.\n\nCorresponding to flashrom svn r1841.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "2a41f0a2c0daeb0ee2a38a252ab96135d70a6b81", "tree": "9d9c28c7560f4947c49e54e62c1f3a04f07aec45", "parents": [ "a5bcbceb581f27cfc0055369d3dd9cfd1ae00bfa" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Mon Jul 28 20:35:21 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Jul 28 20:35:21 2014 +0000" }, "message": "Add new programmer for SPI EEPROMs attached to Intel 82580 NICs\n\nThis patch lets you read and write the EEPROM on 82580-based gigabit NIC\ncards. So far it has been tested on copper NICs only, but other variants\nemploying this controller should work too.\nIt is a nice substitution for the official eeupdate tool.\n\nSpeed is quite decent: less than 4 seconds for erases or writes of 32 kB.\n\nCorresponding to flashrom svn r1832.\n\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a5bcbceb581f27cfc0055369d3dd9cfd1ae00bfa", "tree": "5daecd880a16b7011be28e064fb7550f3e6b7e58", "parents": [ "82b6ec1df30d3fca55547f230c76718d6e613b2a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "message": "Rename programmer registration functions\n\nRegister_programmer suggests that we register a programmer. However,\nthat function registers a master for a given bus type, and a programmer\nmay support multiple masters (e.g. SPI, FWH). Rename a few other\nfunctions to be more consistent.\n\nCorresponding to flashrom svn r1831.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "600576b43d7f76adc49913a7a7dd21e318b063cf", "tree": "58dda54c79c37a339ce3cfbdf6d03fdbf413b81c", "parents": [ "7ba3d6ce160ed46913a63283e0b8822b80985044" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jun 12 22:57:36 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jun 12 22:57:36 2014 +0000" }, "message": "Add selfcheck_board_enables()\n\nCheck for NULL termination of the array, that each board has the two\nmain PCI ID sets defined, that coreboot vendor and model fields are either\nboth set or unset, and that at least either an enable function or a max\ndecode size is available.\n\nCorresponding to flashrom svn r1821.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "0ccec8f21228fab9e5e57c9392f6feafbf296ef1", "tree": "acd2e0d426a3ec0b7829df72f6a0cbb8a9c232e2", "parents": [ "72d42f87a9a01a1d27fba593ce4569331e079cbe" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 01 23:49:03 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 01 23:49:03 2014 +0000" }, "message": "Move global io_base_addr into compilation units\n\nCorresponding to flashrom svn r1813.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "72d42f87a9a01a1d27fba593ce4569331e079cbe", "tree": "b5850f2c7961641b0fbb0447be298ded5c3db3c6", "parents": [ "4f094750fa38f442d575f9cd2f7ce144ae3218cb" ], "author": { "name": "Kyösti Mälkki", "email": "kyosti.malkki@gmail.com", "time": "Sun Jun 01 23:48:31 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 01 23:48:31 2014 +0000" }, "message": "Add IT8212F as programmer\n\nThis PCI PATA controller can use 3V parallel flash up to 128 kB.\n\nMy card was identified as:\n PCI 1283:8212, subsystem 1283:0001.\n\nand labelled as:\n Innovision Multimedia LTD.\n EIO ATA133 RAID\n (DM-8401 Ver A)\n\nThis particular card did not require setting of any GPIO signals to\nenable flash writing. My card has Pm39LV512 in PLCC32 package without\nsocket.\n\nRebased by Stefan (automatic cleanup, some PCI changes, changed\nenable bit handling). Committed with test state NT because the\nrebased version was not tested on real hardware (yet).\n\nCorresponding to flashrom svn r1812.\n\nSigned-off-by: Kyösti Mälkki \u003ckyosti.malkki@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "7f0f3fab4531c975245bf8f3553ff380ac802fc7", "tree": "1d2beb0dcc9fa121e7cfffc7e84d5c367cce9203", "parents": [ "f2756fa240ccf5b2fe888c4abc9c4cdf33932e3a" ], "author": { "name": "Jonathan Kollasch", "email": "jakllsch@kollasch.net", "time": "Sun Jun 01 10:26:23 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Jun 01 10:26:23 2014 +0000" }, "message": "Add VIA VT6421A LPC programmer driver\n\nDue to the mysterious address handling of this chip the user can specify\na base address with the offset parameter, e.g.:\nflashrom -p atavia:offset\u003d0xFFF00000\n\nThanks to Idwer Vollering for his iterative testing of this code, as well as to\nMartijn Bastiaan who did the last tests before merging.\n\nCorresponding to flashrom svn r1809.\n\nSigned-off-by: Jonathan Kollasch \u003cjakllsch@kollasch.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "31402ee6872ce2880f7fe98dc933e5bc73e8613c", "tree": "e86b4bb62924ef524900d377dd3cc908a53a992e", "parents": [ "d5b2aef69d4f4ab5e2ea69e3244e8e8e9a5221b9" ], "author": { "name": "Wei Hu", "email": "wei@aristanetworks.com", "time": "Fri May 16 21:39:33 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 16 21:39:33 2014 +0000" }, "message": "sbxxx: Add support for new AMD SPI controller\n\nThis patch adds support for the \"SPI 100\" SPI engine in Yangtze FCHs\n(found in Kabini and Temash).\n\nTested reading/writing on ASRock IMB-A180 and PC Engines\u0027 APU board.\n\nCorresponding to flashrom svn r1794.\n\nSigned-off-by: Wei Hu \u003cwei@aristanetworks.com\u003e\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f20b7beff054eb316088d590094d9efbc68dbee1", "tree": "6324be451385c9f9cea27381f35f300fbaa7f454", "parents": [ "20da4aa82cc11f25a6a4a52fd2bed219e6e1d829" ], "author": { "name": "Mark Marshall", "email": "mark.marshall@omicron.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "message": "Add \u0027const\u0027 keyword to chip write and other function prototypes\n\nCorresponding to flashrom svn r1789.\n\nInspired by and mostly based on a patch\nSigned-off-by: Mark Marshall \u003cmark.marshall@omicron.at\u003e\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f80419c75a344b303275e380add3b8cb750bab9d", "tree": "124a732dd0d8c171b28649986c716af0477ca746", "parents": [ "b66ed84d193b8c0eddf5d946c6d2d94a8e8360ee" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 02 15:41:42 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 02 15:41:42 2014 +0000" }, "message": "Make delay values unsigned\n\nThere is no reason for negative delays in our use cases:\n - We don\u0027t need it (to work around any quirks).\n - sleep() (POSIX) uses an unsigned argument.\n - usleep() (POSIX) uses an unsigned argument.\n - Sleep() (Windows) uses an unsigned argument.\n\nChange all callees as well (without any complications).\n\nCorresponding to flashrom svn r1782.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" } ], "next": "43eac0394591a4f662d2793e8405226c3c69fdc4" }