)]}' { "log": [ { "commit": "5455786bfb4b09af11f4354a6bb4842d37d78419", "tree": "4444295adb9d0e6f9e13e08a16bc5c88a0b14352", "parents": [ "c3b02dce51aad2766512d1939a1b7447c2d526b8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 15 12:01:04 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 08 19:56:50 2023 +0000" }, "message": "spi95: Avoid automatic probing\n\nIt turned out that the read ID command for the ST/M95 family (0x83)\nis a write command for AT45DB chips. We\u0027ll tag respective chips as\nusing a SPI95 command set, like we did for EDI, to avoid automatic\nprobing.\n\nChange-Id: Ibdf364424ac9cd8a734507a05fe769f008f8178e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/75218\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "a2eaf4aa0166e107b3a3f9c50040d1b983cf4622", "tree": "0b0d4dc14d8898f4456705ab968d66e9a85cdc29", "parents": [ "07dd1219ff158a63dc9fa2d0f32f91bb03d8722e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 22:56:53 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 16 21:49:40 2023 +0000" }, "message": "flashchips: Add entries for SST26VF016/032\n\nThey share a datasheet and look similar to the A/B variants that\nalready had entries but different IDs.\n\nChange-Id: I62ca123de917dc5c4766f3cf00a11d05b3befd4f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73043\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "111c380b2502df035057806fb727a724b18c815f", "tree": "c552fa6497313652798c34a16f41c2d3e56c6cd3", "parents": [ "b8ee2d63ae9f67bee7d6a2cab11de88128021e51" ], "author": { "name": "Kapil Porwal", "email": "kapilporwal@google.com", "time": "Fri Dec 09 19:41:27 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 06 23:36:26 2023 +0000" }, "message": "flashchips.c: Add reg_bits for W25Q256JW_DTR\n\nAdd reg_bits for W25Q256JW_DTR as per the datasheet.\n\nw/o this patch:\nFailed to get WP status: WP operations are not implemented for this chip\n\nw/ this patch:\nflashrom -p internal --wp-range 0x0,0x2000000\nflashrom -p internal --wp-enable\nflashrom -p internal --wp-status\nflashrom -p internal -E \u003c---- failed to erase the flash as WP (which is\nexpected)\n\nSigned-off-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nChange-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549\nOriginal-Reviewed-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73481\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "48dc090ae357bae82cdac2449fce8e7aad545922", "tree": "4fce1e7327fa5bd620213fdcc53fa62f39b427c6", "parents": [ "1e56360b267056e347b786349e6ec72e8f7216bc" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 05 17:20:55 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 06 23:36:26 2023 +0000" }, "message": "flashchips: Drop FEATURE_4BA_WREN from MT25QU128\n\nThe chip is too small for that.\n\nChange-Id: I4672d6d0d1802490b200db475d6fa464772018d7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73475\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1e56360b267056e347b786349e6ec72e8f7216bc", "tree": "dfeb62f02b184503719463de61396a95b88bd191", "parents": [ "5d5b12201bfc7a56d7ece9a90632a960aa8393d3" ], "author": { "name": "Rick Altherr", "email": "kc8apf@kc8apf.net", "time": "Thu Dec 22 10:25:34 2022 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 06 23:36:26 2023 +0000" }, "message": "flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as tested\n\nUsing both a Dediprog SF100 and a Bus Pirate, read and erase works\ncorrectly on a MT25QL128 but writes were failing to take effect.\nCurrently, the entry in flashchips.c indicates that this device supports\n4-byte addressing. Micron\u0027s datasheet indicates that it does not.\nAfter removing FEATURE_4BA_WREN from feature_bits, both SF100 and\nBus Pirate were able to successfully read, erase, and write a\nMT25QL128 so also marking as tested.\n\nChange-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab\nSigned-off-by: Rick Altherr \u003ckc8apf@kc8apf.net\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73474\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a97e353df0b3bb514502b7684b0171af75ff351e", "tree": "15fb98340333226c91a5a08780465672f7cb3195", "parents": [ "f5bffd99bd7737b77e51b3e1bdb3392355b10ff6" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Dec 16 15:41:05 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:58 2022 +0100" }, "message": "flashchips.c: Mark W25Q128.V WP as tested\n\nTested: `-p internal --wp-status`.\n\nChange-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71240\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f5bffd99bd7737b77e51b3e1bdb3392355b10ff6", "tree": "294477f73e4d021f19df9c55ce3758563640e2c5", "parents": [ "3c9bdb97190cbeaf383633d52a57810a2361dccc" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Dec 14 12:30:43 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:58 2022 +0100" }, "message": "flashchips: Add WP settings for Flash Chip `W25Q512NW`\n\nThis patch adds WP register bits and decode range for Flash\nChip `W25Q512NW`.\n\nTested: Able to flash AP FW, wp-enable/disable on Google/rex device\nwhich has flash chip `W25Q512NW`.\n\nSigned-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nChange-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827\nOriginal-Reviewed-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Eric Lai \u003ceric_lai@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71239\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3c9bdb97190cbeaf383633d52a57810a2361dccc", "tree": "daf19e4813959ffc7c8ac9d8ca19ae34bde731ea", "parents": [ "b931e7a81314d0a9e44312ada2996719da19154e" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Dec 15 23:30:16 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "flashchips.c: Indent definition of W25Q512NW-IM properly\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151\nOriginal-Reviewed-by: Eric Lai \u003ceric_lai@quanta.corp-partner.google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71238\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b931e7a81314d0a9e44312ada2996719da19154e", "tree": "06a427c3a3410a48e05e9c1c2da4fc571cd038ab", "parents": [ "09dd6ba4b16fd8d80e09de55702e0ba0a111ac89" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Dec 05 13:06:14 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "flashchips.c: remove WREN from GD25Q256D enter 4BA sequence\n\nAs noted in a comment on\n`commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D\ndatasheet indicates that the chip does not require a WREN command to\nenter 4BA mode.\n\nTesting has confirmed that a WREN command is not required, so change the\nflashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA.\n\nTicket: https://ticket.coreboot.org/issues/356\n\nTested: read/write/erase/verify GD25Q256D flash with FT2232H programmer\nTested: called spi_enter_exit_4ba(true), dumped registers, checked ADS\u003d1.\n\nChange-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71015\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d5ba24c1a0870c9b1e3142ffa122851b22acf0da", "tree": "8208daddbf73ed9733b183524519d1c8b5206601", "parents": [ "b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:28:35 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E\n\nChange-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71011\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86", "tree": "159be3b6cf099734c86474a71131660f903399ab", "parents": [ "c6e8b1ad88ed1c65bba9c6002a36b16181c1ffec" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:27:37 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M\n\nSplit chips:\n * W25Q32.V -\u003e W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV\n * W25Q32.W -\u003e W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q\n\nChange-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71010\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c6e8b1ad88ed1c65bba9c6002a36b16181c1ffec", "tree": "a96474c1ccdee8b8fcb54bf36894f639016979c2", "parents": [ "39687acc6bf41b955a11e8a8fa3f0029342cbb3e" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Aug 14 20:57:48 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for EN25QH32 and EN25QH64\n\nSplit chips:\n * EN25QH32 -\u003e EN25QH32 and EN25QH32B\n * EN25QH64 -\u003e EN25QH64 and EN25QH64A\n\nUnlike older revisions both newly added EN25QH32B and EN25QH64A support\nhalf block (32KiB) erase operation via 0x52 opcode.\n\nChange-Id: I759f0119346235ce0bddc78cde9c461495990c25\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71009\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "29c8b5db5da5c0506aaac26fdfd3c8312638a51b", "tree": "4977598e6bfbbfe95ec1be529dd5b5d2b454c327", "parents": [ "d81997cdb76a721e46cfd98a7e65410d4e9790a5" ], "author": { "name": "Evan Benn", "email": "evanbenn@chromium.org", "time": "Tue Sep 13 16:01:10 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "flashchips: Add write protect bits to W25Q64JW...M\n\nhttps://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale\u003den\u0026DocNo\u003dDA00-W25Q64JW\n\nTested: None\n\nChange-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62\nSigned-off-by: Evan Benn \u003cevanbenn@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71003\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c74eac2fa3349c41f43eb9bd73809a1f051a9346", "tree": "330e6692197e48a9ad63b1b7db3fbf1eb201efde", "parents": [ "c720b6e8fbe9245e670f1424c5d24143b22a4c72" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Thu Oct 06 18:17:58 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:54 2022 +0100" }, "message": "flashchips.c: mark WP of 9 entries as tested\n\nThis is based on information from:\n * commit a850fd0aa8054a1125a9231fa3317428f15900f4\n - GD25LQ128C/GD25LQ128D/GD25LQ128E\n - GD25LQ64(B)\n - GD25Q127C/GD25Q128C\n - GD25Q256D/GD25Q256E\n - GD25Q64(B)\n * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba\n - GD25Q32(B)\n * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8\n - W25Q64BV/W25Q64CV/W25Q64FV\n * https://github.com/Dasharo/dasharo-issues/issues/67\n - W25Q128.V..M\n * https://github.com/Dasharo/flashrom/pull/8\n - W25Q64.W\n\nChange-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Tested-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Tested-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Tested-by: Kamil Pokornicki \u003ckamil.pokornicki@3mdeb.com\u003e\nOriginal-Tested-by: Przemyslaw Banasiak \u003cprzemyslaw.banasiak@3mdeb.com\u003e\nOriginal-Tested-by: Maciej Pijanowski \u003cmaciej.pijanowski@3mdeb.com\u003e\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71001\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "590525835ab9f8b9471c17f859e0e18245008c08", "tree": "16fb4a4b18661a8692fd3f10e14ea8b25c29a3da", "parents": [ "3ca0af0c8baadb8a25056f0d6d7c2299822ae55b" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Mar 08 15:23:58 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips.c: Mark MT25QU256 as tested\n\nAs reported by Charles Parent on the mailing list.\n\nChange-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62664\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70998\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ca0af0c8baadb8a25056f0d6d7c2299822ae55b", "tree": "d47899d5e121026e9dcc7655c0e1ed455030bf24", "parents": [ "bb608ff1900eee52c4bb3eb624421a8c0fe1b694" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri Jun 17 15:10:18 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips.c: change GD25Q256D to \"GD25Q256D/GD25Q256E\"\n\nExtend \"D\" chip entry to include newer \"E\" parts.\n\nChange-Id: I6b398d417da9289cc1d6a191fb20e3f937addb21\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65191\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70997\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bb608ff1900eee52c4bb3eb624421a8c0fe1b694", "tree": "3b020028e30f3c6888a26cccad0f99040d32e5dd", "parents": [ "26237922269390f11788ae573c4af39eb17d5e30" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:33:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips: Add missing block eraser for S25FL512S\n\nNow that we can make use of the extended-address register, we can also\nadvertise the `d8` eraser that can take 3- or 4-byte addresses.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTicket: https://ticket.coreboot.org/issues/357\nChange-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64637\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70996\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "26237922269390f11788ae573c4af39eb17d5e30", "tree": "a91ae80f27628b92bc2401c6c3e871c0473473e5", "parents": [ "ad55d5a4ea4bc82450b076fbf9faffc130a698bb" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:37:37 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512S\n\nAccording to its datasheet, Spansion S25FL512S supports writing/\nreading its extended address register via 0x17/0x16 opcodes. With\nthat enabled, we can also enable the EAR7 feature, i.e. toggling\n4BA mode via bit 7 of that register.\n\nS25FL512S did not advertise EAR support at all, so we set it to\nTEST_UNTESTED again.\n\nChange-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70995\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ad55d5a4ea4bc82450b076fbf9faffc130a698bb", "tree": "6beb87c779785e2e3a823b171231c51c5c6f2602", "parents": [ "9bb8a322e991b899a6faff4ec14d2f4c6dba447d" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:32:16 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips\n\nAccording to their datasheets, ISSI IS25LP256 and IS25WP256 support\nboth 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended\naddress register. Flashrom will use 0xc5 by default if available,\nso adding the FEATURE_4BA_EAR_1716 flag makes no difference for now\n(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA\nset). It\u0027s better to have a comprehensive description of the chips,\nthough, in case somebody wants to use them in the future with a\nmaster that restricts available opcodes.\n\nChange-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70994\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d", "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35", "parents": [ "542b1f04869e7ac42b84800675f08f617ddf3f2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:07:34 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n instructions (and some programmers may be picky about which\n instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "542b1f04869e7ac42b84800675f08f617ddf3f2d", "tree": "9516bc3f06c3fc5d67203328e524b967b5d36901", "parents": [ "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 14:30:12 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Rename FEATURE_4BA_EXT_ADDR -\u003e _EAR_C5C8\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\nTo prepare for other instructions than the default 0xc5/0xc8, rename\nthe original feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70992\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c", "tree": "175824426d5d38363c842aa3bfd4267477d89073", "parents": [ "5215eab80aa6ce4682aaadac5b318cb6c6d1bd7b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 15:17:14 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Drop FOUR_BYTE_ADDR comments\n\n4BA support is implemented by now. So drop these obsolete comments.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I28c5d1de052c28735d5f07874874068ee744b77f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64600\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70991\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5215eab80aa6ce4682aaadac5b318cb6c6d1bd7b", "tree": "c927408b441b4e47102a46386176f27a14f2c3d6", "parents": [ "fffc48d247cef5102113d97538054066546b2297" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 23 15:13:07 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Split W25Q256.V\n\nThe W25Q256JV supports the full set of 4BA instructions, including two\nnative-4BA block erasers.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I1a68121ff40d2b1769632d8e5151c2cd972c23ef\nTicket: https://ticket.coreboot.org/issues/362\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64599\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70990\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fffc48d247cef5102113d97538054066546b2297", "tree": "cdb49567c3d7c2291fa33221989516afb1b03abf", "parents": [ "3f3c1f3238dcede30d0d15d36da6326b428b8b12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 14:26:06 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L\n\nThese chips seem to be rather regular, supporting 2.7V..3.6V, the\ncommon erase block sizes 4KiB, 32KiB, 64KiB and the usual block-\nprotection bits.\n\nStatus/configuration register naming differs from other vendors,\nthough. These chips have 2 status registers plus 3 configuration\nregisters. Configuration registers 1 \u0026 2 match status registers\n2 \u0026 3 of what we are used from other vendors. Read opcodes match\ntoo, however writes are always done through the WRSR instruction\nwhich can write up to 4 bytes (SR1, CR1, CR2, CR3).\n\nS25FL256L supports native 4BA commands and entering a 4BA mode.\nHowever, it uses an unusual opcode (0x53) for the 32KiB 4BA block\nerase.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I356df6649f29e50879a4da4183f1164a81cb0a09\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f3c1f3238dcede30d0d15d36da6326b428b8b12", "tree": "9adc4f207793fe401c9ffd28e2f7c60460766533", "parents": [ "478e179f2d5ecf6a8b82984444b9111913a8f50f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 16:48:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "spi25_statusreg: Allow WRSR_EXT for Status Register 3\n\nSpansion flash chips S25FL128L and S25FL256L use the WRSR instruction to\nwrite more than 2 registers. So align SR2 and SR3 support: The current\nFEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3\nis added. Also, WRSR3 needs a separate flag now.\n\nVerified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "478e179f2d5ecf6a8b82984444b9111913a8f50f", "tree": "a87192cf8ab508ce56cb441147d00d0658355e29", "parents": [ "1e6aabc39de5ca46a69ef1b164ce55a4288753c3" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Sat Jun 04 01:34:44 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:50 2022 +0100" }, "message": "flashrom.c, flashcips.c: Test the order of erase functions\n\nAdd a check so that the erase functions for all flashchips are in\nincreasing order of their respective eraseblock sizes. This is required\nfor the implentation of the improved erasing algorithm. The patch uses\nthe count of eraseblocks in each erase function to determine the order\n(More eraseblocks means that the function has smaller eraseblock size).\nAlso fix the structs in flashchips.c which were found to be not\nconforming to this test.\n\nTested: make \u0026\u0026 ./flashrom\n\nChange-Id: I137cb40483fa690ecc6c7eaece2d9d3f7a851bb4\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64961\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70987\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Aarya \u003caarya.chaumal@gmail.com\u003e\n" }, { "commit": "2502dbd627e595d2974b1419f5e54a2faa7406a1", "tree": "139f05845f46312101c492dd4aefd75a75ade642", "parents": [ "8f5bd989971c97c9d160cf4f1aa2b91f72b152fe" ], "author": { "name": "Atul Dhudase", "email": "adhudase@codeaurora.org", "time": "Tue Sep 21 10:02:20 2021 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "Add W25Q512NW-IM ID to flashrom\n\nAdd Winbond W25Q512NW-IM chip ID and specs to flashrom.\n\nTested: flash W25Q512NW-IM using CCD.\n\nOriginal-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65\nOriginal-Signed-off-by: Atul Dhudase \u003cadhudase@codeaurora.org\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890\nOriginal-Reviewed-by: Shelley Chen \u003cshchen@chromium.org\u003e\nOriginal-Reviewed-by: Vadim Bendebury \u003cvbendeb@chromium.org\u003e\nOriginal-Tested-by: Shelley Chen \u003cshchen@chromium.org\u003e\nOriginal-Commit-Queue: Shelley Chen \u003cshchen@chromium.org\u003e\n(cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61)\n\nNote: this commit was cherry-picked from the cros tree but\nincludes corrections to errors in the original commit\u0027s 4BA\nfeature flags that were spotted by Angel Pons\n\nChange-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70985\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8f5bd989971c97c9d160cf4f1aa2b91f72b152fe", "tree": "2a3ead55a8311b9a917f4e6291c8e9e61291ea4a", "parents": [ "d1af307018bf73b1e585b6427a84b4a58e42c934" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Wed Aug 26 09:15:53 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "flashchips: Fix W25Q256.W\n\nThe JW is the only known variant. A W25Q256FW may have existed with\nless 4BA instructions supported, but it never showed up and no data-\nsheet is available.\n\nUsed the datasheet from here:\nhttps://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf\n\nChange-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTicket: https://ticket.coreboot.org/issues/362\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70984\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1af307018bf73b1e585b6427a84b4a58e42c934", "tree": "74e8bddd48fb391178abc188141c96bfc1625da1", "parents": [ "801fcd0123af9a253d68089e2728d0f51a64b749" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Nov 08 00:00:43 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:49 2022 +0100" }, "message": "flashchips: enable write-protection for W25Q{64,128}.V\n\nConfiguration for W25Q64 was tested on hardware (W25Q64FV).\n\nEmulation of W25Q128 in dummyflasher will be extended to support WP.\nHaven\u0027t tested this one on hardware, but it\u0027s the same configuration as\nfor W25Q64 except that it has WPS.\n\nW25Q64JV chip was renamed to W25Q64JV-.M (those with QPI).\n\nW25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)\nand W25Q64JV-.Q (SR3 and WPS, but no QPI).\n\nflashrom-stable: FIXME added, W25Q128.V should probably be split.\n\nChange-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59071\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70982\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21", "tree": "cd09884914e46f8641d59b95a68132d47c1daa13", "parents": [ "551664c6a7c447746503afcd6e303c9b21fff71c" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Oct 20 17:09:09 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "flashchips.c: mark IS25LP064 as TEST_OK_PREW\n\nTested \u0027-w\u0027, \u0027-E\u0027 and \u0027-r\u0027 successfully with\nmy FT2232H programmer.\n\nChange-Id: I2197ce0be9db7c3d74b24c7445dc06238584ffea\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58472\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70979\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "551664c6a7c447746503afcd6e303c9b21fff71c", "tree": "7d2044394629218ba5b58afad9dd8f68e5034f87", "parents": [ "ccae68ac91b00eb68adf11fa88e6d9a1aaa01b0b" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Mar 09 16:09:08 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:48 2022 +0100" }, "message": "flashchips.c: Mark GD25Q40(B) as tested\n\nAs mentioned by Wolf Dieter Brandt in his mail from 07.Feb.22.\n\nChange-Id: Idec3d82efbdf095c3d57bfe5f0fd487007b554cb\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62712\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70978\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d32e18b0c03a0426f808477544f6ecec9ae10f66", "tree": "73e1e07c595028935a4183b628101b95c53fd660", "parents": [ "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Feb 15 18:06:55 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "flashchips.c: add writeprotect support for more chips\n\nChips I had available for testing were tested with all writeprotect\ncommands and an FT232H adapter. Chips I wasn\u0027t able to test were just\nchecked against the datasheets.\n\nChips used for testing (including chips added in previous patches) are\nlisted in the table below:\n\nFlashrom Chip name | Chip(s) tested\n---------------------------------+----------------------------\nAT25SL128A |\nEN25QH128 |\nGD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG\nGD25LQ64(B) | GD25LQ64CWIG\nGD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG\nGD25Q256D | GD25Q256DYIG\nGD25Q64(B) | GD25Q64CSIG\nW25Q128.JW.DTR |\nW25Q128.V..M |\nW25Q128.W |\nW25Q256JV_M |\nW25Q256.V |\nW25Q64.W |\nXM25QH128C |\nXM25QH256C |\n\nTested: flashrom --wp-{enable,disable,range,list,status}\n\nChange-Id: I7f3d4c4148056098a845b5c64308b0333ebda395\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70976\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c9feb1bdfa96745a200b9a62dc4234446db8ddb6", "tree": "b532df293904cb48d7efa7b127a0072f48801835", "parents": [ "da1c834e9899e5094377a33d19daa53c0d88640b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 21 01:35:13 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:45 2022 +0100" }, "message": "flashchips,writeprotect_ranges: add range decoding function\n\nAllow chips to specify functions that map status register bits to\nprotection ranges. These are used to enumerate available ranges and\ndetermine the protection state of chips. The patch also adds a range\ndecoding function for the example chips. Many other chips can also be\nhandled by it, though some will require different functions (e.g.\nMX25L6406 and related chips).\n\nAnother approach that has been tried in cros flashrom is maintaining\ntables of range data, but it quickly becomes error prone and hard to\nvalidate.\n\nUsing a function to interpret the ranges allows compact encoding with\nmost chips and is flexible enough to allow chips with less predictable\nranges to be handled as well.\n\nTested: dumped range tables, checked against datasheets\n\nChange-Id: Id163ed80938a946a502ed116e48e8236e36eb203\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70969\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c6c3f28c66e0ad792274ca05029a120925e21be6", "tree": "0df6153a2d812235b3defe835f40b9ed08684c92", "parents": [ "9de3f8710d5c46d35cd9869018c85e5aa51483b0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 23:34:15 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "flash.h,flashchips.c: add writeprotect bit layout map to chips\n\nThis patch adds a register bit map `struct reg_bit_info`, with fields\nfor storing the register, bit index, and writability of each bit that\naffects the chip\u0027s write protection. This allows writeprotect code to be\nindependent of the register layout of any specific chip. The new fields\nhave been filled out for example chips.\n\nThe representation is centered around describing how bits can be\naccessed and modified, rather than the layout of registers. This is\ngenerally easier to work with in code that needs to access specific bits\nand typically requires specifying the locations of fewer bits overall.\n\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\n\nChange-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70966\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0", "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df", "parents": [ "0167522794a2e66f00248347122c1bb8ce3b001d" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Wed Oct 20 22:32:25 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:44 2022 +0100" }, "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "236a38cc46ac810d0be679402bb21e83aebcb8b9", "tree": "a460050e0a50e0cb37383709b1abfdbcbc7bbcbc", "parents": [ "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Fri Nov 05 11:48:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips: Add W25Q64JV\n\nI have successfully tested it with FT2232H-programmer.\n\nChange-Id: Ia9a32146b225eca66e9a6bfef45be5f2b24aef46\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58971\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70963\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d173ed4a8e9499127fed16c1a7c9f2262ee7b4a6", "tree": "daf3ce9e6a6aa471eeeea5296904ff369d448f65", "parents": [ "571f6ad31f0047fdbf613448e04d9c7138ade662" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Sep 29 09:28:07 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:43 2022 +0100" }, "message": "flashchips.c: mark EN25F10 as TEST_OK_PREW\n\nAs reported by Wolf Dieter Brandt in his e-mail from 09.Aug.2021.\n\nChange-Id: I0c19f84780e7fa3699fd706f8e105fc5937ba8bf\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58031\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70962\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "571f6ad31f0047fdbf613448e04d9c7138ade662", "tree": "a0926521de7d240eab415da54dc70ffa5712fd5a", "parents": [ "981a344f65c2125b7aba72c0a61760f33c508ec2" ], "author": { "name": "Tao Xia", "email": "xiatao5@huaqin.corp-partner.google.com", "time": "Wed Jul 21 16:41:53 2021 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12833F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nSigned-off-by: Tao Xia \u003cxiatao5@huaqin.corp-partner.google.com\u003e\nChange-Id: I14ab7e04f5209d2bcf34b0d2de9da2c01bf32d00\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56546\nOriginal-Reviewed-by: Weimin Wu \u003cwuweimin@huaqin.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70961\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "981a344f65c2125b7aba72c0a61760f33c508ec2", "tree": "79e38d75327c731023c3e4b5f2729eb5695b2484", "parents": [ "2649dde2be69f01f4c5bee4a7d21223bd25e322c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Tue Jun 22 11:16:55 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips.c: Add \u0027GD25LQ128E\u0027 to match C and D variants\n\nAs defined by gigadevice. C, D and E are all meant to\nbe the same.\n\nChange-Id: I3bef9386a185a0e8c54c125af5509b63540995aa\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55742\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70960\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2649dde2be69f01f4c5bee4a7d21223bd25e322c", "tree": "2232b470f8921c5b5cb9cddf8864536c5e9eec26", "parents": [ "3ba8315e134c3fc0f29b538abb22fd9e85a2361f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 03 13:47:39 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add MX25L12873F\n\nJust add the name to the existing entry, as usual it is supposed to be\ncompatible.\n\nChange-Id: I59c8067f15b5ceac5a2e2f8fe93431a465f17e23\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56054\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70959\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ba8315e134c3fc0f29b538abb22fd9e85a2361f", "tree": "315ee58cda0d2d9de74142d442d43bf31ba500e2", "parents": [ "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8" ], "author": { "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com", "time": "Tue Jun 08 10:52:19 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:42 2022 +0100" }, "message": "flashchips: Add support for Macronix MX66L1G45G\n\nTested on Dediprog SF600: Reading and writing works.\n\nChange-Id: I554e828c97d9ec77b08489573a34e176599d2518\nSigned-off-by: Patrick Rudolph \u003cpatrick.rudolph@9elements.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55353\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70958\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b7014f9e0a6768c3978dd20c4f1cb302c35bf3d8", "tree": "67f1c17c4dd4fd6ab500a78c5aee1ce7db03d5d1", "parents": [ "5fa050515d2fff9679d38803a8594e4a8c5a407a" ], "author": { "name": "Simon Buhrow", "email": "simon.buhrow@sieb-meyer.de", "time": "Mon Feb 15 13:16:57 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: Mark MT25QL256 as tested\n\nAs mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020.\n\nChange-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70957\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5fa050515d2fff9679d38803a8594e4a8c5a407a", "tree": "59ba8caf8f49cbec055d2cb0b47052d3e54c65ab", "parents": [ "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri May 14 15:26:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips: change chip name from \u0027W25Q64JW\u0027 to \u0027W25Q64JW...M\u0027\n\nAccording to the W25Q64JW datasheet rev. E, only devices ending with the\nletter \u0027M\u0027 have a device ID of 8017h. There are other variants with\ndifferent device IDs. This patch makes the \u0027W25Q64JW...M\u0027 definition\nconsistent with the \u0027W25Q32JW...M\u0027 definition.\n\nThe device ID macro defined in flashchips.h has also been renamed from\nWINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.\n\nChange-Id: Ib0dc914da286a191d22e666332b1063b88db4251\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70956\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6ae79b12dc8142f5af6f2c0621a4c3d90fa780d0", "tree": "0d12cf62cf976d9a3378fa48a245478c1caffab1", "parents": [ "b6683e0a5586537269524eaadee5619d1dec410b" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Sat May 08 17:31:23 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:41 2022 +0100" }, "message": "flashchips.c: add support for W25Q32JW...M\n\nThe chip was added to cros flashrom in\n`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.\nQuoting from the commit message:\n\n\u003e We have varied the correct chip name is reported as well as\n\u003e write and read 16MBytes of random data and verified the checksum\u0027s match.\n\u003e Further, --wp-list appears to report the correct ranges.\n\u003e\n\u003e BUG\u003db:130199963\n\u003e BRANCH\u003dnone\n\u003e TEST\u003dRan flashrom with a Dediprog SF100, RW random data and checksum matched.\n\nChange-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70955\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b6683e0a5586537269524eaadee5619d1dec410b", "tree": "b2bdb49813421373adc4a5f8ede57b920b89e05c", "parents": [ "6e69e2b5f78104e5b54e83be889ae887702309ff" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:04:29 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add MX25L3233F\n\nOnly mattering difference to the MX25L3273E seems to be the voltage\nrange (starting at 2.65V instead of 2.7V). I don\u0027t think that would\njustify yet another entry.\n\nChange-Id: I73402dddedf360ab84caed4c019efe27b477d4c2\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52570\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70954\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "6e69e2b5f78104e5b54e83be889ae887702309ff", "tree": "78ea64917e28700796c57bba0d0f8602145360d0", "parents": [ "475a7eed6d6589c8a1e5267a1f4be3500fb245c4" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 21 13:03:13 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Correct OTP comment for MX25L3273E\n\nThe datasheet says 4K bits, maybe just a copy-paste error.\n\nChange-Id: I42b10aa09c969e5c5e7102b1e8ab496f52bd27bb\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52569\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70953\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "475a7eed6d6589c8a1e5267a1f4be3500fb245c4", "tree": "6a90aa1167acc44f0ddf92f0124d3eaa220bef33", "parents": [ "1ebda787f1c6bec8e63d06a01ba921c49c4e2187" ], "author": { "name": "Christian Kudera", "email": "coreboot@kudera.at", "time": "Tue Apr 20 22:50:01 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:40 2022 +0100" }, "message": "flashchips: Add support for Boya/BoHong Microelectronics B_25D16A\n\nRead tested on CH341A\n\nChange-Id: I25b776204affda94cc7e753e7671ef9d3d9508f1\nSigned-off-by: Christian Kudera \u003ccoreboot@kudera.at\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52555\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70952\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1ebda787f1c6bec8e63d06a01ba921c49c4e2187", "tree": "193cb9fe46cd8ca4887496c6fc63e6cc7e8fe7cc", "parents": [ "148254be920530d54d76d742b30a3fb61689cf07" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Apr 20 21:39:11 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips: Adapt IDs for Boya Microelectronics\n\nLooks like BoHong Microelectronics has the same vendor ID and makes very\nsimilar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have\nthe same specifications and their datasheets are mostly identical.\n\nChange-Id: I8d6951797daeeecca6af200c995297c0394adefd\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70951\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "148254be920530d54d76d742b30a3fb61689cf07", "tree": "ff3580e4dcd6726dc1dd97ce6fa2d01d5f1135f6", "parents": [ "e64ef6d72741c39cb9a5e866d9952f2b14366996" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:21:10 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark MX25U25635F as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit 419e32ae457cc36b03757b89471a7ce3770e9611`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dTested writes using Servo\n\nChange-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70950\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e64ef6d72741c39cb9a5e866d9952f2b14366996", "tree": "9ae607243716dcdab4d39e4e282d89412bf020af", "parents": [ "df889fa924154ffd1265971b05002c28651b8e83" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:15:40 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:39 2022 +0100" }, "message": "flashchips.c: mark GD25Q256D as TESTED_OK_PREW\n\nTested read/write/erase/verify with FT232H programmer.\n\nChange-Id: Ia7d52b69eb571113fe3c60ec9a139ee67180509b\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51735\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70949\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "df889fa924154ffd1265971b05002c28651b8e83", "tree": "068e75775d2d757e3cf1a264aa8e7f4d5c069c22", "parents": [ "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Mar 23 17:10:45 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: mark EN25S64 as TESTED_OK_PREW\n\nThe chip was marked as TESTED_OK_PREW in the cros tree by\n`commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`.\n\nQuoting from the original commit message:\n\u003e TEST\u003dread and write BIOS on glimmer with Eon device.\n\nChange-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70948\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bfe149a42aa9b4e0c05793d88094a1e10d3bf2e5", "tree": "e65d194cc42f67ab9caf8bcc6dbf400d5546b6f5", "parents": [ "c205487aede60d9926541159631a0e360abdc82d" ], "author": { "name": "Tim Chen", "email": "tim-chen@quanta.corp-partner.google.com", "time": "Mon Jul 06 14:59:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "CHROMIUM: flashrom: update .tested field for EN25QH128\n\nupdate .tested field from TEST_UNTESTED to TEST_OK_PREW\n\nTested: Flash Duffy bios\n pass on running `flashrom_tester /usr/sbin/flashrom host`\n\nOriginal-Change-Id: I9467588988c2cab0987737c53ace0832144ef169\nOriginal-Signed-off-by: Tim Chen \u003ctim-chen@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Commit-Queue: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n(cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff)\n\nChange-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70947\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c205487aede60d9926541159631a0e360abdc82d", "tree": "417b46539f418ddfc293d1041ad762d54207dec5", "parents": [ "813a7e2eef268f2e63b2cac2e9b60a2ed2365945" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jan 15 18:57:32 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips: Mark Macronix MX25L1635D as tested\n\nTested probe, read, erase and write with a FTDI FT2232H successfully.\n\nChange-Id: I7421b7e36e687ea2ffff494c00157976db73ac43\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49489\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70945\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "813a7e2eef268f2e63b2cac2e9b60a2ed2365945", "tree": "89eba409e95982a9507434721351671c52df042d", "parents": [ "721a4f390410debb77487562c8a47a20edb4d7f2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Jan 08 08:48:17 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:38 2022 +0100" }, "message": "flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW\n\nI have successfully probed/read/erased/written a GD25LQ128D, so marking\nthis entry as tested.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70944\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ef88423928abf61fa894d2798a9d265fd001cd26", "tree": "8ceb8aa058cf63a0f39e4a9c8114733b0914af1c", "parents": [ "e0e8b2b8f99030962994b876353e3a69cb68af80" ], "author": { "name": "luke he", "email": "sixuerain@qq.com", "time": "Mon Dec 28 18:22:21 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips.c: Add support for XMC new SPI flash types\n\nAdds initial support for the follow SPI flash chips:\n\n XM25QU64C\n XM25QU128C\n XM25QU256C\n XM25QH64C\n XM25QH128C\n XM25QH256C\n\nflashrom-stable:\n* Added missing 4BA flags / erasers\n* Dropped wrong, superfluous comments\n* Sorted\n\nSigned-off-by: Luke He \u003csixuerain@qq.com\u003e\nChange-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70942\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e0e8b2b8f99030962994b876353e3a69cb68af80", "tree": "ff9e47bf8eba1954ad347a9ea8bab70bb7af2306", "parents": [ "4ad486465ccceedce372c498ad19ac84edbc0078" ], "author": { "name": "Zoltan HERPAI", "email": "wigyori@uid0.hu", "time": "Sat Aug 08 16:04:34 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:37 2022 +0100" }, "message": "flashchips: Mark Intel 25F640S33B8 as TESTED_PREW\n\nTested with ch341a_spi from an Atheros AP81 reference board.\n\nChange-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef\nSigned-off-by: Zoltan HERPAI \u003cwigyori@uid0.hu\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44342\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70941\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73ae5efbc36e8523d1f2fce1258a9ab2eef02e5e", "tree": "bb4d94a94cf593bae5592de6bdee9afe61eafeae", "parents": [ "0cf3e12fd5e420115551062a225b44e1782ba629" ], "author": { "name": "Jack Olsen", "email": "omegasec@tutanota.com", "time": "Sat Aug 08 21:12:13 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Boya Microelectronics BY25Q128AS\n\nTested on Buspirate.\n\nSigned-off-by: Jack Olsen \u003comegasec@tutanota.com\u003e\nChange-Id: I881ba86cfaa82e43c73360135d47c74d896cc191\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70939\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cf3e12fd5e420115551062a225b44e1782ba629", "tree": "917b704ffedd00099c9958126fe8698edc4ba89f", "parents": [ "3153260aecbec2e8719f8b093c0f17ec860e4b2c" ], "author": { "name": "Jakob Petersson", "email": "github@jakobpetersson.se", "time": "Mon Feb 18 01:55:43 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:36 2022 +0100" }, "message": "flashchips: Add support for Fudan SPI flash chips\n\nflashrom-stable: Found additional info on Github:\n\nCode is taken from existing PATCH by Stefan Tauner stefan.tauner@alumni.tuwien.ac.at\nhttps://mail.coreboot.org/pipermail/flashrom/2016-June/014672.html\n\nWith the only change being the Manufacture ID being changed\nfrom 0x04h to 0xA1h.\n\nI have only tested it with FM25F005 and it seems to work.\n\nSigned-off-by: Jakob Petersson \u003cgithub@jakobpetersson.se\u003e\nChange-Id: I8045ecb8778fd6111fcccc075e69928f131a926a\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/46513\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70938\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3153260aecbec2e8719f8b093c0f17ec860e4b2c", "tree": "3edf5db4440c03b321b3ce5f74816c488f08bc1e", "parents": [ "7e6f3a7ccb8fb5206ceaddc9bb0c285f4264cabf" ], "author": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Aug 16 17:14:56 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add W25Q256JW_DTR\n\nW25Q256JW currently has two variants, the W25Q256JW with device\nID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka\nW25Q256JW-IM) with device ID 0x8019 added by this patch.\n\nWinbond W25Q256-series chips have a few device IDs:\n0x4019: W25Q256FV\n0x6019: W25Q256JW\n0x7019: W25Q256JV\n0x8019: W25Q256JW_DTR\n\nHence we need to be more specific with naming than usual to avoid a\nfalse positive with wildcards.\n\nChange-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386\nOriginal-Reviewed-by: Simon Buhrow\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70937\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e6f3a7ccb8fb5206ceaddc9bb0c285f4264cabf", "tree": "7ded0eda3ea711bab56e644997601a1cc38ef40c", "parents": [ "ebbdc02ee860ee4e3baeecc6a0c220d138499c59" ], "author": { "name": "Steve Markgraf", "email": "steve@steve-m.de", "time": "Mon Jul 13 18:22:56 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add support for Macronix MX25L5121E\n\nTested with ch341a_spi.\n\nChange-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766\nSigned-off-by: Steve Markgraf \u003csteve@steve-m.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43416\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70936\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ebbdc02ee860ee4e3baeecc6a0c220d138499c59", "tree": "23a7947c060e0eddbfb60e6112eb5b5696057913", "parents": [ "0120985bd3ccc5d22906863b21902b29e87bc05b" ], "author": { "name": "Jacob Appelbaum", "email": "jacob@appelbaum.net", "time": "Mon Sep 02 09:10:43 2019 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "Add support for Winbond W25X05CL\n\nThis commit adds support for the Winbond W25X05CL SPI flash chip. The\nWinbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors.\nI have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL\nflash chip using a test clip. Reading, erasing, and writing all function\nas expected.\n\nChange-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc\nSigned-off-by: Jacob Appelbaum \u003cjacob@appelbaum.net\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70935\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0120985bd3ccc5d22906863b21902b29e87bc05b", "tree": "97ac99f76b39e88566e10b0b8e11b6ded21ba3e6", "parents": [ "5eca427ae64519b70d1c4ccfb427305ca9974ba0" ], "author": { "name": "el-coderon", "email": "simon.buhrow@sieb-meyer.de", "time": "Wed Apr 29 12:12:53 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:35 2022 +0100" }, "message": "flashchips: Add W25Q256.W\n\nNicklas Lennert wrote me via the flashrom mailing list that\nhe successfully ran read, write and verify cmd.\n\nSigned-off-by: Simon Buhrow \u003csimon.buhrow@posteo.de\u003e\nChange-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70934\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1bbc501f79319cc6c8d839bc44fa55e96afab33a", "tree": "930ed121151a82ddc0e157c3b2c1b50de99a6a77", "parents": [ "5543961c01fe6d6fb1ec7e68b8dcc766d0d272e3" ], "author": { "name": "Scott Chao", "email": "scott.chao@bitland.corp-partner.google.com", "time": "Wed Apr 08 22:10:50 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "flashchips: Add support for Winbond W25Q64JW\n\nTested: flash coreboot on kakadu and get successful result.\n\nChange-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967\nSigned-off-by: Scott Chao \u003cscott.chao@bitland.corp-partner.google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Hung-Te Lin \u003chungte@chromium.org\u003e\nOriginal-Tested-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70932\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5543961c01fe6d6fb1ec7e68b8dcc766d0d272e3", "tree": "945ad58063335ccf3b76d7dc02eded147c9b1b7f", "parents": [ "3214f58db8f8cceb40d4faa16130124446cc35fa" ], "author": { "name": "Joel Stanley", "email": "joel@jms.id.au", "time": "Sat Jul 27 19:25:35 2019 +0930" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "flashchips: Add W25Q512JV\n\nhttps://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf\n\nTested with dediprog SF100.\n\nChange-Id: I8d16f0918785795cc49500435a03641b87d706e9\nSigned-off-by: Joel Stanley \u003cjoel@jms.id.au\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595\nOriginal-Reviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70931\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3214f58db8f8cceb40d4faa16130124446cc35fa", "tree": "6b7d14da618a215fc619d786305bfad9387e5163", "parents": [ "f62623cff61d677609fbd92a71a5ad7875ad9b8a" ], "author": { "name": "Dino Li", "email": "Dino.Li@ite.com.tw", "time": "Wed Mar 25 17:39:53 2020 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "flashchips: add support for GigaDevice GD25WQ80E\n\nSupport GD25WQ80E, which is the internal flash of IT81202.\n\nTested: Building flashrom and flashing FW image into IT81202 successfully.\n\nChange-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8\nSigned-off-by: Dino Li \u003cDino.Li@ite.com.tw\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70930\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f62623cff61d677609fbd92a71a5ad7875ad9b8a", "tree": "989cca84ef37d1878dca9b25220766fd2123cb49", "parents": [ "9245b889dde1dba76cd696d5d354ac89b84fca65" ], "author": { "name": "sibradzic", "email": "5964548+sibradzic@users.noreply.github.com", "time": "Sat Mar 14 17:21:34 2020 +0900" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:33 2022 +0100" }, "message": "flashchips: Add Macronix MX25R3235F\n\n32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is\nsimilar to the already-supported MX25R6435F, but the total size is\nhalved.\n\nTested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed\nworking probe, read, erase and write.\n\nFixes: https://github.com/flashrom/flashrom/issues/43\n\nChange-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5\nSigned-off-by: Samir Ibradzic \u003csibradzic@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70929\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "05c629be2964bcee368c03d805747da15281856d", "tree": "ffe6f7df4ee0ba5a76e58f739200cc6b3e0383e2", "parents": [ "b5433b782ff7cbde14ebd91aeac27efaec83e9d0" ], "author": { "name": "Bernhard Urban-Forster", "email": "lewurm@gmail.com", "time": "Sun Feb 02 21:29:48 2020 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:21:46 2020 +0000" }, "message": "flashchips: Add Spansion S25FL512S\n\nAs found on the Tesla AP2.5 board.\n\nBased on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html\n\nTested with:\n flashrom -p linux_spi:dev\u003d/dev/spidev0.0,spispeed\u003d512 -r content.bin\n\nSigned-off-by: Bernhard Urban-Forster \u003clewurm@gmail.com\u003e\nChange-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38596\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "4139438943010c7aec6549d8b18865da5b70e978", "tree": "0c517723249fe9a4065ee2b52603d34a385290a6", "parents": [ "89622674b29c09bb33cb5844520d9271ebef8ea0" ], "author": { "name": "darkarnium", "email": "peter.adkins@kernelpicnic.net", "time": "Mon Nov 04 20:06:48 2019 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 14 15:25:30 2019 +0000" }, "message": "flashchips: Add AT25SF321\n\nThis commit adds support for the Adesto AT25SF321 SPI flash chip. Probe\nand read operations have been tested via FT2232H interface, but writes\nhave not been verified.\n\nDatasheet is available at the following URL:\nhttps://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf\n\nChange-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56\nSigned-off-by: Peter Adkins \u003cpete@kernelpicnic.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36904\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1a119498b43a8ed934bcfa0a16465aa4d6d2c74d", "tree": "65860cc7d10787128bc90609af22e74ec1465f39", "parents": [ "80e8dc4df72b72170190a91c31cdc0a0b5e08358" ], "author": { "name": "Peichao Wang", "email": "peichao.wang@bitland.corp-partner.google.com", "time": "Mon Nov 11 15:26:41 2019 +0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 13 12:32:11 2019 +0000" }, "message": "flashchips: Add W25Q128JW_DTR\n\nPort the code from chromeos flashrom\n\nBUG\u003db:144297264\nTEST\u003dTested using W25Q128JWDTR in SPI mode\n\nSigned-off-by: Peichao.Wang \u003cpeichao.wang@bitland.corp-partner.google.com\u003e\nChange-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/36717\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "80e8dc4df72b72170190a91c31cdc0a0b5e08358", "tree": "c706ef2c5e7d1f2a69e70218b849f7c461e8b7ff", "parents": [ "2f6936bd926b6d4f21680e2cdc160fc580c3ecb3" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:35:30 2019 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Mon Nov 11 02:53:01 2019 +0000" }, "message": "flashchips: Add missing N25Q/MT25Q variants\n\nThis adds missing voltage and capacity variants for N25Q and MT25Q\nseries devices. This also fixes a typo in some model numbers where the\nlast letter should have been a G instead of an E. Added devices include:\n\nN25Q256..1E\nN25Q512..1G\nN25Q00A..1G\nN25Q00A..3G\nMT25QU128\nMT25QL128\nMT25QU256\nMT25QU512 tested by Jacob Creedon \u003cjcreedon@google.com\u003e\nMT25QL01G tested by Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nMT25QU01G\nMT25QL02G\nMT25QU02G\n\nTwo have been tested as indicated, all other variants added are marked\nuntested.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34491\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "5374dc3461f1e74a56a4db1a8d684b29cb3a92e5", "tree": "311ed873936176c06226c160ea04a574a3cbe046", "parents": [ "92b17a52a3aaec7e87aabfc6ce5f05726d1000c0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 16:16:15 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 05 23:33:22 2019 +0000" }, "message": "flashchips: Add missing block erasers for GD25Q256D\n\nChange-Id: I7e49e468c7f1eaf0ddd5fc08d6cc6569274faf94\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35798\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "3d8868c2b46548be6885198987492d91933c9ff7", "tree": "2277db98f8b19982802f812b2a984a2591009e37", "parents": [ "4a84ec273a487c27f91bd3df70cbdf8894af70e1" ], "author": { "name": "Konstantin Grudnev", "email": "grudnevkv@gmail.com", "time": "Tue Jul 23 00:48:54 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 04 17:41:01 2019 +0000" }, "message": "Add support for M95M02-A125\n\nAutomotive 2 Mbit (256KiB) serial SPI bus EEPROM\nPREW tested successfully with use of ch341a programmer\non Linux host 5.2.0-1-MANJARO x86_64\n\nSigned-off-by: Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nChange-Id: Ic29cd9051c7eac4822d620c299834134f987f01b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34496\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a", "tree": "c800a57c8c1bc4dc851ac939b289dd21ad03b33b", "parents": [ "07b8a17db65ad38ffcb7344192ba37d79f03193e" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Sep 23 17:12:44 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:20:55 2019 +0000" }, "message": "flashchips.c: Add W25Q128.V..M printlock attribute\n\nAdd a printlock attribute for the Winbond W25Q128.V..M chip. The\nprintlock attributes matches the ChromiumOS repo\u0027s definition of this\nchip.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I775d5d40677593dcb2d05750f8bbc62871b0e551\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35549\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "07b8a17db65ad38ffcb7344192ba37d79f03193e", "tree": "5f69f7abdcb32f73a25e14d9d0c4039385f84676", "parents": [ "86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Sep 23 16:47:05 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:19:00 2019 +0000" }, "message": "flashchips.c: Mark W25Q40EW as TESTED_PREW\n\nMark Winbond W25Q40EW as TESTED_PREW.\n\nThe Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS\nrepository. ChromiumOS has the same defintion for this chip as this\nrepo, except that ChromiumOS does not have FEATURE_OTP.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35535\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2", "tree": "8ef1d074dab28dee198fe84fab0ef7dbccf7bfd2", "parents": [ "40f0757750f246bd78981fb7c02aadf1d47b18e8" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 15:02:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 24 03:00:33 2019 +0000" }, "message": "flashchips.c: Add GD25Q256D from downstream\n\nTake definition of GD25Q256D from ChromiumOS repository.\n\nThis chip was added in `commit 0c38355c` by dlaurie@google.com\n2019-03-17.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35480\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "4362e629762857fefecd54fc970cdfbf5f9d6741", "tree": "5a4d3dacda6d39344416481eab4b0586f1a3d691", "parents": [ "03707300db4369a8c197fdda0b7730d4a43182fd" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 15:02:12 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Sep 18 01:20:33 2019 +0000" }, "message": "flashchips.c: Mark EN29F002(A)(N)B as tested +EW\n\nMark EN29F002(A)(N)B as tested for erase and write. This chip was marked\ntested in the Chromium (downstream) repo change\n98d917cfba55b68516cdf64c754d2f36c8c26722 \"Add a bunch of new/tested\nstuff and various small changes 8\"\n\nTEST\u003dBuild and run flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Idd26187905f389fc858eea5b13915af88e40afe9\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35092\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "03707300db4369a8c197fdda0b7730d4a43182fd", "tree": "38c72cfe7cee022776e9a71876738dadb9e39262", "parents": [ "4f00912c704ea6b69df8dc331199503b1c6739c3" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 12:50:43 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 07:40:02 2019 +0000" }, "message": "flashchips.c: Identify MX25L25645G part\n\nApply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d,\n\"flashrom: Identify MX25L25645G part\" from\nchris_zhou@compal.corp-partner.google.com 2019-04-13. Change description\nwas:\n\n\"\"\"\nMX25L25635F and MX25L25645G have the same chips identify. Add\nMX25L25645G to the name of the part so that it doesn\u0027t confused people.\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I317345b4753cfc46fdca8f673a0591e33b62138b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35091\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "4f00912c704ea6b69df8dc331199503b1c6739c3", "tree": "18b7d84641364382629a82122b858bd5d90db5b3", "parents": [ "dd59220e7e774d3e8fa100cd0b448fa363e3be73" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Aug 26 10:45:18 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:47 2019 +0000" }, "message": "flashchips: Add GD25Q127C name to the GD25Q128C entry\n\nRenamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128.\n\nAccording to downstream (ChromiumOS) change\n4216ba3d0fbd1804a71002b9c17e0b04029a03f1 \"flashchips: Add GD25Q127C name\nto the GD25Q128C entry\", the 127C chip is replacement for the 128C chip.\nI have confirmed that 127C is newer and that 128C does not appear to be\ndocumented on Gigadevice\u0027s website or available from Digikey.\n\nTEST\u003dRan flashrom -L\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35089\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "dd59220e7e774d3e8fa100cd0b448fa363e3be73", "tree": "6d7c8fb007bf977a011c3b4b63bb906f5872b677", "parents": [ "71b706f544eff68657a15139c39b9f0d8c3b2940" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Fri Aug 23 10:11:37 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Tue Sep 17 06:29:13 2019 +0000" }, "message": "flashchips.c: Put SFDP-capable chip back into position\n\nPut entry for Unknown SFDP-capable chip back into place at end of file.\n\nChange 1f9cc7d89992114c70f7a0545ad9f98701bebe56 \"flashchips.c: Sort file\nby vendor and model\" reordered many entries in flashchips.c, including\nthis one. However, the entry for Unknown, SFDP-capable chip should not\nhave been moved before any specific chip entries.\n\nAs reported by Angel Pons \u003cth3fanbus@gmail.com\u003e at\nhttps://review.coreboot.org/c/flashrom/+/33931:\n\n\"\"\"\nOops, this introduced a bug: the SFDP entry is no longer at the end of\nflashchips.c, so probing on a SFDP-capable Winbond chip results in added\nnoise (flashrom says things about an unknown chip, and then has two\ndefinitions for the same chip).\n\"\"\"\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5955020456dbcd5e7db280a459b668a743e464dc\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35037\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "188127e5692df218c560253095a1e96cdff7c6cd", "tree": "f4e17efd282d0c26c07ab5c1342c9120874e45b6", "parents": [ "ea0c093246fbaba9ab89348400ba4e99032aa4e0" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Aug 06 16:10:34 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Aug 21 06:18:16 2019 +0000" }, "message": "flashchips: upstream changes to GD25LQ128\n\nChange name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the\nchange from the chromium flashrom repo SHA\n6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at\nhttps://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)\n\nThe rationale from that change was:\n\n The GD25LQ128C part is EOL. It\u0027s replacement is GD25LQ128D, but\n both chips identify in the same manner. Add GD25LQ128D to the name\n of the part so that it doesn\u0027t confused people.\n\nMaking this name consistent will simplify further merging from the\nchromium fork.\n\nChange-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34735\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "045b97ebd97426b70706db7338a7fd76790b8781", "tree": "428bed111f3cc84a29c0059d74e337fe4cf7c7c9", "parents": [ "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:26:56 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:47 2019 +0000" }, "message": "flashchips: Add missing MT25Q erase commands\n\nThis adds additional 32KiB subsector erase commands 0x5c and 0x52 and an\nadditional bulk erase command of 0x60.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34490\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "e8e7b0e6e8b7f665c0cce4e9a68c5b7573d39130", "tree": "28ad082eab9008a0906bd409bf01377511202b27", "parents": [ "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:21:22 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:12:41 2019 +0000" }, "message": "flashchips: Fix N25Q512 bulk erase\n\nThe N25Q is a stacked device, so it requires 0xC4 to perform a die\nerase.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34489\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "08e9d1d895edc2a86e8c89aeda6ffe03b503eb24", "tree": "e554fa9e21be6164a33b6486e1cc04346f39d005", "parents": [ "a4e579f94a80b949a0173b4b49cce01f20383aa7" ], "author": { "name": "Jacob Creedon", "email": "jcreedon@google.com", "time": "Mon Jul 22 12:04:40 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 05 21:09:32 2019 +0000" }, "message": "flashchips: Split MT25Q from N25Q\n\nThe MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q\nis almost entirely backwards compatible with the N25Q series, however,\nthe MT25Q has additional subsector erase commands available, and there\nare differences in stacked devices in the higher capacity variants. The\nN25Q devices are left with \"Micron/Numonyx/ST\" as the vendor and MT25Q\ndevices are set with \"Micron\" as the vendor.\n\nSigned-off-by: Jacob Creedon \u003cjcreedon@google.com\u003e\nChange-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34488\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a4e579f94a80b949a0173b4b49cce01f20383aa7", "tree": "320e0898ff31848178faa258ae6d326a10a37c14", "parents": [ "8855257d2051b2db0f6b1a4125d39f075d360cc4" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 24 14:18:39 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 03 14:47:06 2019 +0000" }, "message": "flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PRE\n\nThe AMD Am29F010 was marked TEST_OK_PRE in chromium repo change\nSHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other\ndifferences in the definition of this chip.\n\nThis is the only change from the Chromium repo to be upstreamed for AMD\nchips.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34534\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "8855257d2051b2db0f6b1a4125d39f075d360cc4", "tree": "3968368edfdf80bc3b8be45714492d29654e2a88", "parents": [ "a508ca0acdc5cbd0ae8c2342d865d363ef24f185" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 24 13:56:06 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 03 14:46:24 2019 +0000" }, "message": "flashchips.c: Mark Intel 82802AB as TEST_OK_PREW\n\nIntel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their\nSHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork\nand here in upstream are otherwise substantially similar.\n\nThere are no other downstream changes for Intel chips to be upstreamed.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34533\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "a136d425cebc01fa4cfb670696243fd2194dd711", "tree": "9792a00db0dbd81de32d32f5da3b2d1651e5437b", "parents": [ "b221cd7048f9cde1fe789e686a0e0adaf9a688b3" ], "author": { "name": "Hemanth Guruva Reddy", "email": "meethemanth@gmail.com", "time": "Thu Jul 11 11:08:27 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 17 10:45:16 2019 +0000" }, "message": "flashchips: Add Macronix MX25L51245G as known chip\n\nMX25L51245G is identical to handling of MX66L51235F.\n\nChange-Id: I964e630197e33d69b199fdfb8816f18e3112bbb1\nSigned-off-by: Hemanth Guruva Reddy \u003cmeethemanth@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34234\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "908adf4589d34eaf3bd8395afa52aed8c8887cfd", "tree": "7381774317fc86dd8426183093d99ca45b06d5c1", "parents": [ "1f9cc7d89992114c70f7a0545ad9f98701bebe56" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Wed Jul 03 15:34:06 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 05 22:48:40 2019 +0000" }, "message": "flashchips.c: Make .tested lines consistent\n\nAs per comments on https://review.coreboot.org/c/flashrom/+/33833/, make\nplacement of spaces in .tested attributes with literal definitions\nconsistent.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33998\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "1f9cc7d89992114c70f7a0545ad9f98701bebe56", "tree": "be790c5a8ade8cbf74fccf2c05a878f77ea25651", "parents": [ "2d7ab6963c4450f2fae74632e0e74037641d50d2" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Mon Jul 01 11:10:45 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 05 22:48:18 2019 +0000" }, "message": "flashchips.c: Sort file by vendor and model\n\nFor self-consistency, and to allow tools to assist with merging the\nchromium fork of flashrom, sort the entries of flashchips.c. The file is\nalready largely sorted, though deviations have crept in over time.\n\nThis is a non-clever mostly ASCII-order sorting. It is not intended to\nbe permanent.\n\nChange-Id: I75a99583592526f60ba5264e92391bf8b1213b20\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33931\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "69146f70a65e8f376833390ced3951d8a8746996", "tree": "645527630eca55e910925cf5239294931a34ef9b", "parents": [ "f29ea362bb9ea035b6a36f0eff88c6ab77bbb97f" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 17:14:11 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:32:50 2019 +0000" }, "message": "flashchips.c: Format SFDP-capable chip entry\n\nTo allow automated tools to manipulate flashchips.c, make the definition\nof SFDP-capable chip more consistent with other definitions. This\ninvolves\n- reordering fields to match both other entries and the definition of\n struct flashchip.\n- reformatting comments to make them consistent with other entries.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I8708a11993822085b3e8d8c80532dfb935d39876\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33834\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "f29ea362bb9ea035b6a36f0eff88c6ab77bbb97f", "tree": "ed7eeb1e769ca400001f31c54985655f20f69f04", "parents": [ "c1863cad848a03a07e6d1a9b24dafaac39d62a94" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 17:14:02 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:32:22 2019 +0000" }, "message": "flashchips.c: Make comment placement consistent\n\nFor consistency, move a comment about an entry from inside the open\nbrace to outside it.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33837\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "c1863cad848a03a07e6d1a9b24dafaac39d62a94", "tree": "60e3d752d3d826d7f45f9872f3a1aed1233fe73c", "parents": [ "f5ad688f8be10c23dacc853ec0120bef5c6c3e1f" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:08:03 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:31:57 2019 +0000" }, "message": "flashchips.c: Fix field order\n\nFor consistency and in order to allow automated tools to work with\nflashchips.c, put fields in the same order as they are defined in struct\nflashchip, in flash.h\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33833\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "f5ad688f8be10c23dacc853ec0120bef5c6c3e1f", "tree": "474ca95ab1203026b761fbcfd325ab99390bcf32", "parents": [ "86bf6ab8876898d93ec19472190d8a2d0d56056e" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 12:09:13 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:30:42 2019 +0000" }, "message": "flashchips.c: Add comma after every .voltage attribute\n\nTo allow automated tools to manipulate flashchips.c, ensure that every\nvoltage attribute ends with a comma, even if it is the last member in\nthe definition.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33832\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\n" }, { "commit": "86bf6ab8876898d93ec19472190d8a2d0d56056e", "tree": "5001c54868278741c6675e2bf319128d88ef1b6e", "parents": [ "fdf5da43975808230f4e7c455dd0c57552622dfb" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 16:58:20 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Thu Jul 04 04:29:26 2019 +0000" }, "message": "flashchips: Drop dead code of AT26DF321\n\nThe definition for the AT26DF321 has been commented out since it was\nfirst added in 2008. The chip now appears to be obsolete, being marked\n\"obsolete\" and unstocked at Digikey. It is also only referred to in\nhistorical documents on the manufacturer\u0027s website (microchip.com).\n\nTo avoid further bitrot of this dead code, drop it.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33836\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "fdf5da43975808230f4e7c455dd0c57552622dfb", "tree": "27b3ddb8e2b32af53ce543deea1526b96b09fbd5", "parents": [ "cbb85c007605c4c643aa99738981ee6284644667" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 16:56:52 2019 +1000" }, "committer": { "name": "Edward O\u0027Callaghan", "email": "quasisec@chromium.org", "time": "Wed Jul 03 13:08:52 2019 +0000" }, "message": "flashchips.c: format block_erasers members\n\nTo allow automated tools to manipulate flashchips.c, ensure all\n.block_erasers definitions have consistent formatting:\n- start with the opening brace on a new line.\n- ensure end brace indented exactly two tabs.\n\nSFDP-capable chip is the one exception to this rule as it has an empty\nblock instead.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33831\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "cbb85c007605c4c643aa99738981ee6284644667", "tree": "d8a51d547c2ebafb629219854350355ae8438299", "parents": [ "57938f86991548c2efa62cb0fabd30f8090847b3" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Tue Jun 25 13:42:34 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:49:26 2019 +0000" }, "message": "flashchips.c: Make end of line comments consistent\n\nTo allow automated tools to manipulate flashchips.c, make end of line\ncomment formatting more consistent. Specifically, this change moves the\ncomma from end of line to immediately after the field value, before the\ncommment.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33830\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "57938f86991548c2efa62cb0fabd30f8090847b3", "tree": "c93fc8e290c4d3a80ce0b2dd1bbda2bd770422a0", "parents": [ "fa3fcd3ab353deb959130ee82f72f845f0fd8209" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:06:43 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:46:38 2019 +0000" }, "message": "flashchips.c: ATMEL-\u003eAtmel for consistency\n\nReplace the single instance where a vendor name was spelled\ninconsistently.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33829\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fa3fcd3ab353deb959130ee82f72f845f0fd8209", "tree": "1b0839e1cb7b8e257ded1dd9d132b043c76f486a", "parents": [ "f75d8c558778a47e90f814860b3c664115aefc36" ], "author": { "name": "Alan Green", "email": "avg@google.com", "time": "Thu Jun 27 15:41:50 2019 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 02 09:45:53 2019 +0000" }, "message": "flashchips.c: Make whitespace consistent\n\nFor consistency, and to make the file amenable to manipulation by tools,\nuse only tabs when indenting. Some previous changes had introduced\nspaces for indenting.\n\nAlso ensure that every table entry is separated by a single blank line.\n\nSigned-off-by: Alan Green \u003cavg@google.com\u003e\nChange-Id: Ib2193798cc52641d6c443f8851903c749b31cb74\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33828\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f75d8c558778a47e90f814860b3c664115aefc36", "tree": "7ceb5b5f2a4c4ae037e48290f747c61240e711de", "parents": [ "0a0b45bba6c1f467958c92620110a731d4917c89" ], "author": { "name": "David Tomaschik", "email": "davidtomaschik@google.com", "time": "Thu Jun 20 09:49:01 2019 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 28 06:44:59 2019 +0000" }, "message": "Add support for MX25U25635F\n\nThis is a 256Kb part with support for JEDEC 4 byte addressing modes.\nTested successfully for probe/read.\n\nChange-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c\nSigned-off-by: David Tomaschik \u003cdavidtomaschik@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33639\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f2cd32570eb8624c60e97aecd5c9045249b376fe", "tree": "6a268512dc000d2a0e0a08e68ccad9df4b5853c5", "parents": [ "c4e9fd0abc51959885aafe6312a2d8c9b3935434" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:03:45 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 01 16:37:32 2018 +0000" }, "message": "flashchips: Add Sanyo LE25FU206/A and LE25FU106B\n\nAs per user `The_Raven Raven` on the mailing list. Since the added\nvalues had some inconsistencies, the chips are marked as untested.\n\nChange-Id: I6c26aafdca232110986334e85297d73d513600dc\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28813\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" } ], "next": "61818dc098edf3bf41f2d6502456fe0cd078c007" }