)]}' { "log": [ { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "ad5b71994ef7cdf7ecacd967d27d13b487805607", "tree": "5fccb97c12eca8807c7403fe69b42a37bcb780ea", "parents": [ "c09fca49c925e62271632ac7bf6ad40fe53b5d98" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue May 16 11:13:17 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu May 18 13:54:53 2023 +0000" }, "message": "chipset_enable.c: Drop `_LARGEFILE64_SOURCE`\n\nThis file does not access any large files, so there\u0027s no need to define\nthis feature test macro.\n\nChange-Id: I866cfa2f996eeea5846e5d9189647ad7a4a4e3e4\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/75272\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "632131590aa13544515f84822f94eb8f54d78e38", "tree": "7ba2063d0a8136be60866dc40fa79f11b2415598", "parents": [ "7a480310de5f7ec35d2d2acc7b60ca1ff8296944" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Apr 24 12:00:58 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 02 14:28:17 2023 +0000" }, "message": "chipset_enable: Mark C236 as DEP\n\nAs reported working by Tomas on the ML:\nhttps://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/2YSYIYKBUL5K26ZR5XIBV2YCXSNRWTNT/\n\nChange-Id: I575956d7e121350530e5b3e4e21384c0ea338d8f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/74857\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8c37eaa29e585ad5709dc306232cd21b2ab06b2c", "tree": "abcf1479206a3d7348ff98c5001de8bd16136297", "parents": [ "e0b92e0c8e88b19ed53c28ec71e3dd585f4b96dc" ], "author": { "name": "Christopher Lentocha", "email": "christopherericlentocha@gmail.com", "time": "Wed Jan 18 12:36:18 2023 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "Add missing Intel B460 flash chip id\n\nNote that while I can read the chip, on my Lenovo Legion T5 28IMB05,\ncannot write to the flash chip with any tools except upgrading with\nvendor tool, no downgrades are allowed, due to the fact of SMM, even if\nI did manage to flash the BIOS chip somehow, would still face bootguard\nsince this machine has bootguard. But if I read the chip, and verify my\nread bin file, it works fine, until changing the SMBIOS, which is in\nthe vendor BIOS update package.\n\nflashrom-stable:\nMarked as DEP as that is the convention for config-dependent chipsets.\n\nChange-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca\nSigned-off-by: Christopher Lentocha \u003cchristopherericlentocha@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/72056\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73486\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e0b92e0c8e88b19ed53c28ec71e3dd585f4b96dc", "tree": "41f402c9e215ab1731e58dc9451aa10190b436f0", "parents": [ "12d5eb9d2047cc15b7a4b1f46514e1151342dfa6" ], "author": { "name": "Jan Samek", "email": "jan.samek@siemens.com", "time": "Tue Dec 06 16:42:56 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "chipset_enable.c: add PCI ID for TGL-UP3\n\nAdd PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.\n\nChange-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407\nSigned-off-by: Jan Samek \u003cjan.samek@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "12d5eb9d2047cc15b7a4b1f46514e1151342dfa6", "tree": "9b1a6a63670e36607d08d33b4b20b9ce91a1012a", "parents": [ "d48318c92c88d35e9b90d61796d18df1266f2a82" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 00:11:10 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "chipset_enable: Add PCI ID for Raptor Lake S\n\nThe ID was found in [1].\n\n[1] Intel(r) 700 Series Chipset Family Platform Controller Hub\n Datasheet, Volume 1 of 2\n Doc. No.: 743835, Rev.: 002\n\nChange-Id: Iea4c6e856d2f153cef4906c7febbe895d958edae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73484\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d48318c92c88d35e9b90d61796d18df1266f2a82", "tree": "ada182ab55fe420fa36782479efbae6030c04dce", "parents": [ "c1fa3418ad546f1c6029174fa2f75c0e6b48e7a2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 14 23:37:18 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "chipset_enable: Add missing Tiger Lake IDs\n\nIt is unclear if the SPI controller is never hidden on Tiger Lake,\nhence we keep stacking the IDs of the eSPI controller. Tiger Point H\nIDs are from [1], the UP3/4 IDs from [2].\n\n[1] Intel(r) 500 Series Chipset Family Platform Controller Hub\n Datasheet, Volume 1 of 2\n Doc. No.: 635218, Rev.: 008\n[2] `src/include/device/pci_ids.h` in coreboot\n\nChange-Id: I4e50df6d6511e0ecd1ead96c67247e433fbf271a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73483\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c1fa3418ad546f1c6029174fa2f75c0e6b48e7a2", "tree": "8d55916f42b24d8c68905ab901181594de33290a", "parents": [ "c152f53a12c11f9effe08671d9366d11a0a6587d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 23:56:12 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:48:20 2023 +0000" }, "message": "chipset_enable: Add a line break in debug output\n\nIf loglevel is \u003e\u003d debug, we should end all lines at\ninfo level with a line break.\n\nChange-Id: Ibf85869a9156facda58c5fb6a0a558d124ffd2b8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72586\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "96f964b419845e185ccd718d46dc38751fbc7967", "tree": "468e7139c3ad9d88758ab555b3f1b288d99a5b47", "parents": [ "4d51e07242459f86d00eaf522786695e46ec2511" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 23:47:51 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "chipset_enable: Mark AMD Pinnacle/Raven Ridge and Matisse as DEP\n\nTested Pinnacle Ridge and Raven Ridge on an ASRock A320M-HDV and\nMatisse on an ASRock A520M-HDV. Because there can be access pro-\ntections set up in the chipset, mark them as DEP.\n\nChange-Id: Id389786d2b2dcea0141322c94ac72e03161019db\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73157\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e3c305dfd234503faa23c5491962db8f52d0134c", "tree": "b86a019224a05586e18b98eae8ff0c9b51a1c701", "parents": [ "070587892b4af723bf8f1f423d0b26e12e061084" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 21:45:56 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Implement memory-mapped reads\n\nQuery the RomRange2 register for the memory range (usually top below 4G)\nand try to map that. Reads outside this range will still be served via\nthe command engine.\n\nChange-Id: I21aa67d550ccda0f55a9cf3ff14545a881624d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72583\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "735b186eeffb997a957075d7e610b9700b53cbe1", "tree": "1e27f0dc7f2cae492459530df208859221a1d3ca", "parents": [ "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 18:28:45 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Add new driver for AMD SPI100 controllers\n\nStart with a very simple PIO driver. Reads are slow this way, but\nwe can optimize that later. A factor of 2 is possible simply by\naligning the FIFO reads, and another factor of 3 (at least) with\nmemory-mapped reads.\n\nWe override the SPI speed but choose a conservative value to be\non the safe side. Flashrom only supports normal read commands,\nhence we won\u0027t go over 33MHz. Also, if the firmware set a lower\nspeed for normal reads, we use that. We can\u0027t use dual/quad I/O\nwith the SPI command engine, and tests have shown that increasing\nthe SPI speed lifts the read speed only marginally. It seems to\nbe limited by the FIFO reads.\n\nChange-Id: I403d5f103b3ae72f3a91829d562984c54c2e2d00\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72577\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "78cd559d0eebeb2e725f19db89ab2f11aac05613", "tree": "6c7e68cca1b199aec9d6a9fce34da32171f12f8f", "parents": [ "e604d56cf5654db8b744cbe5fb4fdb5fbfecd4e8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 18:24:34 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Start new driver for AMD SPI100\n\nWe start with the known fam17h PCI devices. Handle what we can gather\nfrom the LPC device and then hand over to a to-be-written SPI driver.\n\nChange-Id: I8215d2bf30ac95ec2258f28267edfdb7af569bea\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72576\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e604d56cf5654db8b744cbe5fb4fdb5fbfecd4e8", "tree": "997104c21770b3a847d438004873691b39aea898", "parents": [ "019810f3fd083df5f6f61d19dda2d252709d02fe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:34:57 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Split detection for AMD Merlin Falcon and Stoney\n\nSplit the chipset enable entries because future SoCs use the same\nPCI IDs. We use the SMBus device for this, just like `sb600spi`.\nHowever, as the latter expects the LPC device to be passed, we\nhave to look that up first.\n\nChange-Id: Iba02d8695d150f9be51c996932b845a487b0e4ce\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72574\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "019810f3fd083df5f6f61d19dda2d252709d02fe", "tree": "d9f2f1e6f8e10b6bb1d4b7f56f431f9073942fbc", "parents": [ "6d98aece44f6f3458c79160adf4dddc7f8500378" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:11:24 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Optionally check PCI revision field\n\nWe used to match compatible chipset devices by vendor and device ID\nonly. On some chipsets, e.g. AMD southbridges / SoCs, this is not\nenough, though, as the device IDs are rarely updated.\n\nIn the case of AMD chipsets, we can identify the chipset with the\nrevision ID of the SMBus device. So we add that field to the chipset\nenable list.\n\nChange-Id: I4021cf8e83c605fde4360c274b39481b1e0ff070\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72573\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f8d9a272845cd96cf5a33560fe0b4ad54a13bfc3", "tree": "b2cdc0459a6c7e99fcf925c05c309273e6b0e446", "parents": [ "5194d589bfc637fef26073252f312c853895eab9" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Wed Mar 16 09:19:19 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess_x86_msr: rename msr function to msr_xxx\n\nThis eliminates the need to redefine the rdmsr and wrmsr symbols,\nresulting in more understandable code. The common prefix clarify the\nrelation between the functions.\n\nChange-Id: Ie5ad54d198312578e0a1ee719eec67b37d2bf6a4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62851\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72318\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "19ce50d3746fb1d9e5238bac49cf88ffe654848e", "tree": "90852ac71da4bc563f5bda33dd2954cd990f1d4b", "parents": [ "6c73e27aa68e0e100f6573cd0910f6f54bff271d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:59:18 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_dev_find() from internal to canonical place\n\nAlso rename to `pcidev_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: Ie21f87699481a84398ca4450b3f03548f0528191\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72310\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48a946673fa770a9224c2b79a8f8440c51b109ed", "tree": "62f3bd1fee1f4e6cf45d42011d2dcbb435ca028e", "parents": [ "15004ba11d6c3b86c7824bb30a630c81e94cc9a4" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Feb 26 11:36:17 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move scandev_inclass logic from internal to pcidev\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: I1978e178fb73485f1c5c7e732853522847267cee\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "df3672d08beb0d1946dccc702fc4df75b051cd22", "tree": "c4996a38aa040f3824f9360f698b89e3265cb369", "parents": [ "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77" ], "author": { "name": "Peter Marheine", "email": "pmarheine@chromium.org", "time": "Wed Jan 19 17:11:09 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: fix build on non-x86 targets\n\nThe changes to hwaccess in commit 49d758698a0d (hwaccess: move x86\nport I/O related code into own files) cause build failure on non-x86\nsystems because the hwaccess_x86_* headers are included in some files\nthat are built for all platforms (particularly those in the internal\nprogrammer) and those headers in turn include \u003csys/io.h\u003e which only\nexists on x86.\n\nThis change avoids including those headers on non-x86 platforms so\nthe internal programmer can be built without errors.\n\nThe comment on the stub implementation of rget_io_perms() is also\nmodified to remove references to non-x86 platforms, since that file is\nonly built on x86 now.\n\nTested: meson build succeeds for both x86 and ARM targets\n\nSigned-off-by: Peter Marheine \u003cpmarheine@chromium.org\u003e\nChange-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61194\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72279\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77", "tree": "ae3340f0a563d1d9ed48285cc861e7e90e2343ef", "parents": [ "a6b45c4516e15aeb405028e5095e86259fcd9e34" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Jan 17 15:11:43 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move mmio functions into hwaccess_physmap\n\nThe mmio_le/be_read/writex functions are used for raw memory access.\nBundle them with the physmap functions.\n\nChange-Id: I313062b078e89630c703038866ac93c651f0f49a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72278\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "74b4aa0b15439a2ab2474889a7abed978439757a", "tree": "a3e6d01052b04bbae7c71af7c1148d3619ba1ab1", "parents": [ "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:52:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "physmap: rename to hwaccess_physmap, create own header\n\nLine up physmap with the other hwaccess related code.\n\nChange-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4", "tree": "5432e2d6675b9f389ad95bf47f4e2e7decd5807f", "parents": [ "a065520a7c7eedcca961de1fc891cc0b04e6df77" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:25:49 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess physmap: move x86 msr related code into own files\n\nAllow x86 msr related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nflashrom-stable: Squashed fixup for FreeBSD\n\nChange-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60111\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72266\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a065520a7c7eedcca961de1fc891cc0b04e6df77", "tree": "f7a4c280f6d3114b98a52e147f988c4ae293271b", "parents": [ "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 16:36:05 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move x86 port I/O related code into own files\n\nAllow port I/O related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nChange-Id: I372b4a409f036da766c42bc406b596bc41b0f75a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60110\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72265\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698", "tree": "2ca206a0bb2873472e243eb2138c7f1e0345abf2", "parents": [ "b7c6a66d5167a9cb6d83081f4c84b7a6c0d28046" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Nov 02 21:03:00 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pci.h: move include into own wrapper\n\nSplit the include of hwaccess and libpci. There is no need to have pci.h\nincluded in hwaccess.\n\nChange-Id: Ibf00356f0ef5cc92e0ec99f8fe5cdda56f47b166\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58883\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72264\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ac90af6cdc747bfe3dc38c83c0b7272addf37659", "tree": "ec67fd7c4d01db82b5a1ffd8c8ed36a7229108dd", "parents": [ "bb4f3b06dcfb60a6ab84750c9b149482dc5ee579" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 18 00:22:47 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:34:15 2023 +0000" }, "message": "Change references to flashrom-stable\n\nAdapt all mentions of the mailing list and also the version print.\n\nChange-Id: Ib4a3271422ee6cf4d0efb8c3fa858b66a22c0a33\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70922\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0c8221bb4462d7410a4667ab3526502c5eaa241d", "tree": "f2264704cde0950882873089f8c8d16154c401a1", "parents": [ "e28d8e4e2332054fb4b7f61e8ce03f316e3a63f3" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Thu Oct 20 21:23:33 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "chipset_enable.c: Mark Intel C246 as DEP\n\nTested reading, writing and erasing the flash chip of a Prodrive\nHermes mainboard with an Intel C246 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I07d6c4a60e468c61eba836db91e1335f4a762048\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68594\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71493\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1ab7d2bb0c4ea7be2e251caa564ab91d27ee7ea", "tree": "905816b92fb3759fcb82767cb94b49d6e0f02594", "parents": [ "8cfc7377ffa880659660b344e97333986aba9130" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 03:03:47 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `laptop_ok` with bool\n\nUse the bool type instead of an integer for the variable `laptop_ok`,\nsince this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I5d9fc3516bc2d29f11b056e35b3e5e324ce93423\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66891\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "980d6b8d712d26711dcd5a71007e4626c7198cd5", "tree": "38e926243e6a10734971066fd1602d373fd04784", "parents": [ "f25447e5724bd8664338b69b12399f101abed76b" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 02:48:15 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `programmer_may_write` with bool\n\nUse the bool type instead of an integer for the variable\n`programmer_may_write`, since this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I69958527ae018a92f1c42734a7990d0c532dee0c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71483\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "756b6b32e2a49c487d4bbc42d370e8826b41c922", "tree": "ce4db0712ab0fba0c5bed684ca67e012a2f2807d", "parents": [ "15095dbb7b9d7f1938d43e5ff3b99054b0798803" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 21 17:15:13 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Add Intel Jasper Lake support\n\nLoosely based on commit b01d7e9f (ichspi: Add Jasper Lake support)\non flashrom master.\n\nBesides a little change in descriptor detection, no difference to\nCannon Point was found. Hence, add new PCI IDs as 300 series.\n\nChange-Id: I9c715c1a5f1ceea32dc51669453d89b315ba8ca2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71453\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "29c23dd08474b2457ffd8a72ee3d8587676cd999", "tree": "73ccbc237df969f57ad5c9f7e044e0d4b9ca2656", "parents": [ "8efb0b337a46aaa5f2da902aa862d30e6a1305be" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 21 15:25:09 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Add Alder Lake support\n\nLoosely based on commit 11680db4 (ichspi: Add Alder Lake support)\non flashrom master.\n\nBeside a little change in descriptor detection, no difference to\nTiger Lake was found. Hence, add new PCI IDs as 500 series.\n\nChange-Id: Icc1278755ff64f03128d8faadbca85a4ff76864d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71448\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e57d4e49fd2556f0fe267833d35cc57b7e252c06", "tree": "ef260430367f0d2025fd6c5c12c101f37639613e", "parents": [ "672bdcfd4ffeb065b7056042769e3cc512d87c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Mon Jan 03 09:44:29 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Elkhart Lake support\n\nElkhart Lake has a chipset called Mule Creek Canyon which is quite\ncompatible with 300 series chipsets. There are a few differences though,\ne.g. different encoding for the SPI clock values for read and write in\nthe FLCOMP register. In addition Elkhart Lake has a new PCI device ID\nfor the SPI controller which is added, too.\n\nTested: Read and flash complete flash on Siemens MC EHL1\n\nChange-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fafc3d8048d9e26b708323805868d127eeecc12e", "tree": "dfe8d02595cde3456708d263a01033ba9754efac", "parents": [ "6ae640b1f33464969d401e00b44b3b5157f1ce09" ], "author": { "name": "Tim Crawford", "email": "tcrawford@system76.com", "time": "Wed Nov 17 06:23:25 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add TGP-H IDs\n\nAdd IDs for: H510, B560, H570, Q570, Z590, W580, HM570, QM570, WM590\n\nTested on system76/oryp8 (HM570). flashrom is able to read the image\nusing the internal programmer.\n\nChange-Id: I96f63253d42578151f99dcbb42347afecc03f49d\nSigned-off-by: Tim Crawford \u003ctcrawford@system76.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57533\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Benjamin Doron \u003cbenjamin.doron00@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71440\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "69c324a7d4015c3ca4ba8d39a1c42670369f5afb", "tree": "c24c0bbe9512d67ed1daa9f919beeea00672441e", "parents": [ "5c9f542bf8ce514c628c59e42e35fbcb615d8937" ], "author": { "name": "melvyn2", "email": "melvyn2@brcok.tk", "time": "Sat Oct 30 16:02:22 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Mark Intel Z390 as DEP\n\nTested read/write on GIGABYTE Z390 AORUS MASTER, incl. ME region with\nme_cleaner.\n\nChange-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nSigned-off-by: melvyn2 \u003cmelvyn2@brcok.tk\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58774\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71438\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937", "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744", "parents": [ "cce1e5b8636ebef59dd509680594e17b0a207857" ], "author": { "name": "Michał Żygowski", "email": "michal.zygowski@3mdeb.com", "time": "Wed Jun 16 15:13:54 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "eec477f1a6f4ba718e713438532c81d9a9b7db72", "tree": "ee51926458b3f9fcc18fc81a74f6fc3be2fc90a5", "parents": [ "a4e63e7957c5eb41d9e0dc237949102795494f31" ], "author": { "name": "Sophie van Soest", "email": "sophie@entropie.rocks", "time": "Sun Jul 04 13:54:26 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Mark Z97 as DEP\n\nTested on GIGABYTE GA-Z97-HD3.\n\nSigned-off-by: Sophie van Soest \u003csophie@entropie.rocks\u003e\nChange-Id: I73bdd9afefae8e7c013d400e17a15e56d84322f4\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56060\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71421\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3bf7cfba9fca9b18d4ad5b843399bc00a3be1f49", "tree": "cc4c65492591a94835ad9a0c9617084ec8ab006e", "parents": [ "66565a7953b27a55cd963bb4f608c08f7d5237f0" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Mon Aug 30 23:25:06 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add support for Intel Emmitsburg PCH\n\nThis patch does the following:\n- Add PCIe ID for Intel Emmitsburg PCH\n- Based on ICH descriptor content, choose CHIPSET_C620_SERIES_LEWISBURG\n if ISL/PSL is 80.\n\nTested: tried on a server with Intel Emmitsburg PCH, flash update\nwas successful. This server, however, does not have flash chip\ninstalled, it instead has em100 emulator connected.\n\nChange-Id: I2a1bb7467e693d1583aa885fa0e277075edd4a3e\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nSigned-off-by: David Hendricks \u003cddaveh@amazon.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54965\nOriginal-Reviewed-by: Christian Walter \u003cchristian.walter@9elements.com\u003e\nOriginal-Reviewed-by: Johnny Lin \u003cJohnny_Lin@wiwynn.com\u003e\nOriginal-Reviewed-by: Tim Chu \u003cTim.Chu@quantatw.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71419\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1c7297fdbb34c6d211a31b4071c232d7e053289a", "tree": "141678ce4577d4743df0808f550b43329c7fd884", "parents": [ "4db0fdfdcb59f94e41c0967375c899e2d274e113" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon May 17 10:50:40 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add Gemini Lake eSPI PCI device ID\n\nTaken from coreboot `PCI_DEVICE_ID_INTEL_GLK_ESPI` macro, untested.\n\nChange-Id: Ie34527e56edcba4982f17b8e0aef0fc4280a52bc\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54354\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71355\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113", "tree": "5866347a6c5e63477f8e05cc32443085319c2df3", "parents": [ "771bb7952a91722d2d9f100e19b0566f06298126" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 10 17:04:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b499b67d1b112141792a71ad9119d51dd9052684", "tree": "e1477a95f0987cdaf6a4a9f1c774d7bbb7f9773b", "parents": [ "bc0285c9b3e6faa8538cb0d2a1d50c158a955919" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Thu Apr 22 17:08:00 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add IDs for H310C and B365 PCHs\n\nThe device ID for H310C can be found in Intel document 335192-004, but\nthe device ID for B365 is not there. Other sites list these IDs:\n\nhttps://linux-hardware.org/index.php?id\u003dpci:8086-a2ca-1462-7c09 (H310C)\nhttps://linux-hardware.org/index.php?id\u003dpci:8086-a2cc-1849-a2cc (B365)\n\nBoth of these PCHs have been tested as well.\n\nChange-Id: If9f0a49a0f1821e5592213e07962ee48654cdc07\nOriginal-Tested-by: Timofey Komarov \u003chappycorsair@yandex.ru\u003e\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52605\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71349\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bc0285c9b3e6faa8538cb0d2a1d50c158a955919", "tree": "af7580298b29c029ef14f10b837388c16ee3c5a9", "parents": [ "d493baaa0c21c3b3f648b0349104978f4f589a33" ], "author": { "name": "Gaggery Tsai", "email": "gaggery.tsai@intel.com", "time": "Thu Dec 12 11:52:03 2019 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add CMP-H IDs\n\nThis patch adds CMP-H support. They are HM470, WM490, QM480,\nW480, H470, Z490 and Q470.\n\nTested: build flashrom and run on CML-S with CMP-H\n flashrom -p internal -w ./coreboot.rom\n reboot and check the code is flashed correctly\n\nSigned-off-by: Gaggery Tsai \u003cgaggery.tsai@intel.com\u003e\nChange-Id: Ic7f04fc5cbe3422cbd219c46586c32fc847c921f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/37677\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Tim Crawford \u003ctcrawford@system76.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71348\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d493baaa0c21c3b3f648b0349104978f4f589a33", "tree": "0ff6e28d593d487cc3b6da1265827b8d740c76fc", "parents": [ "0be623c3d88bef4c37d546e0970b0e8ac890be24" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.io", "time": "Sat Mar 06 21:14:39 2021 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable: Mark QS67 as DEP\n\nTested on MacBook Air 4,2.\n\nChange-Id: Ia31c9d336d6ffe441323616174018b0f6a8897bd\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51320\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71347\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7630390672170718d6114f1439705d03765ac036", "tree": "266da495f6b51660caaa5110c45abe49d96a6715", "parents": [ "198bef39367088df36c88ecf93bd3b900a597735" ], "author": { "name": "Sam McNally", "email": "sammc@chromium.org", "time": "Thu Mar 11 11:41:46 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add PCI ID for Comet Lake U Base\n\nTested: `flashrom -r` on a kindred chromebook with a Celeron 5205U.\n\nChange-Id: I627dcacdad167343287ac0ec26b47505c2f823ee\nSigned-off-by: Sam McNally \u003csammc@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51401\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71341\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "198bef39367088df36c88ecf93bd3b900a597735", "tree": "d4310f2f5618c92bd7dbada59a5015ed6a8d38f7", "parents": [ "9eeae3328682feadb663490eafaa26ee15cc0003" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Sat Feb 20 10:51:56 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel C216 as DEP\n\nTested reading and writing internal flash on HP Z220 SFF.\n\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nChange-Id: I97538577c32e6c40374c414f005eb3165ed2e11d\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/50986\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71340\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "abb34fee66dc5255ac0ae770eb3d7f1c28f7b792", "tree": "af60db80459aba40d14cc08af031149c95ec598e", "parents": [ "2bb6792361f66a78473212d4dcddfe69d7b88aad" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Dec 06 23:09:13 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Intel H110 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\n280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71333\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2bb6792361f66a78473212d4dcddfe69d7b88aad", "tree": "95924eefb318626978a4ee525f56ce2d123dfeac", "parents": [ "0a84d0d6950fef06ea0c0b0d220f9a97d2a958f0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Nov 03 17:19:52 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: mark \"Broadwell U Base\" as DEP\n\nTested probe/read/erase/write operations succeed with cros\nflashrom on rikku chromebox. Marking as DEP to follow\nconvention for ME-enabled chipsets.\n\nTested: Applied patch to cros flashrom and verified that\n`flashrom -VV` no longer prints a chipset warning on rikku\n\nChange-Id: I0b4d1dd2b271537faea15856442fe183d9de3318\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71332\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3b3fc9344d6cfd29007545826ecaf1e483b4bed4", "tree": "e249fbe857aee081ed4cdd2bf35feafac056673f", "parents": [ "55f6564524189f99097b3c6525b1b339a72cd063" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Nov 20 10:05:29 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Intel Q67 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nElite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47797\nOriginal-Reviewed-by: Frans Hendriks \u003cfhendriks@eltan.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71330\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "55f6564524189f99097b3c6525b1b339a72cd063", "tree": "640e378ca1287a26f1a91ff4c0f088a84a7fa6bf", "parents": [ "0ad11992be40c7e1e9b8a1f45a48a3e5362f6f7c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Nov 02 14:43:10 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add Intel pch7 did\u003d0x1e4{1,2,3} support\n\nModified to be pch7 over pch6 as per-coreboot and review\ncomments.\n\nChange-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71329\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "4f29bb799b4672eebcc0bdfc6fb544b2b5544b6f", "tree": "8a27542cc468d103319c7c36afe894f57870f59a", "parents": [ "c753c40971c1481943e8a18dc24b33037e2a579d" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@gmail.com", "time": "Wed Aug 12 12:48:06 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "Add support for Comet Lake-U/400-series PCH\n\nAdd enum CHIPSET_400_SERIES_COMET_POINT and treat it identically\nto CHIPSET_300_SERIES_CANNON_POINT.\n\nAdd PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT.\n\nTest: read/write unlocked CML-U board\n\nflashrom-stable:\nAs suggested above, treat it the same as 300 series. But don\u0027t add a\nnew enum.\n\nChange-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71325\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1592fe589725cccbc72db60fdb1858b6edb7432c", "tree": "caf214baffdfd692575632e27eec9c20b128f780", "parents": [ "c218a053aafbedc985ba448d9a1430116d38ad9b" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Aug 28 12:48:32 2020 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel Q77 as DEP\n\nTested reading and writing internal flash on Dell Optiplex 9010 SFF.\n\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nChange-Id: I4717959be1b79aa986f1276589d01ce7475bda8f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44910\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71320\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "c218a053aafbedc985ba448d9a1430116d38ad9b", "tree": "ab4cc37bd2680e2c5c0337c1e580801ec7e009b0", "parents": [ "9f0641960c4b3a4d71d5876b12e9c1e354bec139" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Wed Aug 19 12:16:40 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "add PCI IDs for additional c620 series PCH chips\n\nAdd PCI IDs for C621A, C627A and C629A.\n\nChange-Id: I636becd9f08bdf604c6af81ce396049655353b04\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71319\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "9f0641960c4b3a4d71d5876b12e9c1e354bec139", "tree": "8149dd59cba3645b9ea66faae3f2f1168f10f6b3", "parents": [ "5c639b32004925ae89ac6eb654344bad21cea9ef" ], "author": { "name": "Luka Kovacic", "email": "luka.kovacic@sartura.hr", "time": "Thu Jul 30 13:31:15 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller\n\nSupport for the Intel C620 Series Chipset SPI Controller (rev 04) is added\nto enable SPI flash access on the following platform:\n\n- Intel Xeon D-2187NT\n\nSupport for this controller was shortly tested on the platform above.\nThe flash is recognized, some regions of the flash are locked.\n\nSigned-off-by: Luka Kovacic \u003cluka.kovacic@sartura.hr\u003e\nOriginal-Tested-by: Jakov Petrina \u003cjakov.petrina@sartura.hr\u003e\nCc: Luka Perkov \u003cluka.perkov@sartura.hr\u003e\nChange-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71318\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1f967c8acf61e2cc0d5e53c50bae11513a16755c", "tree": "3a38c1422300513fe68cbeafbd76603290abcd23", "parents": [ "7a6bce62a7b178c141a4dfc5e73b6b9ad80db84e" ], "author": { "name": "Jan Samek", "email": "jan.samek@siemens.com", "time": "Wed Jan 08 12:35:14 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: add PCI ID for APL-I (Broxton)\n\nChange-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324\nSigned-off-by: Jan Samek \u003cjan.samek@siemens.com\u003e\nSigned-off-by: Henning Schild \u003chenning.schild@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71315\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "abefc466e311de6b33eb0e0cf25fb72e558cc805", "tree": "620b775973797a6ec3312d9af47be0d509de3a81", "parents": [ "6d42d2ba8c718c5123286401bbcc61b0142aecef" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 29 15:23:59 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Spell `BIOS` in uppercase\n\nIntel document #336067 uses `BIOS Control` to refer to this register.\n\nChange-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Marcello Sylvester Bauer \u003csylv@sylv.io\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71309\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "77a2a6e43576ab3c3b31263ec7464e30fa62b44d", "tree": "f4440424307f96043492269721d81ce396b19ef0", "parents": [ "a9335cc637c4d96ec37d8965628efbc0a7eb233a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Mar 23 16:05:07 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add more Lewisburg PCH IDs\n\nChange-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39780\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71304\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a9335cc637c4d96ec37d8965628efbc0a7eb233a", "tree": "0a5527d8e79de6d9c86848c87a88b3b5868b7853", "parents": [ "7113d17adc9f51400003bbdb4ed53e7b5d46b9dc" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Mon Mar 09 03:05:42 2020 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel HM75 as DEP\n\nTested reading and writing on a Samsung laptop (see CB:39388).\n\nChange-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71303\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7113d17adc9f51400003bbdb4ed53e7b5d46b9dc", "tree": "6e69cac79ec6a491aeef722d5536b604b98871a9", "parents": [ "de307c0d68ae46749a1dc392d983892b06f6a78a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sat Feb 29 23:13:43 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Skylake U Premium as DEP\n\nTested reading, writing and erasing the internal flash chip using an\nAcer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\n" }, { "commit": "2e3e10669d719545968ddec3b44b8a9363f4b432", "tree": "95f7807b9ec68fdc9d21590fc7c174ee0f391fca", "parents": [ "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Dec 02 13:17:46 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:24 2022 +0000" }, "message": "chipset_enable.c: Validate physmap() return rcrb value\n\nValidate the physical mapping in enable_flash_silvermont().\n\nChange-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67868\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d", "tree": "5541efefb64efc6611a315e12936608c37803c3c", "parents": [ "d92dd50bcac6b2d0dfffa9f983712f7400990f3d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Thu Oct 15 19:19:05 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:15 2022 +0000" }, "message": "chipset_enable.c: check return value from rphysmap() call\n\nPort from the ChromiumOS fork of flashrom.\n\nChange-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46444\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67867\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "399a4dd721a64a1d22e2f8028cc39d6496515ed6", "tree": "6a40ff5ca048148294b209d8cb99ab9558fdc44f", "parents": [ "b57f48f77f367c43cd83878d92aa55de151c0798" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 15 12:59:42 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:53 2022 +0000" }, "message": "chipset_enable.c: Disable SPI on ICH7 if booted from LPC\n\nCommit 92d6a86 (\"Refactor Intel Chipset Enables\") eliminated a check\nto disable SPI when ICH7 has booted from LPC, as the hardware does not\nsupport it. Therefore, when flashrom probes the SPI bus, it times out\nwaiting for the hardware to react, for each and every SPI flash chip.\nThis results in very long delays and countless instances of the error:\n\n Error: SCIP never cleared!\n\nTo prevent this, bring back part of the lost check. Probing for LPC and\nFWH when booted from SPI does not seem to cause any problems on desktop\nmainboards with ICH7, so don\u0027t disable LPC nor FWH if that is the case.\n\nTested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.\n\nChange-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40401\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67863\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b5433b782ff7cbde14ebd91aeac27efaec83e9d0", "tree": "facd5500f80682ce09fe7135362df5f4e7a87609", "parents": [ "3eae69531936cc41f227a532efea4cc3598d0f68" ], "author": { "name": "Johanna Schander", "email": "git@mimoja.de", "time": "Sun Dec 29 15:16:14 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:00:51 2020 +0000" }, "message": "chipset_enable.c: Add Ice Lake U to known and tested systems\n\nIntel Ice Lake systems use an 495 Series Chipset\nthat behaves compatible to pch300 chips but chip names\nare undocumented at this point.\n\nThis change was tested in read/write/erase on the Razer\nBlade Stealth (late 2019) with intel 1065G7 CPU and\n\"Ice Lake U Premium PCH\".\n\nChange-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15\nSigned-off-by: Johanna Schander \u003cgit@mimoja.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37987\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Christoph Pomaska \u003cgithub@slrie.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3799a1cc1adda28bb8bd4464020a7bbadd3960f1", "tree": "d654267ccdf97429733da5e0c07560be27a9d6f1", "parents": [ "e4c2b48f39902c7ff49a6a9e29525bdd3092c412" ], "author": { "name": "Wim Vervoorn", "email": "wvervoorn@eltan.com", "time": "Mon Jan 20 15:01:54 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 22 14:15:33 2020 +0000" }, "message": "chipset_enable: Add Kaby Lake U Prem. to known and tested systems\n\nIntel Kaby Lake U (with the 9d4e device id) support is available but\nmarked not tested.\n\nTested reading, writing and erasing both internal flash chips on the\nFacebook Monolith system with the Intel i3 7100U SoC. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall follow\nsuit as well.\n\nSigned-off-by: Wim Vervoorn \u003cwvervoorn@eltan.com\u003e\nChange-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38481\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53", "tree": "8df82988b92b7b091358e72570671d908016a08a", "parents": [ "a9d6d1a817ce20e834fe7c354629976e3e5f1108" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Dec 18 00:26:15 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 21 11:47:21 2019 +0000" }, "message": "chipset_enable.c: Mark Intel HM76 as DEP\n\nTested reading, writing and erasing the internal flash chip using a\nSamsung NP530U3C laptop with an Intel HM76 PCH. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37803\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "d58128eb83e59e09113666c80da81c891d76e949", "tree": "8ef79ded03a5d02eac66c0dde923a24fcd8408b2", "parents": [ "9e2dc2fc818cc9c1b46924e103ce669ad154b7ab" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Oct 06 21:07:44 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 08 09:59:22 2019 +0000" }, "message": "chipset_enable.c: Mark Intel Q75 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nPro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35826\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ea0c093246fbaba9ab89348400ba4e99032aa4e0", "tree": "f5982cd4b2d3e207d064612083a286fcd5ad5cfc", "parents": [ "bde44a1989342859240c6993d1f782945bb4ce94" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 17:34:16 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:33:25 2019 +0000" }, "message": "chipset_enable: Mark Intel CM236 and CM246 as DEP\n\nThe usual ME-lock limitations apply, so this is DEP instead of OK.\n\nTested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also\nregression tested on Apollo Lake. Flashrom works fine, and logs and\ndescriptor dumps look good. Also, register and descriptor output\nagree on the flash layout and permissions.\n\nChange-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34073\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "bde44a1989342859240c6993d1f782945bb4ce94", "tree": "8887b05e3561727001e0dd6ad14ee1d040ff9ee3", "parents": [ "2a5dfaf140eb8f22c923a026df855da0c5e9bf82" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@puri.sm", "time": "Thu Jul 04 17:52:40 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:46 2019 +0000" }, "message": "chipset_enable: Add support for Cannon Lake U Premium\n\nAdd support for Cannon Lake U Premium (CFL-U/WHL-U).\nSame as discrete 300-series CNP PCH.\n\nTested on a WHL-U laptop w/unlocked IFD.\n\nChange-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@puri.sm\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34076\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "a508ca0acdc5cbd0ae8c2342d865d363ef24f185", "tree": "8fe50245d5bb3b8817427287510f199df1015e73", "parents": [ "519be66fc59558971dd653afe69ccaf1a633b492" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 24 19:34:43 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:27:57 2019 +0000" }, "message": "chipset_enable: Fix recent -Wmissing-field-initializer trouble\n\nChange-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "d2d3993a25c3236d397209f9c2118c3b17ce4f95", "tree": "8c91f0f2d588e66963c13e48dd972de555985bf4", "parents": [ "3750986348cb99b8f0d828b73972b545a2f9c878" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 16:49:37 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:23:53 2019 +0000" }, "message": "ichspi: Add Apollo Lake support\n\nIt\u0027s almost identical to 100 series PCHs and later. There are some\nadditional FREGs (12..15). To not clutter the `if` conditions further,\nmake more use of `switch` statements.\n\nTested on Kontron mAL10. Mark it as DEP as usually the last sector\nis not covered by the descriptor layout and can\u0027t be read.\n\nChange-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30995\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3750986348cb99b8f0d828b73972b545a2f9c878", "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315", "parents": [ "908adf4589d34eaf3bd8395afa52aed8c8887cfd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 14:23:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:15:58 2019 +0000" }, "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "17890b37f362e551e886506f39e7bf7181419457", "tree": "9278586896099d40869319f64cd3124e1c4f902a", "parents": [ "f9632d82634bbbdc7e90357d3ea7c4a631ab4376" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Sun Jun 02 23:07:52 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 03 20:21:58 2019 +0000" }, "message": "chipset_enable: Mark Intel QS77 as DEP\n\nTested reading and writing with `-p internal` on MacBook Air 5,2 with\nIntel QS77.\n\nChange-Id: I508b6379507c2881c976d6baf7348b1161449cfe\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33164\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cacb11c6252b6e1f4f0a2a33b47717ff22995d9", "tree": "062ee516f90ae51baf0f5c0f8ffe27c8c91bc4bb", "parents": [ "1cf369fb59546e705c5ca9368e629681c98b2893" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Feb 04 12:16:38 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 04 15:46:25 2019 +0000" }, "message": "Remove trailing whitespace\n\nChange-Id: I1ff9418bcf150558ce7c97fafa3a68e5fa59f11e\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/31227\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "099c8b2d5faae4d7f49c01c856f78398b743baa3", "tree": "738cd19feef5a59b0b4b8cfaf9beac3ed9145a67", "parents": [ "e7cbfae69e2bdf22018f14fbaf076a78995a2b60" ], "author": { "name": "Tristan Corrick", "email": "tristan@corrick.kiwi", "time": "Sat Dec 22 00:41:54 2018 +1300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 13:07:34 2018 +0000" }, "message": "chipset_enable.c: Mark Intel C224 as DEP\n\nTested on a Supermicro X10SLM+-F. The flash chip has been read, written,\nand erased many times without issue. Most boards with this chipset will\nhave the ME region locked, hence the selection of DEP.\n\nChange-Id: I25126b94e691289a7b29dd81d5c864854a4e0245\nSigned-off-by: Tristan Corrick \u003ctristan@corrick.kiwi\u003e\nReviewed-on: https://review.coreboot.org/c/30361\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7fb508dc137818587bf142ec1f28fbc1c3a371fc", "tree": "10d295db825b47c407d21f37e66bb4b7eff9e40a", "parents": [ "f2cd32570eb8624c60e97aecd5c9045249b376fe" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Nov 02 14:25:31 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Nov 03 11:33:25 2018 +0000" }, "message": "chipset_enable.c: Mark Intel PM55 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nPavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since\nall ME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/29437\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c4e9fd0abc51959885aafe6312a2d8c9b3935434", "tree": "d04cdf7484dac323c64eff0ec80526d26e2f3aa5", "parents": [ "61818dc098edf3bf41f2d6502456fe0cd078c007" ], "author": { "name": "Tristan Corrick", "email": "tristan@corrick.kiwi", "time": "Thu Nov 01 00:33:57 2018 +1300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Nov 01 11:06:07 2018 +0000" }, "message": "chipset_enable.c: Mark Intel H81 as DEP\n\nTested on an ASRock H81M-HDS. The flash chip has been read, written, and\nerased many times without issue. Most boards with this chipset will have\nthe ME region locked, hence the selection of DEP.\n\nChange-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4\nSigned-off-by: Tristan Corrick \u003ctristan@corrick.kiwi\u003e\nReviewed-on: https://review.coreboot.org/29391\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73ab88d58ee6ca1f0a822faafe0b14996e65ddbf", "tree": "bd539c80e1d257465ab421de57c8f0118be8f273", "parents": [ "f112e242ab84534eee1b8e90e9cd6302a0db742f" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Oct 07 13:07:55 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 08 11:59:15 2018 +0000" }, "message": "chipset_enable.c: Mark Intel HM65 as DEP\n\nTested reading, writing and erasing the internal flash chip using a\nToshiba L755 laptop with an Intel HM65. However, since all ME-enabled\nchipsets are marked as DEP instead of OK, this one shall follow suit as\nwell.\n\nChange-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28955\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2f1d0076b3e3b8a85ae0e698949079305cac87a2", "tree": "3654cda71f7827f494b2817632edc705ae2ae11a", "parents": [ "1a7fb6e0c327bc23290ad02a2b97410f15fdde4a" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Oct 04 10:42:42 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 05 11:36:07 2018 +0000" }, "message": "Remove unneeded whitespace\n\nChange-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/28707\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c4d3efbffdf22367c71ec712c828969aafadab54", "tree": "5d58335b26f0643e815664fe7eda48ff47c0ae01", "parents": [ "3130cbd89b14bf29da32a9c151a4a633fb023e54" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Sep 30 19:39:41 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 11:50:51 2018 +0000" }, "message": "chipset_enable.c: Mark Broadwell U Premium as DEP\n\nAs per Laurent Grimaud on the mailing list. I also have said chipset.\nSince all ME-enable chipsets are marked as DEP instead of OK, this\none shall follow suit as well.\n\nChange-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28817\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ccfa8f9d9a68b1e4238d2dbbc4e9c8bcf9bae8a6", "tree": "d8b4b128709d5c5173269494c56d388c8e8434dd", "parents": [ "e2c90c45f7d1dbdd02269f0a8f3c95cb8ee5fa91" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Aug 21 03:30:58 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Aug 22 10:26:51 2018 +0000" }, "message": "chipset_enable.c: Mark Intel HM55 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\n630 laptop with an Intel HM55. However, since all ME-enabled chipsets\nare marked as DEP instead of OK, this one shall follow suit as well.\n\nChange-Id: Iaedd5bdc34dfff9b8588a3f4e1ad46460077fdf9\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/28253\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ac01baa073b0f154ffd3ffdc7c9e75987f8b525c", "tree": "c81104f7a8f08db2c6f0cc5d59f8f0e3fe7ea494", "parents": [ "b0247b3acbc7d8d9f8da1db48a9b81c5f2e24a38" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon May 28 16:52:21 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 24 13:44:51 2018 +0000" }, "message": "Remove unneeded white spaces\n\nChange-Id: I90f171924790ced74a62ca344fee8607607aa480\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/26652\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a50b8fde67fa52984980159127de789cf9a1c688", "tree": "cb7230f818fd01fd47e22de2258e1d6914528b74", "parents": [ "291c101c66adcb1c3435934f3f49fa7f24f7c249" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Mar 20 14:25:09 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 04 10:28:53 2018 +0000" }, "message": "chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs\n\nThe Kaby Lake \"200 Series\" PCHs [1,2] share the register layout of their\nSkylake \"100 Series\" siblings.\n\n[1] Intel® 200 Series (including X299) and Intel® Z370 Series\n Chipset Families Platform Controller Hub (PCH)\n Datasheet - Volume 1 of 2\n Revision 003\n Document Number 335192\n\n[2] Intel® 200 Series (including X299) Chipset Family Platform\n Controller Hub (PCH)\n Datasheet - Volume 2 of 2\n Revision 003\n Document Number 335193\n\nChange-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/26232\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b", "tree": "980f498681fcc053ec1e591e22bb16afbef0a191", "parents": [ "3f7e3419887c6d37330387f8e32c86ba47bdf70c" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Tue Mar 27 12:15:09 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:18:58 2018 +0000" }, "message": "Fix whitespace errors\n\nChange-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25380\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "305a2b3ed36ce87663aea177a806c6f435a4ceec", "tree": "a9dcc88821f3f7f8174c5ed1ba851f3522240b62", "parents": [ "2b5adfb1b656dd6a6efbf45a7a411c87840c5394" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Mon Jan 08 05:31:55 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 26 15:27:42 2018 +0000" }, "message": "chipset_enable: Mark VX855 as tested\n\nI can confirm a successful reading and writing of SST49LF080A (LPC) on a\nWyse Cx0 Thin Client (Phoenix BIOS 1.0G).\n\nChange-Id: I8f48b49ccb760f69d676ec6cbb233e532b12fbe8\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23158\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "73c882086fe7d6fac9859e2faa93ec56cc96b9bd", "tree": "b6f32ecc6126de577c687718c9810f5c1bfbd132", "parents": [ "d0803c8407c459e972cb9912a4a3cbfeebb93d9e" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Thu Dec 28 20:19:21 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:56 2018 +0000" }, "message": "chipset_enable: Mark VX900 as tested\n\nI can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550\nThin Client (AMI BIOS 786R9 v1.04).\n\nChange-Id: I190253b0c1920747b710ed7155e78191cce139eb\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23030\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d0803c8407c459e972cb9912a4a3cbfeebb93d9e", "tree": "7c361a17c153b09bf9da9ea685e29b4648118218", "parents": [ "aac81424ebb8234b54cbab8fe47350b562b84fae" ], "author": { "name": "Lubomir Rintel", "email": "lkundrak@v3.sk", "time": "Mon Oct 30 07:57:53 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:45 2018 +0000" }, "message": "vt_vx: check whether the chipset\u0027s MMIO range is configured\n\nAvoid attempting to read the SPI bases from the location 0x00000000, all\nzeroes mean that the chipset\u0027s MMIO area is not enabled.\n\nChange-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23029\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "bbf0dbde3855a58f7324dedb81fdcce0f99c1c87", "tree": "081df1b795f34cfe65e4d436dc076f967af10c8e", "parents": [ "1f33cb58001f95c3de69f037acae6f72baddca2b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 19 16:29:45 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Nov 21 22:29:27 2017 +0000" }, "message": "chipset_enable: Mark SiS 630 as tested OK\n\nTested on an Elitegroup P6STMT with an SST39SF020A parallel flash [1].\n\n[1] https://mail.coreboot.org/pipermail/flashrom/2017-November/015193.html\n\nChange-Id: If8cc2af262e392bfba326a62c1a48c658c7d6ce8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22522\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7b629bcde47e18d094e496fb8ae537272ead0998", "tree": "3c44a9d573fb61ca483054a845722e051558aefd", "parents": [ "8681df128708a548e64865bb6fd8f6cd957e061d" ], "author": { "name": "Ricardo Ribalda Delgado", "email": "ricardo.ribalda@gmail.com", "time": "Wed Mar 22 14:08:31 2017 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Sep 17 18:03:42 2017 +0000" }, "message": "sb600spi: Add support for Merlin Falcon Chipset\n\nThis patch has been tested on a board similar to AMD Bettong.\n\n00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus\nController [1022:790b] (rev 4a)\n00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC\nBridge [1022:790e] (rev 11)\nroot@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom\n\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at\nhttps://flashrom.org\n\nCalibrating delay loop... OK.\ncoreboot table found at 0x9ffd6000.\nFound chipset \"AMD FP4\".\nEnabling flash write... OK.\nFound Micron/Numonyx/ST flash chip \"N25Q128..1E\" (16384 kB, SPI)\nmapped at physical address 0x00000000ff000000.\nReading old flash chip contents... done.\nErasing and writing flash chip... Erase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21429\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1bccd88c3c8c0041795b96faef2cb4179bfbd7c", "tree": "f7dd8abd576d25c606508fa2ea6b4007b5b3d291", "parents": [ "4d440a7c4102faae21b16204e667ea74c1dc8e52" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Tue Aug 08 23:28:54 2017 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 19 20:34:34 2017 +0000" }, "message": "chipset_enable: Mark Braswell as tested\n\nReported by Uwe Vieweg:\nhttps://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html\n\nChange-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df\nSigned-off-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20923\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a54ceb1dbe76e76ca8701dbda3e5baf011b16d6d", "tree": "f27ce3b104511a8b1598e77858cb42b41cb5e515", "parents": [ "67d71792929f94d4638a3663f2fc19aea4918681" ], "author": { "name": "Youness Alaoui", "email": "kakaroto@kakaroto.homelinux.net", "time": "Wed Jul 26 18:03:36 2017 -0400" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 10 15:18:11 2017 +0000" }, "message": "rpci: Use pci_dev struct pointer to avoid API breaks\n\nThe pci_dev structure is never meant to be used as is, but always as a\npointer. By using the struct itself in undo_pci_write_data, we are risking\ndata corruption, or buffer overflows if the structure size changes.\n\nThis is especially apparent on my system where flashrom segfaults\nbecause I compile it with pciutils 3.3.0 and I run it on a system\nwith pciutils 3.5.2. The struture size is different and causes a\nstruct with the wrong size to be sent to the library, with invalid\ninternal field values.\n\nThis has been discovered and discussed in Change ID 18925 [1]\n\n[1] https://review.coreboot.org/#/c/18925/\n\nChange-Id: Icde2e587992ba964d4ff92c33aa659850ba06298\nSigned-off-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/20784\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "500263434b69594dc01b3ccfe5e2c4c498d87656", "tree": "e78ca90e544a00521dca899c5f9187ff57cc0250", "parents": [ "fa62294536a3ce5070e8d9065aaa1aa45031f910" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 18:24:32 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:30:48 2017 +0000" }, "message": "chipset_enable: Set 100 series chipsets to NT\n\nChange-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19047\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "93c306939b732fb05f6d8a692acc3fca78bc0f9f", "tree": "197478ba299562a8044c7d998c24e365af61b295", "parents": [ "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Mar 20 14:25:09 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:13:59 2017 +0000" }, "message": "chipset_enable: Add support for Intel Skylake / Kabylake\n\nAll publicly known Skylake / Kabylake / Sunrise Point PCH variants\nshare the same register interface [1..6]. Although all SPI configu-\nration is now done through the SPI PCI device 1f.5, we can\u0027t probe\nfor it directly since its PCI vendor and device IDs are usually hid-\nden.\n\nTo work around the hidden IDs, we use another PCI accessor that doesn\u0027t\nrely on the OS seeing the PCI device.\n\nThis handles SPI flashes only. While booting from LPC is still sup-\nported, it seems nobody uses it any more.\n\nSome additional PCI IDs were gathered from driveridentifier.com.\n\nTEST\u003dCompiled with B150 set to NT (instead of BAD) and checked for\n sane register readings.\n\n[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002EN\n Document Number 332995\n\n[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms\n Volume 2 of 2\n Revision 001EN\n Document Number 332996\n\n[3] 7th Generation Intel® Processor Families I/O Platform\n Datasheet - Volume 1 of 2\n Revision 002\n Document Number 334658\n\n[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms\n Datasheet - Volume 2 of 2\n Revision 002\n Document Number 334659\n\n[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform\n Controller Hub (PCH)\n Datasheet - Volume 1 of 2\n Revision 004EN\n Document Number 332690\n\n[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)\n Datasheet - Volume 2 of 2\n Revision 001EN\n Document Number 332691\n\nChange-Id: I000819aff25fbe9764f33df85f040093b82cd948\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18925\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "560111e2ce506b75b112f0d10b5f9b99f007bfa5", "tree": "d9a568d1b4c092a80c9252a648f7ea7ce79bff01", "parents": [ "512059118e9ff56d2b4f3c324db5e764e288ac68" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 26 12:27:17 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:48:06 2017 +0200" }, "message": "ichspi: Drop `dev` parameter from init functions\n\nIt\u0027s never used and has no clear contract (e.g. will the pointer stay\nvalid beyond the call?).\n\nChange-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19460\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "512059118e9ff56d2b4f3c324db5e764e288ac68", "tree": "7c3c384d1579b467135fd85dd9cfbb88abb4771c", "parents": [ "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 17 17:59:54 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:47:49 2017 +0200" }, "message": "Handle Intel Wildcat Point *LP* like Lynx Point LP\n\nThe subtle difference was ignored when adding these chipsets. The\nintegrated Wildcat Point LP PCH is documented in [1].\n\nI\u0027m not sure how to account for \"Broadwell H\" which seems not publicly\ndocumented. Maybe it\u0027s an unreleased HM9*, in which case the non-LP\npath should be correct.\n\n[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,\n Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor\n Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet\n Revision 004\n Document Number: 330837\n\nChange-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18883\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ea99f57c9d8fe28600cd08f653c10e5c0c0dd3f", "tree": "dda8ea443bd14845e927838fa2e27fba61761584", "parents": [ "b4d8a2a64b72d65e447161179279c108709c0ac3" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Mar 17 17:22:53 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 25 18:53:50 2017 +0200" }, "message": "Move register decodes into enable_flash_ich_handle_gcs()\n\nGCS was decoded partly inside, partly outside this function. The\ndecoding of `top_swap` was off, since passing a `uint8_t` as `bool`\ndoesn\u0027t magically check bit0 only.\n\nWhile we are at it, rename this void function to enable_flash_ich_\nreport_gcs() as it\u0027s not doing anything. Beside debug output it\ndoesn\u0027t have any side effects.\n\nChange-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18882\nTested-by: build bot (Jenkins)\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "23e10b87801c22f34642895de8b0b726265eb016", "tree": "2d62c23191801afaecbf98925effb8b8c7a44ab6", "parents": [ "c2644a3fc14088a2535c05edbd56c041b3a7370d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jan 23 16:16:49 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jan 23 16:16:49 2016 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 24\n\nTested mainboards:\nOK:\n - ASRock G31M-GS\n Reported by Александр Трубицын\n - ASRock G41M-VS3\n Reported by Александр Трубицын\n - ASRock N68C-S UCC\n Reported by Alexey Belyaev\n - ASRock AMCP7AION-HT (ION 330HT(-BD))\n Reported by Stefan Tauner\n - ASUS P5K SE\n Reported by Александр Трубицын\n - ASUS P5KPL-VM\n Reported by Marin Vlah\n - ASUS RAMPAGE III GENE\n Reported by stevessss on IRC\n - GIGABYTE GA-945GM-S2\n Reported by Александр Трубицын\n - GIGABYTE GA-945GCM-S2 (rev. 3.0)\n Reported by Александр Трубицын\n - GIGABYTE GA-965P-S3\n Reported by Александр Трубицын\n - GIGABYTE GA-EG43M-S2H\n Reported by Александр Трубицын\n - GIGABYTE GA-EP31-DS3L (rev. 1.0)\n Reported by Александр Трубицын\n - GIGABYTE GA-G33M-S2\n Reported by Александр Трубицын\n - GIGABYTE GA-G33M-S2L\n Reported by Александр Трубицын\n - GIGABYTE GA-H55M-S2\n Reported by Александр Трубицын\n - GIGABYTE GA-J1900N-D3V\n Reported by Marcos Truchado and Guillermo von Hünefeld\n - GIGABYTE GA-K8NS\n Reported by nicolae788\n - GIGABYTE GA-M56S-S3\n Reported by Estevo Paz Freire\n - GIGABYTE GA-P31-DS3L\n Reported by Александр Трубицын\n - GIGABYTE GA-P31-S3G\n Reported by Александр Трубицын\n - MSI MS-7336\n Reported by Benjamin Bellec\n - MSI X79A-GD45 (8D) (MS-7760)\"\n Reported by mortehu on IRC\n - Supermicro A1SAi-2550F\n Reported by Bernard Grymonpon\n - Supermicro X7DWT\n Reported by Steven Stremciuc\n\nLaptop:\n - ASUS U38N\n Reported by Ultra on IRC\n - Dell Latitude D630\n Reported by Márton Miklós\n - Fujitsu Amilo Xi 3650\n Reported by Elmar Stellnberger\n - Lenovo T400 (whitelisting only)\n\nChipsets:\n - Mark 8086:1f38 (Intel Avoton/Rangeley) as tested\n Reported by Jeremy Porter and Bernard Grymonpon\n - Add Intel Sunrise Point IDs but no support yet.\n\nFlash chips:\n - Atmel AT45DB321D to PREW (+PREW)\n Reported by The Raven\n - Eon EN25QH32 to PREW (+PREW)\n Reported by Josua Mayer\n - Eon EN25QH64 to PREW (+EW)\n Reported by David s. Alessio\n - GigaDevice GD25LQ64(B) to PREW (+PREW)\n Reported by Greg Tippit\n - Intel 28F001BN/BX-T to PREW (+EW)\n Reported by Lu Xie\n - Micron M25P10-A to PREW (+W)\n Reported by the Raven\n - Micron M25PE40\n Reported by David Wood\n - Micron N25Q128..3E to PREW (+PREW)\n Reported by Miklós Márton\n - Macronix MX25L3273E to PREW (+PREW)\n Reported by Roklobsta on IRC\n - Macronix MX23L6454 to PR (+PR)\n Reported by Steven Honeyman\n - Macronix MX25U6435E/F to PREW (+PREW)\n Reported by Marcos Truchado and Guillermo von Hünefeld\n - PMC Pm25LQ032C to PREW (+EW)\n Reported by Dirk Knop\n - Spansion S25FL016A to PREW (+EW)\n Reported by Márton Miklós\n - Spansion S25FL128S......0 to PREW (+PREW)\n Reported by Jim Houston\n - Spansion S25FL204K to PR (+PR)\n Reported by Thomas Debrunner\n - SST SST49LF016C to PREW (+EW)\n Reported by Steven Stremciuc\n - SST SST39VF040 to PREW (+PREW)\n Reported by Xavier Bourgeois\n - SST SST49LF040B to PREW (+EW)\n Reported by Rikard Åhlund\n - ST M25P10-A to PREW (+W)\n Reported by Martijn Schiedon\n - Winbond W39V040FA to PREW (+EW)\n Reported by Евгений Черкашин\n - Winbond W39V080FA to PREW (+EW)\n Reported by protagonist0 on IRC\n - Winbond W25Q80.W to PREW (+PREW)\n Reported by Miklós Márton\n - Winbond W25X64 to PREW (+REW)\n Reported by Johannes Krampf and Manuel Dejonghe\n - Fix ID of AMIC A25LQ64\n Reported by Roman Titov\n - Fix page size of Spansion S25FL129P......1\n Copy and paste error from the 128S uniform 256kB variant, probably.\n - Add Micron/Numonyx phase-change memory IDs\n\nMiscellaneous:\n - Detect Android target OS.\n No changes are required to build flashrom (excluding programmers\n with NEED_PCI) on Android.\n - Update rayerspi (spipgm) URL\n - Fix max_data_write handling of at45db.\n - Minor refinement of the README\n - Mark board enable for the GA-K8NS variants as tested.\n Tested by \"nicolae788\" on a board with socket 754.\n - Mark \"Multi-system\" chassis as non-laptop case.\n - Remove W836xx log requests.\n We got enough (and no one is looking at them for the time being anyway).\n - serprog: improve invalid reply error message, contributed by Urja Rannikko.\n - Remove default include paths for MinGW.\n - Disable implicit rules in the Makefile because we don\u0027t need them and they\n just make the build (imperceptibly) slower.\n - Enable our own strnlen() implementation not only on DJGPP but also if\n HAVE_STRNLEN is not defined. This is needed to get older BSDs\n (e.g. NetBSD 6.0, FreeBSD \u003c 8.0) to work.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1917.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "94d8665ea34cb9678c4b08ea340c4a292e520a1d", "tree": "0bfef32aa6ec7df3ccf9e1b3f1e673510500a3e0", "parents": [ "839db6dccd416417f15771beef234b54cd058627" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Nov 21 23:35:47 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Nov 21 23:35:47 2015 +0000" }, "message": "Add support for VIA VT8251\n\nSeems to work on IBM SurePOS 700 and\nIBM (now Toshiba) AnyPlace Kiosk Model 4838-310.\n\nTested-by: Jason Vannest \u003cJason_Vannest@abercrombie.com\u003e\nTested-by: Rowlinson Mark \u003cMark.Rowlinson@uk.fujitsu.com\u003e\n\nCorresponding to flashrom svn r1900.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "5c316f954941241ed75a1f00f00bf1bff318488a", "tree": "ce836bcb29d7d9da86ee583a88236b020985ba36", "parents": [ "dc627931848ed6af40be4f7d5bdb8e33d28b8333" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 22\n\nTested mainboards:\nOK:\n - AOpen UK79G-1394 (used in EZ18 barebones)\n Reported by Lawrence Gough\n - ASUS M4N78 SE\n Reported by Dima Veselov\n - ASUS P5LD2-VM\n Mark board enable as tested (reported by Dima Veselov)\n - GIGABYTE GA-970A-UD3P (rev. 2.0)\n Reported by trucmar on IRC\n - GIGABYTE GA-990FXA-UD3 (rev. 4.0)\n Reported by ROKO__ on IRC\n - GIGABYTE GA-H77-DS3H (rev. 1.1)\n Reported by Evgeniy Edigarev\n - GIGABYTE GA-P55-USB3 (rev. 2.0)\n Reported by Måns Thörnqvist\n - MSI MS-7817 (H81M-E33)\n Reported by Igor Kolker\n\nChipsets:\n - Marked Intel Bay Trail (0x0f1c) as tested OK\n Reported by Antonio Ospite\n - Refine Intel IDs\n * Add IDs for Braswell\n * Add IDs for 9 Series PCHs (e.g. H97, Z97)\n * Rename Wellsburg devices slightly\n\nFlash chips:\n - Atmel AT25DF041A to PREW (+PREW)\n Reported by Tai-hwa Liang\n - Atmel AT26DF161 to PREW (+EW)\n Reported by Steve Shenton\n - Atmel AT45DB011D to PREW (+PREW)\n Reported by The Raven\n - Atmel AT45DB642D to PREW (+PREW)\n Reported by Mahesh Mokal\n - Eon EN25F32 to PREW (+PREW)\n Reported by Arman Khodabande\n - Eon EN25F40 to PREW (+REW)\n Reported by Jerrad Pierce\n - Eon EN25QH16 to PREW (+EW)\n Reported by Ben Johnson\n - GigaDevice GD25Q20(B) to PREW (+PREW)\n Reported by Gilles Aurejac\n - Macronix MX25U6435E/F to PR (+PR)\n Reported by Matt Taggart\n - PMC Pm25LV512(A) to PREW (+PREW)\n Reported by The Raven\n - SST SST39VF020 to PREW (+PREW)\n Reported by Urja Rannikko\n - Winbond W25Q40.V to PREW (+EW)\n Reported by Torben Nielsen\n - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).\n - Add MX25L6465E variant.\n - There was never a MX25L12805 AFAICT.\n - Split MX25L12805 from models with the same ID but an additional 32 kB\n eraser: MX25L12835F/MX25L12845E/MX25L12865E.\n - Add a bunch of ST parallel NOR flash chip IDs.\n\nMiscellaneous:\n - Whitelist ThinkPad X200.\n - Constify master parameter of register_master().\n - Remove FEATURE_BYTEWRITES because it was never used at all.\n - Refine hwseq messages and make them less prominent.\n - Fix the yet unused PRIxCHIPADDR format string thingy.\n - Fix copy\u0026paste error in spi_prettyprint_status_register_bp().\n Spotted by Pablo Cases.\n - Add an additional SMBus controller revision to identify another Yangtze\n model. Thanks to Dan Christensen for reporting this issue.\n - dediprog: add missing include for stdlib.h.\n This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.\n - Remove references to struct pci_filter from programmer.h.\n It is only needed in internal.c where it has a complete type. Having\n it in programmer.h provokes a warning by some old versions of gcc.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1879.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "823096e5270dc7ccd8b0315377428556d1987dcf", "tree": "53fbf8653802401b1a35a6046aa8c54e0f8b0d1a", "parents": [ "4095ed797f87c92b52e15d9f6fdc0b895c414cc9" ], "author": { "name": "Duncan Laurie", "email": "dlaurie@chromium.org", "time": "Wed Aug 20 15:39:38 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:38 2014 +0000" }, "message": "Add support for Intel Wildcat Point PCH\n\nThe Wildcat Point PCH can be paired with Broadwell or Haswell.\nThis patch was essentially backported from ChromiumOS commit 9bd2af8.\n\nCorresponding to flashrom svn r1845.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" } ], "next": "4095ed797f87c92b52e15d9f6fdc0b895c414cc9" }