)]}'
{
  "log": [
    {
      "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8",
      "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0",
      "parents": [
        "a02df33fbf1c196395a61049e60895d4ae0e0a5b"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Aug 12 01:13:45 2023 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Sep 18 19:24:39 2023 +0000"
      },
      "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n"
    },
    {
      "commit": "d2472e5a8e3ee6faa85c3c14b5932c5e96c132e8",
      "tree": "9a6abde0488a16df0df6fa6373106eeb259442f8",
      "parents": [
        "f5fcd742a0568aaf50274bc32e1206f99d65a8b8"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Mar 12 00:44:15 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Mar 14 23:31:10 2023 +0000"
      },
      "message": "amd_spi100: Check IllegalAccess before executing command\n\nThe SPI controller immediately sets the IllegalAccess flag if we\nconfigured an opcode (and optional address) that is not allowed\nin the current configuration.\n\nChange-Id: Icfa5a2823a302857aef0331ce44221747cf5fdd9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73678\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "f5fcd742a0568aaf50274bc32e1206f99d65a8b8",
      "tree": "efdc370c3cc1fcca883364200bc0b6fff5db83ae",
      "parents": [
        "2d614d61c39eefb2796a6edaecb88a0b31650f3c"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Mar 11 17:11:12 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Mar 14 23:31:10 2023 +0000"
      },
      "message": "amd_spi100: Revise 4BA support\n\nWith current SoCs, a flash bigger than 16MiB can\u0027t be fully\nmemory mapped. Also, the memory mapping doesn\u0027t necessarily\nshow us the expected window of the flash.\n\nSo, we consider a memory-mapped read only if we know that\nthe SPI controller\n* sends 32-bit addresses, and\n* doesn\u0027t remap any address bits.\n\nMoreover, we disable support for 4BA mode changes, as we\ncurrently don\u0027t reset the chip state and don\u0027t know if the\ncontroller feels in charge of these.\n\nSending native 4BA commands, however, shouldn\u0027t be a problem,\nso enable these.\n\nChange-Id: I899a89067774334fe15b05bf0b7f2baed5068353\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73677\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "2d614d61c39eefb2796a6edaecb88a0b31650f3c",
      "tree": "bcb4b67d76b9dcb2a9de7fa1f6fc82d1e7129bc9",
      "parents": [
        "50fb6f19bb8faad483078d3201977c65e2b57d5c"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Mar 11 01:06:15 2023 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Mar 14 23:31:10 2023 +0000"
      },
      "message": "amd_spi100: Fix memory-mapped reads for partially mapped chips\n\nIf the memory-mapping doesn\u0027t cover exactly the full flash chip,\nwe have to translate the `start` offset by subtracting the offset\nof the mapping inside the chip\u0027s space (`mapped_start`). This\ncalculation should also work if more than the chip\u0027s size is\nmapped. Then this offset would be negative.\n\nWe also use the newly added `mapped_start` for the preceding\ncalculations in the SPI engine fallback case. It keeps its exact\nsemantics, though.\n\nChange-Id: I4881b2420cb80c079052235ad54cedbb6fa3c945\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73671\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Marty E. Plummer \u003chanetzer@startmail.com\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "e3c305dfd234503faa23c5491962db8f52d0134c",
      "tree": "b86a019224a05586e18b98eae8ff0c9b51a1c701",
      "parents": [
        "070587892b4af723bf8f1f423d0b26e12e061084"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 21:45:56 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 28 23:42:48 2023 +0000"
      },
      "message": "amd_spi100: Implement memory-mapped reads\n\nQuery the RomRange2 register for the memory range (usually top below 4G)\nand try to map that. Reads outside this range will still be served via\nthe command engine.\n\nChange-Id: I21aa67d550ccda0f55a9cf3ff14545a881624d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72583\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "070587892b4af723bf8f1f423d0b26e12e061084",
      "tree": "7217441f5e207ec4750e912079aae5a3b95ffc05",
      "parents": [
        "d81637c3d7c2bf25f1709b6f28a423e074d906f3"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 19:56:39 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 28 23:42:48 2023 +0000"
      },
      "message": "amd_spi100: Use source-aligned read for the FIFO\n\nMakes reading twice as fast (on this Raven Ridge).\n\nChange-Id: I878c7603e514859c48a9c7823f98a391ea921b21\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72582\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "735b186eeffb997a957075d7e610b9700b53cbe1",
      "tree": "1e27f0dc7f2cae492459530df208859221a1d3ca",
      "parents": [
        "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 18:28:45 2023 +0000"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Feb 28 23:42:48 2023 +0000"
      },
      "message": "amd_spi100: Add new driver for AMD SPI100 controllers\n\nStart with a very simple PIO driver. Reads are slow this way, but\nwe can optimize that later. A factor of 2 is possible simply by\naligning the FIFO reads, and another factor of 3 (at least) with\nmemory-mapped reads.\n\nWe override the SPI speed but choose a conservative value to be\non the safe side. Flashrom only supports normal read commands,\nhence we won\u0027t go over 33MHz. Also, if the firmware set a lower\nspeed for normal reads, we use that. We can\u0027t use dual/quad I/O\nwith the SPI command engine, and tests have shown that increasing\nthe SPI speed lifts the read speed only marginally. It seems to\nbe limited by the FIFO reads.\n\nChange-Id: I403d5f103b3ae72f3a91829d562984c54c2e2d00\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72577\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    }
  ]
}