)]}'
{
  "log": [
    {
      "commit": "fbc41d2a932ede9c02aa7803472c31f39ec200f2",
      "tree": "8b72b78abfd99bf8737b90cc2fece11f2dbe93d3",
      "parents": [
        "966dc9b776c2897d1245937639ab41fc834d7cb9"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Feb 22 23:04:01 2026 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Mar 22 09:47:02 2026 +0000"
      },
      "message": "spi: Move SPI related things into new chipdrivers/spi.h\n\nA few things that rely heavily on `flash.h` are moved there instead:\n* function signatures containing `erasefunc_t`,\n* the inline default_wrsr_target() that needs to know struct flashctx.\n\nThis allows to keep the new header file free of a transitive `flash.h`\ninclude.\n\nChange-Id: Ib215821feeb822ea3fc11bf9f48c0328f9a394d4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/416\n"
    },
    {
      "commit": "39687acc6bf41b955a11e8a8fa3f0029342cbb3e",
      "tree": "36f702391d17eae36554a2064297284a14cbc10b",
      "parents": [
        "081ffbae47cbebda5611de101b9dd53b3a58b6bb"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Mon Jul 25 00:23:25 2022 +0300"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:55 2022 +0100"
      },
      "message": "writeprotect_ranges.c: add more range functions\n\nNot all chips follow the same pattern. There are differences in how CMP\nbit is treated or in block size used.\n\nChange-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71008\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "c9feb1bdfa96745a200b9a62dc4234446db8ddb6",
      "tree": "b532df293904cb48d7efa7b127a0072f48801835",
      "parents": [
        "da1c834e9899e5094377a33d19daa53c0d88640b"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Thu Oct 21 01:35:13 2021 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:45 2022 +0100"
      },
      "message": "flashchips,writeprotect_ranges: add range decoding function\n\nAllow chips to specify functions that map status register bits to\nprotection ranges. These are used to enumerate available ranges and\ndetermine the protection state of chips. The patch also adds a range\ndecoding function for the example chips. Many other chips can also be\nhandled by it, though some will require different functions (e.g.\nMX25L6406 and related chips).\n\nAnother approach that has been tried in cros flashrom is maintaining\ntables of range data, but it quickly becomes error prone and hard to\nvalidate.\n\nUsing a function to interpret the ranges allows compact encoding with\nmost chips and is flexible enough to allow chips with less predictable\nranges to be handled as well.\n\nTested: dumped range tables, checked against datasheets\n\nChange-Id: Id163ed80938a946a502ed116e48e8236e36eb203\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70969\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    }
  ]
}