)]}' { "log": [ { "commit": "610c1aad71bfa118c4f49ac01761f586b8dede69", "tree": "8ad4cfd904cf909526b32b03561ad369f42720d9", "parents": [ "b95fe9b9751746b269a3bbd7021cf731d8553715" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:56:05 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "spi: Pass master instead of flash to .send_command\n\nIn the SPI-master API, `.send_command` should only forward commands to\nthe SPI bus. All details about the commands and the SPI slave should be\nhandled in the chip driver. Hence, replace the `flashctx` pointer with\none to the `spi_master` to enforce proper separation.\n\nChange-Id: I50934a1294217794b7e23cc98ade7e4279c059a1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74897\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "e3f648c3146be28c642782b11187011dfd6f258d", "tree": "272af33324401b45fc68bef0e1d697bf502998c1", "parents": [ "32f1ea8df501b41362058bb699a7ea96482e4db3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:55:23 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 22:42:55 2026 +0000" }, "message": "spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected. This was originally the only read-\nprotection mechanism, introduced with ICH7. The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits. Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible. The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits. Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone, we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74896\n" }, { "commit": "42daab10a7704bfbe4a0af1a07748b8858649301", "tree": "9a9aa5465db9f58aa9d0c55f9807a2f694a98e05", "parents": [ "af26008fbabdd780bc6966acca4ad2481520b304" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 16 00:27:27 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Properly add Emmitsburg PCH\n\nThe Emmitsburg or C740 series PCH is actually ahead of all the other,\ncurrently supported chipsets. Finally, Intel added new registers that\ncarry the read and write access permissions for all 16 regions.\n\nThe old FRAP register seems to be still around, so we print both new\nand old registers. For the detailed report we use the new registers,\nthough.\n\nWe also adapt the descriptor detection slightly: We check for `NM \u003d\u003d 6`\njust like we did for Lewisburg. This way we won\u0027t treat a huge range of\nISL (ICH/PCH strap length) values as Emmitsburg, which should result in\nless false positives.\n\nThe output of `ich_descriptors_tool\u0027 tested on some Supermicro firmware\nlooks reasonable. Also tested read/erase/write in `swseq\u0027 and `hwseq\u0027\nmodes with 7 series PCH, reading with ADL-P. All logs still report FRAP\nsettings correctly.\n\nChange-Id: Ibf5ebe2e2edfe5e5ae26bf1136648bf6354b0aa9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/187\n" }, { "commit": "869f0e77ad1203ae078163ddfd32b0b08bf3f135", "tree": "e453d6939c74035f6f1d7ea3cce79713efebf58d", "parents": [ "eeee91bd73ffac9c225a1b86a6cd0c96997f589b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 22:58:39 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Use `swseq_data\u0027 on ICH7 paths too\n\nTested read/erase/write on ThinkPad T60 (ICH7), reading on ADL-P.\n\nChange-Id: I0682e8fe811b6cc54102035cb3f1f834b8792b0a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/178\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "eeee91bd73ffac9c225a1b86a6cd0c96997f589b", "tree": "6fe1ea8ca8844390e1a2b30bb9670f06b1a7d56c", "parents": [ "ecba1d87f1054a286796489a570a6b4614ec1fda" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 21:12:21 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Replace all switch/case on `ich_generation\u0027\n\nTested read/erase/write on ThinkPad T60 (ICH7), reading on ADL-P.\n\nChange-Id: Idcddc19cb18abc418eb2aecbeb75b9926971cc4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/177\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "ecba1d87f1054a286796489a570a6b4614ec1fda", "tree": "dd424b4568d7ed3d72f713ceae6f5dcb87756ce4", "parents": [ "e8babf4ab03842fc1ed59f8c3b72459ca9775e2b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 21:03:27 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Drop redundant bail-out cases in ich_set_bbar()\n\nich_set_bbar() is never called for ICH8 nor Bay Trail.\n\nChecked verbose output stays the same on ThinkPad T60 (ICH7).\n\nChange-Id: Ia4af7b4543081f2dfa850c4343989a2f158b43c5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/176\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "e8babf4ab03842fc1ed59f8c3b72459ca9775e2b", "tree": "3103eb005c1de66e2501dc969c67ca690d0c436f", "parents": [ "fda324bfc3c09cce47fe1947f6a2883b357d7f1d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 20:40:56 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Use a single check to enable hwseq for PCH100+\n\nThe only difference between these blocks was the debug message printed.\nLet\u0027s not be that picky and unify the code. It does not only simplify\nthe condition but also helps to avoid mistakes: C620 series Lewisburg\nwas most likely missed here earlier.\n\nChange-Id: Ic802c6327afdea86a0f50ced53deabe8c2f36175\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/175\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "fda324bfc3c09cce47fe1947f6a2883b357d7f1d", "tree": "f2411a115e7d4a7d8222aa9c90aba3243c80921e", "parents": [ "a1f6476a65bda5262d46430724a3af4b49bcd9e7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 20:36:21 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Introduce SPI_ENGINE_PCH100 marker\n\nUse a new SPI_ENGINE_PCH100 marker in ich9_spi_init(). Suddenly this\nfunctions becomes more readable again.\n\nTested read/erase/write in `swseq\u0027 and `hwseq\u0027 modes with 7 series \u0026\nreading with ADL-P. Log output stays consistent.\n\nChange-Id: Iff03354ee886eb1ea80e37e50914b8afff08a29e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/174\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "a1f6476a65bda5262d46430724a3af4b49bcd9e7", "tree": "4c03ecc180e60864fcbf59952c01c58390921eed", "parents": [ "3f75d4476da015ae1ee033c1de1ad4dc08f66b0d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 20:23:28 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Split ICH7 init out\n\nThe original, ICH7 init only shared about three lines with the newer,\never growing ICH9+ init. That\u0027s not worth an indentation level in an\nendlessly long function, so split it out.\n\nWe introduce a kind of \"breakpoint\" into the `ich_chipset\u0027 enum:\n\n SPI_ENGINE_ICH9\n\nThis marks all chipset entries below it as supporting this code path\nand should help to avoid long `case\u0027 lists.\n\nTested read/erase/write on ThinkPad T60 (ICH7).\n\nChange-Id: I41e46d12e02c1343e636b47b2378db86e76af95e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/173\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d518563f197241cc72f5da4b2108b2df10f00372", "tree": "8ec807be43adf3b5c9f66a2701b7bf0ea3a4a11f", "parents": [ "bd72a470b9b58386b52ca4568313be71b4d2c472" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 05 18:44:41 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Prepare for multi i/o and dummy bytes\n\nMulti-i/o commands split SPI transactions into multiple phases that\ncan be transferred over 1, 2 or 4 wires. For this, we adapt `struct\nspi_command` with a new enum, specifying the transfer mode, and ad-\nditional size fields. While we are at it, move everything related\ninto a new header file `spi_command.h` so we won\u0027t further clutter\n`flash.h`.\n\nOn the master side, we add respective feature flags for the multi-\ni/o modes.\n\nSee also the comment in `spi_command.h` about multi-i/o commands.\n\nChange-Id: I79debb845f1c8fec77e0556853ffb01735e73ab8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/44\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "3824c8d9dde3dc7c9db0f7dcdd08ee21a759dd57", "tree": "c232684790ea29165851ac5f314d6e7ebf44e16b", "parents": [ "0d4354eee32c834a602f5bec05803bd36977cfaa" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun May 26 16:59:22 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 02 10:02:58 2024 +0000" }, "message": "ichspi: Allow all opcodes when the \"opmenu\" isn\u0027t locked\n\nThe opmenu is not authoritative when we can re-program it on the fly.\nHence always return true in ich_spi_probe_opcode() when it isn\u0027t locked.\n\nTested by `cobra` on IRC.\n\nChange-Id: I636f00acbdfa1661c13c2d82d7d7e61fbe6b543b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/151\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "842d678f07439e133e69fc775a848dcd66369446", "tree": "c01716fbc4220c1211749772d6a566e6d70701d7", "parents": [ "aa714dd3dd7090e1fa7175f3a32a252b04817261" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Fri Jan 15 09:48:12 2021 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "libflashrom: Return progress state to the library user\n\nProjects using libflashrom like fwupd expect the user to wait for the\noperation to complete. To avoid the user thinking the process has\n\"hung\" or \"got stuck\" report back the progress complete of the erase,\nwrite and read operations.\n\nAdd a new --progress flag to the CLI to report progress of operations.\n\nInclude a test for the dummy spi25 device.\n\nTested: ./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus\u003d7 -r /dev/null --progress\n\nflashrom-stable:\n* Closer to original libflashrom API.\n* Split update_progress() into progress_start/_set/_add/_finish:\n Simplifies progress calls scattered through the code base. We let\n the core code in `flashprog.c` handle the total progress. Only API\n is flashprog_progress_add(). Erase progress is completely handled\n in `flashprog.c`. Fine grained read/write progress can be reported\n at the chip/programmer level.\n* Add calls to all chip read/write paths and opaque programmers\n except for read_memmapped() (which is handled in follow ups).\n* At least one wrinkle left: Erasing unaligned regions will slightly\n overshoot total progress.\n\nChange-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nSigned-off-by: Daniel Campello \u003ccampello@chromium.org\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74731\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "9a11cbf21a5078bcdb8db7584c44a9ee17020db4", "tree": "e67a9eadfdb7a71f81df36c7e97180474a8c59df", "parents": [ "aabb3e0ff54e87c0136c91f105e506ed19184cc6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:19:07 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:40:04 2024 +0000" }, "message": "Let the flash context directly point to the used master\n\nWe used to have a pointer to a full `registered_master` struct in\nour flash context. Beside the used master, this contained a bit\nmask of supported buses. Oddly convenient, this bit mask invited\nto bypass the chip driver and break the abstraction. It allowed\nto place bus-specific details virtually anywhere in flashprog,\nmaking it harder to find a good place for them.\n\nSo, get rid of the `buses_supported` bit mask by pointing directly\nto the master. Only the chip driver will implicitly know which type\nof master is used.\n\nChange-Id: I9ce13d8df0e7ccc67519d888dd9cb2e2ff8d6682\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72533\n" }, { "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b", "tree": "bf0c3951886de60086d32ff6e1a850adad926da6", "parents": [ "929d2e1b17a448d3352dbecb6a620ee0c1e65a58" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 23:31:40 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n they advertise the whole default set (PAR, LPC, FWH), they only pro-\n vide a maximum decode size for one of them. The latter is probably\n wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "e7a41e3cec25165b6564b62b6aa64f90bd2dab71", "tree": "a635e566992d379fa1acca5de7fd7517e5c13580", "parents": [ "b0be3200954bebf2431c4d7bd441096f157f621e" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Nov 28 17:40:56 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "tree/: Make probe_opcode() flashctx argument const\n\nProbing an opcode generally shouldn\u0027t involve mutating the flashctx\nstate and currently no probe_opcode functions do that.\n\nMake the flashctx arg const so that call sites don\u0027t need to have a\nnon-const pointer.\n\nTested: ninja test\n\nChange-Id: I19e98be50d682de2d2715417f8b7b8c62b871617\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72543\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0cea753aff33b78051febadf8786df83144b5ee7", "tree": "8972ea6cf44e249659ddad7ea3d9aa2dedffc0b6", "parents": [ "ab9f25893f1fa87cbbaf656869e346391eccdb31" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Mon Jul 04 18:21:50 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi: Add function to probe erase command opcode for all spi_master\n\nAdd a field, probe_opcode, to struct spi_master which points to a\nfunction returning a bool by checking if a given command is supported by\nthe programmer in use. This is used for getting a whitelist of commands\nsupported by the programmer, as some programmers like ichspi don\u0027t\nsupport all opcodes.\n\nMost programmers use the default function, which just returns true.\nICHSPI and dummyflasher use their specialized function.\n\nflashrom-stable: Added `.probe_opcode` for `dirtyjtag_spi`, `ich7`.\n\nChange-Id: I6852ef92788221f471a859c879f8aff42558d36d\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72539\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0b587f921aebd36aaa9f69faea0d2601386d7379", "tree": "c13c57f89dd385d3ed1bd76893cf7a251f8eba1a", "parents": [ "7310f19a07d70a16a0e6342ceb538854729282cd" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Sep 09 23:01:05 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "spi: Make \u0027default_spi_write_aai\u0027 the default unless defined\n\nA NULL func pointer is necessary and sufficient for the\ncondition `NULL func pointer \u003d\u003e default_spi_write_aai\u0027 as to not\nneed this explicit specification of \u0027default\u0027.\n\nTherefore drop the explicit need to specify the \u0027default_spi_write_aai\u0027\ncallback function pointer in the spi_master struct. This is a reasonable\ndefault for every other driver in the tree with only a few exceptions.\n\nThis simplifies the code and driver development.\n\nflashrom-stable: Updated `dirtyjtag_spi` which was added earlier.\n\nChange-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67479\nOriginal-Reviewed-by: Peter Marheine \u003cpmarheine@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72369\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77", "tree": "ae3340f0a563d1d9ed48285cc861e7e90e2343ef", "parents": [ "a6b45c4516e15aeb405028e5095e86259fcd9e34" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Jan 17 15:11:43 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move mmio functions into hwaccess_physmap\n\nThe mmio_le/be_read/writex functions are used for raw memory access.\nBundle them with the physmap functions.\n\nChange-Id: I313062b078e89630c703038866ac93c651f0f49a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72278\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "74b4aa0b15439a2ab2474889a7abed978439757a", "tree": "a3e6d01052b04bbae7c71af7c1148d3619ba1ab1", "parents": [ "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:52:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "physmap: rename to hwaccess_physmap, create own header\n\nLine up physmap with the other hwaccess related code.\n\nChange-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "51264d5def2188624a3354c62722a95e64224645", "tree": "f8b01a56582b453253d7a7b09b26cedd61bbe96f", "parents": [ "121a5b8d63008db1d179ab69fc1c6b39e03d575c" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.de", "time": "Tue Sep 21 10:00:14 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "remove compile guards\n\nThe build system handles the decision when to build a file.\nExtra compile guards for the source files are not necessary.\n\nChange-Id: I76a76e05c7a7dd27637325ab1e9d8946fd5f9076\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57797\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72260\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "21b20218a6128c1880eceb634101df176b56692d", "tree": "84402bf4e4ac933b023ac6e1c56f4a693ef522bc", "parents": [ "b91a203091fc43824bc57f3c8e2db0bcc311da59" ], "author": { "name": "Anastasia Klimchuk", "email": "aklm@chromium.org", "time": "Thu May 13 12:28:47 2021 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_opaque_master() API\n\nIt was impossible to register a const struct opaque_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: Id3adb4cf04ae04dbe87ddb96f30871cb5f7c8ff0\nSigned-off-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54170\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72202\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5e08e3e829e3f736e18cef7b8f4a8929c9e06257", "tree": "cfe9483275582e2ff2a50628824cf8e842c1feef", "parents": [ "6c33185c81f4aab0d048be7c4b68dca1a91800c2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 11 17:38:14 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "programmer: Smoothen register_spi_master() API\n\nIt was impossible to register a const struct spi_master that would\npoint to dynamically allocated `data`. Fix that so that we won\u0027t\nhave to create more mutable globals.\n\nChange-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72179\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8cfc7377ffa880659660b344e97333986aba9130", "tree": "3ab74fbb322c79a63fed60c20077c42332408280", "parents": [ "980d6b8d712d26711dcd5a71007e4626c7198cd5" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 03:10:29 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "ichspi.c: Retype appropriate variables with bool\n\nUse the bool type instead of an integer for appropriate variables, since\nthis represents their purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: If7eeacc44921f52aa593ab1302f17a5c5190f830\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66892\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71484\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "43040f297e68cd4d826d58f57566581ef902d179", "tree": "a8357aba5a8dbfd43f3e7949c865f2682bf5962d", "parents": [ "4203a47a102e2622f404ee6567b240882d584116" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Thu Jun 23 14:38:35 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: indent struct *_master consistently with tabs\n\nUse `\u003ctab\u003e.key\u003ctab\u003e*\u003d \u003cvalue\u003e,`\n\nTEST: `make VERSION\u003d0 MAN_DATE\u003d0` returns the same flashrom binary\nbefore and after the patch\n\nChange-Id: I1c45ea9804ca09e040d7ac98255042f58b01f8ef\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65363\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71466\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f6c1cb1a856e67b8cf7eaf7a90b09bc3923a3718", "tree": "9776b733a8f851fe90b582068baae97e64425e40", "parents": [ "137f02f887144eae222e44adb675cb299fd00337" ], "author": { "name": "Martin Roth", "email": "gaumless@gmail.com", "time": "Tue Mar 15 10:55:25 2022 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Global cleanup: Fix a few spelling errors\n\nJust a trivial patch to fix a few errors found by codespell.\n\nHere\u0027s the command I used:\ncodespell -S subprojects,out \\\n-L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun\n\nSigned-off-by: Martin Roth \u003cgaumless@gmail.com\u003e\nChange-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71455\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e57d4e49fd2556f0fe267833d35cc57b7e252c06", "tree": "ef260430367f0d2025fd6c5c12c101f37639613e", "parents": [ "672bdcfd4ffeb065b7056042769e3cc512d87c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Mon Jan 03 09:44:29 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Elkhart Lake support\n\nElkhart Lake has a chipset called Mule Creek Canyon which is quite\ncompatible with 300 series chipsets. There are a few differences though,\ne.g. different encoding for the SPI clock values for read and write in\nthe FLCOMP register. In addition Elkhart Lake has a new PCI device ID\nfor the SPI controller which is added, too.\n\nTested: Read and flash complete flash on Siemens MC EHL1\n\nChange-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937", "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744", "parents": [ "cce1e5b8636ebef59dd509680594e17b0a207857" ], "author": { "name": "Michał Żygowski", "email": "michal.zygowski@3mdeb.com", "time": "Wed Jun 16 15:13:54 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e1345602641114c8eeb5cfef992bf1da8d7fa6a", "tree": "ce19124575cfd893449c754800c757d096dd3130", "parents": [ "690a944066619ff9d450d71cdcfe2e0bcb1120f3" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Jun 07 13:29:13 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "treewide: Drop unnecessary uses of memset/memcpy\n\nSimply provide an initialiser or use a direct assignment instead.\n\nChange-Id: I07385375cd8eec8a95874001b402b2c17ec09e09\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55267\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71372\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "690a944066619ff9d450d71cdcfe2e0bcb1120f3", "tree": "e8da9e733570d6ebb25251f2362f17af5c59d626", "parents": [ "c40ca200100fe6fc451ab7f9bdf9751af1899d02" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Jun 07 12:33:53 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "treewide: Drop most cases of `sizeof(struct ...)`\n\nSpelling out the struct type name hurts readability and introduces\nopportunities for bugs to happen when the pointer variable type is\nchanged but the corresponding sizeof is (are) not.\n\nTested: `make CONFIG_EVERYTHING\u003dyes CONFIG_JLINK_SPI\u003dno VERSION\u003dnone -j`\nwith and without this patch; the flashrom executable does not change.\n\nflashrom-stable: Applied partially.\n\nChange-Id: Icc0b60ca6ef9f5ece6ed2a0e03600bb6ccd7dcc6\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55266\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71371\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113", "tree": "5866347a6c5e63477f8e05cc32443085319c2df3", "parents": [ "771bb7952a91722d2d9f100e19b0566f06298126" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 10 17:04:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5eca427ae64519b70d1c4ccfb427305ca9974ba0", "tree": "1ca22ef1e0072a76650fdd182206844f8ebddd7d", "parents": [ "1bbc501f79319cc6c8d839bc44fa55e96afab33a" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sun Apr 12 17:27:53 2020 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:34 2022 +0100" }, "message": "const\u0027ify flashctx to align signatures with cros flashrom\n\nThe ChromiumOS flashrom fork has since const\u0027ify flashctx\nin a few places. This aligns the function signatures to\nmatch with downstream to ease forward porting patches\nout of downstream back into mainline flashrom.\n\nThis patch is minimum viable alignment and so feedback is\nwelcome.\n\nChange-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7cb43957c5fe405cd82584f0a54428f2d2d286ff", "tree": "9981905ba97c0509e8686782855d97cffe77d80e", "parents": [ "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Mar 16 20:40:42 2022 +0530" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Sun Oct 30 09:43:35 2022 +0000" }, "message": "ichspi: Unify timeouts across all SPI operations to 30s\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\n`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument\nin favor of a fixed timeout of `30 seconds` for any given SPI operation\nas recommended by the SPI programming guide.\n\nDocument: Alder Lake-P Client Platform SPI Programming Guide\n Rev 1.30 (supporting document for multi-master accessing the\n SPI Flash device.)\n\nRefer to below section to understand the problem in more detail and SPI\noperation timeout recommendation from Intel in multi-master\nscenarios.\n\nOn Intel Chipsets that support multi-mastering access of the SPI flash\nmay run into a timeout failure when the operation initiated from a\nsingle master just follows the SPI operational timeout recommendation\nas per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR\nspecification, table 9.7).\n\nIn the multi-master SPI accessing scenario using hardware sequencing\noperation, it\u0027s impossible to know the actual status of the SPI bus\nprior to individual master starting the operation (SPI Cycle In Progress\na.k.a SCIP bit represents the status of SPI operation on individual\nmaster).\n\nThus, any SPI operation triggered in multi-master environment might need\nto account a worst case scenario where the most time consuming operation\nmight have occupied the SPI bus from a master and an operation initiated\nby another master just timed out.\n\nHere is the timeout calculation for any hardware sequencing operation:\n Worst Case Operational Delay \u003d\n (Maximum Time consumed by a SPI operation + Any marginal\n\t adjustment)\n\n Timeout Recommendation for Hardware Sequencing Operation \u003d\n ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +\n Current Operational latency)\n\nAssume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC,\nGbE and other reserved etc, hence, the Timeout Calculation for SPI\nerase Operation would look like as below:\n\n Maximum Time consumed by a SPI Operation \u003d 5 seconds\n\n Worst Case Operational Delay \u003d 5 seconds\n\n Timeout Recommendation for Hardware Seq Operation \u003d\n 5 seconds * (6 - 1) + 5 seconds \u003d 30 seconds\n\nBUG\u003db:223630977\nTEST\u003dAble to perform read/write/erase operation on PCH 600 series\nchipset (board name: Brya).\n\nOriginal-Signed-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867\nOriginal-Tested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nChange-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68691\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\n" }, { "commit": "15f539c8c978e002f2b6397a7a74e1af817d5cb3", "tree": "933422f889c4d668cace147b383c4aa3a9b024a6", "parents": [ "a1fc01d9e2f28d3d5f1506117c11f35bd42a7a6a" ], "author": { "name": "David Hendricks", "email": "dhendrix@chromium.org", "time": "Thu Aug 26 21:27:17 2010 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Sep 24 18:49:09 2019 +0000" }, "message": "ichspi: Replace default JEDEC_BE_D8 with JEDEC_SE\n\nThis aligns the upstream master branch with chromium\u0027s. On-the-fly\nopcode reprogramming is supported by both branches so the default\nopcode shouldn\u0027t matter.\n\nReview URL: http://codereview.chromium.org/3239001\n\nChange-Id: I379549e8fa966e75e3d8b7932700df62cf50df64\nSigned-off-by: Mayur Panchal \u003cpanchalm@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34689\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "519be66fc59558971dd653afe69ccaf1a633b492", "tree": "74f0912de156a86d56111f377db080246e5205e9", "parents": [ "ef78de4a21323b8c459337356289218211f2c5ce" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 23 20:03:35 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:26:59 2019 +0000" }, "message": "Fix -Wsign-compare trouble\n\nMostly by changing to `unsigned` types where applicable, sometimes\n`signed` types, and casting as a last resort.\n\nChange-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30409\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "d2d3993a25c3236d397209f9c2118c3b17ce4f95", "tree": "8c91f0f2d588e66963c13e48dd972de555985bf4", "parents": [ "3750986348cb99b8f0d828b73972b545a2f9c878" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 16:49:37 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:23:53 2019 +0000" }, "message": "ichspi: Add Apollo Lake support\n\nIt\u0027s almost identical to 100 series PCHs and later. There are some\nadditional FREGs (12..15). To not clutter the `if` conditions further,\nmake more use of `switch` statements.\n\nTested on Kontron mAL10. Mark it as DEP as usually the last sector\nis not covered by the descriptor layout and can\u0027t be read.\n\nChange-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30995\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "deeac7e41a311a0806af0e65a2ce5c6673f9cf92", "tree": "2ff1082bf9ed049c2863deff9a6d66b6980b1812", "parents": [ "959aafa53eeae4f22766b9d098e5ca952af8c070" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:09:42 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:25:15 2019 +0000" }, "message": "spi: Drop spi_controller type\n\nNot needed anymore. Drop it fast before it encourages anyone to\nviolate layers again!\n\nChange-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33651\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "29e46d0aa6ec9ce0b5234bf3bdbd9f22c951252c", "tree": "5c2e329fbd6ca08b5dfe66c65eb8fa00049ff7ab", "parents": [ "504215b9f68e26938eea75afcbc22bdf389af991" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Sun Jun 09 17:38:25 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 15:06:47 2019 +0000" }, "message": "ichspi.c: Remove unneeded \u0027else\u0027\n\n\u0027else\u0027 is not needed after a \u0027break\u0027 or \u0027return\u0027.\n\nChange-Id: Ie000732158f27632ee92404c66a9aab43f3b374c\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33347\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "db7482bb72035fab8386226d1720cde09e0c700e", "tree": "8a2114a45c22a44e01d8494f224b38c35b17cb71", "parents": [ "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 12:04:30 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 11 23:50:12 2019 +0000" }, "message": "Fix several -Wno-implicit-fallthrough warnings\n\nGCC is picky about the comment being where the break should go.\n\nChange-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30406\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "e2cbb12f2209a0ba16bc87e31d544fd7fc47f0e2", "tree": "3d0a25e70f59aae1f0016adf7f001094b42c5426", "parents": [ "84b453e4d4140230bd4d72d530b2b08f9a51b4e2" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Jan 02 21:11:08 2019 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 19:08:37 2019 +0000" }, "message": "Fix one more -Wmissing-field-initializers warning\n\nFixes:\n\n ichspi.c: In function ‘ich_init_spi’:\n ichspi.c:1707:9: warning: missing initializer for field ‘component’\n\nChange-Id: Iee5728167963fece24822ad2e3ab7bd9d444b42c\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/31224\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "df4905822754ac1f303f7939f5b77b35e5ac4a67", "tree": "547a0248de382233cecfc018a25996ffc0195b2d", "parents": [ "93e1625f9fb5f1080c40685488d006b2982062d7" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 11:57:15 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 18:44:16 2019 +0000" }, "message": "Fix several -Wno-missing-field-initializers warnings\n\nChange-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30405\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "93e1625f9fb5f1080c40685488d006b2982062d7", "tree": "810e5b2807d6f5c102059e2b8a99a91a17c8f9c7", "parents": [ "d82be7b2be34fb3273781e72f5d8e52a3103b961" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 11:54:47 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 18:31:45 2019 +0000" }, "message": "Fix several -Wold-style-declaration warnings\n\nChange-Id: Iffe5e652779a13ee7f64696fb5df4a781fe9a632\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30404\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7590d1a9375e94d01cef08a2bde10a05177d5829", "tree": "a69d185d67f2b7d846d5f92b358b917b82696b0a", "parents": [ "f9a30554803a670f9b95a7794be00f03929d6ecd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue May 03 13:38:28 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 29 14:56:51 2018 +0000" }, "message": "Enable writes with active ME\n\nReplace the `ich_spi_force` logic with more helpful warnings. These can\nbe hidden later, in case the necessary switches are detected. Also,\ndemote some warnings about settings that are the default nowadays (e.g.\nSPI configuration lock, inaccessible ME region).\n\nChange-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/26261\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b", "tree": "980f498681fcc053ec1e591e22bb16afbef0a191", "parents": [ "3f7e3419887c6d37330387f8e32c86ba47bdf70c" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Tue Mar 27 12:15:09 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:18:58 2018 +0000" }, "message": "Fix whitespace errors\n\nChange-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25380\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "19eb0792b8439198d7ef0077b8f79f275fa39a9d", "tree": "b2d1e9a9e53150c48828f2e38afbf6264d48b6ac", "parents": [ "3083ed90c62e9516615e2322f23ca798e5124a8f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 13 00:44:45 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Dec 19 12:30:05 2017 +0000" }, "message": "ichspi: Fix 100 series PCH (Skylake) support\n\nPretty subtle missing `else` made flashrom treat Skylake like older\nchipsets.\n\nChange-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Youness Alaoui \u003ckakaroto@kakaroto.homelinux.net\u003e\nReviewed-on: https://review.coreboot.org/22832\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "22f2dc5ec0b13a413a9ce42a5836ec2aa3b1abfc", "tree": "9b496559cd9503628b42f19c5789400e0bcc5373", "parents": [ "1f081530b60ee805532f106f59cc33973e160481" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Aug 31 16:14:22 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 05 22:33:41 2017 +0000" }, "message": "ichspi: Disable software sequencing by default for Skylake\n\nSkylake is a mess, especially with coreboot. We have now a present and\nconfigured software sequencing interface with SCGO supposedly being\nreadonly (Apollo Lake has that feature and a strap documented, Skylake\nbehaviour might be the same). As we can\u0027t easily check if it\u0027s read-\nonly, just enable hardware sequencing by default (even if the software\nsequencing interface seems usable).\n\nChange-Id: I8a13fb9c3ca679b3f7d39ad1dc56d5efdc80045b\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/22274\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "8b2152d54a67e4139525ce49aefe1a6d0e41b85c", "tree": "6b2b15743a972873d96c12591767780cdc905539", "parents": [ "f268d8b2d6fe5ea5ab0e0e2c5eec02c16d023ce5" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Aug 31 13:18:49 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 03 16:53:36 2017 +0000" }, "message": "ichspi: Fix software sequencing for Skylake\n\nTwo occurences of ICH9_REG_OPMENU were overlooked and not replaced,\nrendering the software sequencing unusable on Skylake.\n\nChange-Id: I16eebcf37ab8ba39b02f33135535552e380b0b92\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/22273\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Patrick Rudolph \u003csiro@das-labor.org\u003e\n" }, { "commit": "a5216367d5640f07d58a6549fa6df86d91daff1a", "tree": "72cb2a7ba167ed6d6e0509ad8292ea7283932e7a", "parents": [ "aa91d5c16858cb400cc61e8a759838f645e3f314" ], "author": { "name": "David Hendricks", "email": "dhendricks@fb.com", "time": "Tue Aug 08 20:02:22 2017 -0700" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Fri Sep 01 20:34:44 2017 +0000" }, "message": "chipset_enable: Add support for C620-series Lewisburg PCH\n\nThis adds PCI IDs for C620-series PCHs and adds\nCHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.\n\nLewisburg is very similar to Sunrise Point for Flashrom\u0027s purposes,\nhowever one important difference is the way the \"number of masters\" is\ninterpreted from the flash descriptor (0-based vs. 1-based). There are\nalso new flash regions defined.\n\nChange-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b\nSigned-off-by: David Hendricks \u003cdhendricks@fb.com\u003e\nReviewed-on: https://review.coreboot.org/20922\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "aa91d5c16858cb400cc61e8a759838f645e3f314", "tree": "163b27954a680ea02f945ee383f8dbc7c1cc03c8", "parents": [ "a1bccd88c3c8c0041795b96faef2cb4179bfbd7c" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Sat Aug 19 17:04:21 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Aug 21 21:21:47 2017 +0000" }, "message": "ichspi: \"Fix\" access permission reporting for regions \u003e 7\n\nCan\u0027t find bits that tell us the actual permissions in charge. So report\nthem as unknown.\n\nChange-Id: Ib73f95e0348f5c6d89988e3ea3529af0ec3b23a6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/21106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "0bb3f7142aecdf883cc28bd9b771bdba3da5d7d9", "tree": "1bd56eecff210a628c148c836e2dfce13ebfd5f8", "parents": [ "d54e4f467753a247552bfb629f007f8931b0caa7" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Mar 29 16:44:33 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:24:06 2017 +0000" }, "message": "ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()\n\nThe condition `base \u003e limit` is still valid since `base` is always at\nleast 4096 greater than `limit` in this case.\n\nChange-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19046\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d54e4f467753a247552bfb629f007f8931b0caa7", "tree": "0a7bb8254865783ad1fa1dc958e74e1a57936953", "parents": [ "93c306939b732fb05f6d8a692acc3fca78bc0f9f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 23 23:45:47 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 28 12:22:58 2017 +0000" }, "message": "ichspi: Add support for Intel Skylake\n\nThe Sunrise Point PCH, paired with Skylake, has some minor changes\nin the HW sequencing interface:\n\n * Support for more flash regions moved PR* registers\n * Only 4KiB erase blocks are supported by the primary erase command\n * A second erase command for 64KiB pages was added\n * More commands were added for status register access etc.\n * A \"Dedicated Lock Bits\" register was added\n\nNo support for the new commands was added.\n\nThe SW sequencing interface seems to have moved register location and\nis not supported any more officially. It\u0027s also untested.\n\nChanges are loosely based on the Skylake support commit in Chromium OS\nby Ramya Vijaykumar:\n\n commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1\n Author: Ramya Vijaykumar \u003cramya.vijaykumar@intel.com\u003e\n\n flashrom: Add Skylake platform support\n\nChange-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n" }, { "commit": "d152fb95e2b7fda62a85f6c8e4112ba9f353a8d6", "tree": "cfd2ea28b75cb90db72f488ee237a068d0cb52a4", "parents": [ "731316a9128c4015bc0facd1743afeb3a080129e" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 19 12:57:10 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 13 16:27:55 2017 +0000" }, "message": "Drop redundant `enum msglevel`\n\nUse `enum flashrom_log_level` instead to avoid further confusion.\n\nChange-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/20268\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "560111e2ce506b75b112f0d10b5f9b99f007bfa5", "tree": "d9a568d1b4c092a80c9252a648f7ea7ce79bff01", "parents": [ "512059118e9ff56d2b4f3c324db5e764e288ac68" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Wed Apr 26 12:27:17 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 20 11:48:06 2017 +0200" }, "message": "ichspi: Drop `dev` parameter from init functions\n\nIt\u0027s never used and has no clear contract (e.g. will the pointer stay\nvalid beyond the call?).\n\nChange-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/19460\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n" }, { "commit": "4c72315c10c0a760a6ed9181257aa7fe3ce9176d", "tree": "a98688792c28001185f29bd30ce569ca38f888ce", "parents": [ "bfb067b076c048935314635ffb16c0913a171744" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jan 14 22:47:55 2016 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jan 14 22:47:55 2016 +0000" }, "message": "Pimp the manpage to create nicer hyperlinks and HTML output\n\nAlso, add a target to the makefile to build a flashrom.8.html with groff.\nTo fix some formatting issues this adds some indention commands as well.\n\nCorresponding to flashrom svn r1913.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "5c316f954941241ed75a1f00f00bf1bff318488a", "tree": "ce836bcb29d7d9da86ee583a88236b020985ba36", "parents": [ "dc627931848ed6af40be4f7d5bdb8e33d28b8333" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Feb 08 21:57:52 2015 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 22\n\nTested mainboards:\nOK:\n - AOpen UK79G-1394 (used in EZ18 barebones)\n Reported by Lawrence Gough\n - ASUS M4N78 SE\n Reported by Dima Veselov\n - ASUS P5LD2-VM\n Mark board enable as tested (reported by Dima Veselov)\n - GIGABYTE GA-970A-UD3P (rev. 2.0)\n Reported by trucmar on IRC\n - GIGABYTE GA-990FXA-UD3 (rev. 4.0)\n Reported by ROKO__ on IRC\n - GIGABYTE GA-H77-DS3H (rev. 1.1)\n Reported by Evgeniy Edigarev\n - GIGABYTE GA-P55-USB3 (rev. 2.0)\n Reported by Måns Thörnqvist\n - MSI MS-7817 (H81M-E33)\n Reported by Igor Kolker\n\nChipsets:\n - Marked Intel Bay Trail (0x0f1c) as tested OK\n Reported by Antonio Ospite\n - Refine Intel IDs\n * Add IDs for Braswell\n * Add IDs for 9 Series PCHs (e.g. H97, Z97)\n * Rename Wellsburg devices slightly\n\nFlash chips:\n - Atmel AT25DF041A to PREW (+PREW)\n Reported by Tai-hwa Liang\n - Atmel AT26DF161 to PREW (+EW)\n Reported by Steve Shenton\n - Atmel AT45DB011D to PREW (+PREW)\n Reported by The Raven\n - Atmel AT45DB642D to PREW (+PREW)\n Reported by Mahesh Mokal\n - Eon EN25F32 to PREW (+PREW)\n Reported by Arman Khodabande\n - Eon EN25F40 to PREW (+REW)\n Reported by Jerrad Pierce\n - Eon EN25QH16 to PREW (+EW)\n Reported by Ben Johnson\n - GigaDevice GD25Q20(B) to PREW (+PREW)\n Reported by Gilles Aurejac\n - Macronix MX25U6435E/F to PR (+PR)\n Reported by Matt Taggart\n - PMC Pm25LV512(A) to PREW (+PREW)\n Reported by The Raven\n - SST SST39VF020 to PREW (+PREW)\n Reported by Urja Rannikko\n - Winbond W25Q40.V to PREW (+EW)\n Reported by Torben Nielsen\n - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).\n - Add MX25L6465E variant.\n - There was never a MX25L12805 AFAICT.\n - Split MX25L12805 from models with the same ID but an additional 32 kB\n eraser: MX25L12835F/MX25L12845E/MX25L12865E.\n - Add a bunch of ST parallel NOR flash chip IDs.\n\nMiscellaneous:\n - Whitelist ThinkPad X200.\n - Constify master parameter of register_master().\n - Remove FEATURE_BYTEWRITES because it was never used at all.\n - Refine hwseq messages and make them less prominent.\n - Fix the yet unused PRIxCHIPADDR format string thingy.\n - Fix copy\u0026paste error in spi_prettyprint_status_register_bp().\n Spotted by Pablo Cases.\n - Add an additional SMBus controller revision to identify another Yangtze\n model. Thanks to Dan Christensen for reporting this issue.\n - dediprog: add missing include for stdlib.h.\n This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.\n - Remove references to struct pci_filter from programmer.h.\n It is only needed in internal.c where it has a complete type. Having\n it in programmer.h provokes a warning by some old versions of gcc.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1879.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "4095ed797f87c92b52e15d9f6fdc0b895c414cc9", "tree": "deaca4de25e5bafc24fe0a48a401a8d4f062a170", "parents": [ "2ba9f6ebe56b208a1fb0b0ce5edf81097a0158be" ], "author": { "name": "Duncan Laurie", "email": "dlaurie@chromium.org", "time": "Wed Aug 20 15:39:32 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:32 2014 +0000" }, "message": "Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton\n\nThe core of this patch to support Bay Trail originally came from the\nChromiumos flashrom repo and was modified by Sage to support the\nRangeley/Avoton parts as well.\nBecause that was not complicated enough already Stefan Tauner refactored\nand refined everything. Bay Trail seems to be the first Atom SoC able to\nsupport hwseq. No SPI Programming Guide could be obtained so it is\nhandled similarly to Lynx Point which seems to be its nearest relative.\n\nCorresponding to flashrom svn r1844.\n\nSigned-off-by: Duncan Laurie \u003cdlaurie@chromium.org\u003e\nSigned-off-by: Martin Roth \u003cgaumless@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Marc Jones \u003cmarcj303@gmail.com\u003e\nTested-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Thomas Reardon \u003cthomas_reardon@hotmail.com\u003e\nTested-by: Wen Wang \u003cwen.wang@adiengineering.com\u003e\nAcked-by: Marc Jones \u003cmarcj303@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "2ba9f6ebe56b208a1fb0b0ce5edf81097a0158be", "tree": "06741544f702c84fa5fcbc5edb8a888530917481", "parents": [ "9e3a6984da1bb38af37ce4bb54af8f7475b7c766" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:19 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 20 15:39:19 2014 +0000" }, "message": "Refine Flash Component descriptor handling\n\nPossible values as well as encodings have changed in newer chipsets as follows.\n - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all\n operations\n - Since Cougar Point the chipsets support dual output fast reads (encoded\n in bit 30).\n - Flash component density encoding has changed from 3 to 4 bits with Lynx\n Point, currently allowing for up to 64 MB chips.\n\nCorresponding to flashrom svn r1843.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "7608d368fcd566a60ab47755eb1c9263ca9d7b35", "tree": "89281c1e08bcc265ac38ba1f1497462f97627fbc", "parents": [ "18f509780a3eb76ffe31b4bfc24016c408dec537" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 05 23:28:47 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 05 23:28:47 2014 +0000" }, "message": "ichspi: fix missing set_addr on erases and possible crossings of 256 B boundaries\n\nApparently the erase function did never set any address before issuing the\nerase commands. How could this ever work?\nAlso, according to PCH documentation crossing 256 byte boundaries is invalid\nand may cause wraparound due to the flash chip\u0027s pages. Check for this on\nreads as well as writes.\n\nThanks to Vladimir \u0027φ-coder/phcoder\u0027 Serbinenko for noticing these issues\nand providing the initial patch.\n\nCorresponding to flashrom svn r1837.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a5bcbceb581f27cfc0055369d3dd9cfd1ae00bfa", "tree": "5daecd880a16b7011be28e064fb7550f3e6b7e58", "parents": [ "82b6ec1df30d3fca55547f230c76718d6e613b2a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "message": "Rename programmer registration functions\n\nRegister_programmer suggests that we register a programmer. However,\nthat function registers a master for a given bus type, and a programmer\nmay support multiple masters (e.g. SPI, FWH). Rename a few other\nfunctions to be more consistent.\n\nCorresponding to flashrom svn r1831.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f20b7beff054eb316088d590094d9efbc68dbee1", "tree": "6324be451385c9f9cea27381f35f300fbaa7f454", "parents": [ "20da4aa82cc11f25a6a4a52fd2bed219e6e1d829" ], "author": { "name": "Mark Marshall", "email": "mark.marshall@omicron.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "message": "Add \u0027const\u0027 keyword to chip write and other function prototypes\n\nCorresponding to flashrom svn r1789.\n\nInspired by and mostly based on a patch\nSigned-off-by: Mark Marshall \u003cmark.marshall@omicron.at\u003e\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "92d6a861ce0e4727c911fd8d6aeba312b805f765", "tree": "ae9e39df5b092aea28d5193054cc66a53525f233", "parents": [ "8d7ec2a209073ce4a403378fa6c828397f5011e9" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Oct 25 00:33:37 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Oct 25 00:33:37 2013 +0000" }, "message": "Refactor Intel Chipset Enables\n\n - Combine enable_flash_ich_4e() and enable_flash_ich_dc() to\n enable_flash_ich_fwh().\n - Remove unjustified (chipset) name parameters from various\n enable_flash_ich* functions.\n - Make Poulsbo and Tunnel Creek use generic enables by refining existing\n functions to work with them, including everything in ichspi.c.\n - Refactor enable_flash_ich_fwh_decode() to be called unconditionally for\n all chipsets.\n - Add support for Intel Atom Centerton (S12x0).\n - Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally\n anyway.\n - Move spibar handling out of ich_init_spi() into enable_flash_ich_spi()\n - Various small cleanups.\n\nCorresponding to flashrom svn r1761.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "7fb5aa049bee3c685835dc24c8184c5897e4a6bd", "tree": "3d193e98d25da24307824ab8d0939f3538ec2e50", "parents": [ "36e9f4b3595c6e8b13f80f85785a91b65ecad62f" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 14 15:48:44 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Aug 14 15:48:44 2013 +0000" }, "message": "Automatically unmap physmap()s\n\nSimilarly to the previous PCI self-clean up patch this one allows to get rid\nof a huge number of programmer shutdown functions and makes introducing\nbugs harder. It adds a new function rphysmap() that takes care of unmapping\nat shutdown. Callers are changed where it makes sense.\n\nCorresponding to flashrom svn r1714.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "dbac46c3efd6858212280c7ae6854bb0c9f93b7a", "tree": "8188320a07f63b187c21f902ac238fe7a513225c", "parents": [ "20a36baf56afac4896c8abe5a94dbe974a25dbc9" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 13 22:10:41 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 13 22:10:41 2013 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 19\n\nTested mainboards:\nOK:\n - ASUS P8H77-V LE\n http://www.flashrom.org/pipermail/flashrom/2013-June/011127.html\n - HP Pegatron IPMEL-AE (Evans-GL6)\n Reported by Idwer on IRC\n - MSI MS-7379 (G31M)\n http://paste.flashrom.org/view.php?id\u003d1726\n - MSI MS-7816 (H87-G43)\n http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html\n - MSI MS-9830 (IM-945GSE-A, A9830IMS)\n http://paste.flashrom.org/view.php?id\u003d1730\n - Supermicro X8SAX\n http://paste.flashrom.org/view.php?id\u003d1717\nNOT OK:\n - Intel D2700MUD\n http://paste.flashrom.org/view.php?id\u003d1723\n - Intel DQ45CB\n http://www.flashrom.org/pipermail/flashrom/2013-August/011369.html\n\nChipsets:\n - Add PCI ID for Intel\u0027s Coleto Creek.\n - Mark Intel H87 (0x8c4a) as OK.\n http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html\n\nMiscellaneous:\n - ichspi: Fix printing address ranges if space is divided by FPB.\n - Tiny other stuff.\n\nCorresponding to flashrom svn r1709.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "27cb34b8a99e863cf7ed3a0098c55b059889b80e", "tree": "8131ce99aa05f74583e67157c85bf09f707b6eab", "parents": [ "efe2d43056bcc15d70903354c6410a498b56b285" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jun 01 00:06:12 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jun 01 00:06:12 2013 +0000" }, "message": "Change warning regarding protected ICH regions\n\nThere is no good reason to collect further log files of locked Intel-\nbased boards. Forward affected users directly to an explanation in\nthe wiki instead.\n\nCorresponding to flashrom svn r1675.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "67d163d2fa6e7db9673e8ec820b8ef21bca5e907", "tree": "3cfa28408caa64594638f4a5cad7f5deafa8506a", "parents": [ "8225868465f6ad75958a1f81514d9c4978487184" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Jan 15 17:37:48 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Jan 15 17:37:48 2013 +0000" }, "message": "Fix duplicate \u0027const\u0027 declaration specifiers\n\nThanks to Idwer and clang for noticing these problems.\n\nCorresponding to flashrom svn r1646.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nSigned-off-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "c6fa32d2b5c08d2fcc92fee2974a3fc02a3ca1f7", "tree": "7ac561c734007cfe88577cdad895f87524e3184f", "parents": [ "5561955b1158e8bd29299735abef1e26a5a9cdbc" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jan 04 22:54:07 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jan 04 22:54:07 2013 +0000" }, "message": "Introduce msg_*warn\n\nAlso, unify all outputs of \"Warning:\" and \"Error:\" to use normal\ncapitalization instead of mixing it with all capitals.\n\nCorresponding to flashrom svn r1643.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\n" }, { "commit": "d7d423bbc1d2564c60daaecd9ab1dca3843c5fea", "tree": "bc9d591677afbe3dae8f9a01a70f95f9487982a7", "parents": [ "99f947ddc8156eb37b5dafc076480f405c9be0b6" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Oct 20 09:13:16 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Oct 20 09:13:16 2012 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 15\n\nTested Mainboards:\nOK:\n - Foxconn P55MX\n http://www.flashrom.org/pipermail/flashrom/2012-October/010002.html\n\nTested flash chips:\n - Eon EN25F64 to PR (+PR)\n http://paste.flashrom.org/view.php?id\u003d1426\n - Macronix MX25L1005 to PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2012-October/010004.html\n - Set SST39VF512 to PREW (+W)\n http://www.flashrom.org/pipermail/flashrom/2012-September/009958.html\n\nTested chipsets:\n - Z77 (only reading was really tested)\n\nMiscellaneous:\n - Fix ft2232_spi\u0027s parameter parsing.\n - Fix nicrealtek\u0027s init (always segfaulted since r1586 oops).\n - Add another T60 variant to the laptop whitelist.\n - Improve message shown when image file size does not match flash chip\n - Refine messages regarding the flash descriptor override strap according\n to the findings by Vladislav Bykov on his P55MX.\n - Fix the ID of EN25F64.\n - Demote and clarify debug message in serprog_delay().\n - Minor other cleanups.\n\nCorresponding to flashrom svn r1613.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "eb58257b9650b9191d8b987e0b214fed1ad2b77a", "tree": "8e37e169514dfba6083cc6f8c18943e69b81e9a4", "parents": [ "3c0fcd0f30f2b3c0df57b66e645859d923e68d16" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:52:50 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:52:50 2012 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 14\n\nTested Mainboards:\nOK:\n - ASUS M3A78-EH\n http://www.flashrom.org/pipermail/flashrom/2010-October/005297.html\n - ASUS P2B-LS\n http://www.flashrom.org/pipermail/flashrom/2010-November/005506.html\n - Biostar TA790GX A3+\n http://paste.flashrom.org/view.php?id\u003d1350\n - ECS 848P-A7\n http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html\n - GIGABYTE GA-G41MT-S2PT\n Reported on IRC\n - GIGABYTE GA-H77-D3H\n Reported and tested by Alexander Gordeev on IRC.\n - Gigabyte GA-X79-UD5\n http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html\n - Shuttle FN78S\n http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html\n - VIA EITX-3000\n Reported on IRC by Tuju\n\nNOT OK:\n - Dell PowerEdge C6220 (0HYFFG)\n http://www.flashrom.org/pipermail/flashrom/2012-September/009900.html\n - Foxconn Q45M\n http://www.flashrom.org/pipermail/flashrom/2012-September/009923.html\n - MSI MS-7309 (K9N6SGM-V)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009712.html\n - Supermicro X9QRi-F+\n http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html\n - ZOTAC H61-ITX WiFi (H61ITX-A-E)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009649.html\n\nASUS CUSL2-C has been tested to be working with the board enable once\nimplemented for the TUSL2-C board. They seem to have the same PCI IDs\nas shown in the links below. Since only the CUSL2-C board enable has been\ntested yet, we distinguish the two by DMI strings.\nhttp://paste.flashrom.org/view.php?id\u003d1393\nhttp://www.flashrom.org/pipermail/flashrom/attachments/20091206/ddca2c6c/attachment-0002.eml\n\nTested flash chips:\n - Set EMST F25L008A to PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009714.html\n - Set GigaDevice GD25Q64 to PREW (+PREW)\n http://git.chromium.org/gitweb/?p\u003dchromiumos/third_party/flashrom.git;a\u003dcommit;h\u003d9e8ef49b1f626c2197e131fba6c5b65c8af4eeea\n - Set Macronix MX25L12805 to P (+P)\n http://www.flashrom.org/pipermail/flashrom/2012-September/009887.html\n - Set SST SST49LF003A/B to PREW (+EW)\n http://paste.flashrom.org/view.php?id\u003d467\n - Set Winbond W49V002FA to PREW (+EW)\n http://www.flashrom.org/pipermail/flashrom/2011-January/005781.html\n\nTested chipsets:\n - Intel X79 (0x1d41)\n http://www.flashrom.org/pipermail/flashrom/2012-August/009811.html\n\nBoard enables:\n - add ASUS P4P800-X\n Created by Idwer Vollering and tested by Mingsen Bao:\n http://paste.flashrom.org/view.php?id\u003d467\n - add DMI string to P4P800-VM\n\nMiscellaneous:\n - Add remaining Intel 7 series chipset (LPC) PCI IDs\n - Add generic SPI detection for chips from Winbond\n - Minor manpage changes\n - Minor other cleanups\n - Escape full stops after abbreviations in the manpage.\n - Add ICH9 and successors to spi_get_valid_read_addr\n\nCorresponding to flashrom svn r1601.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "e3adea08648c4ba0e0ebed702aba0adcf21e3925", "tree": "f4778bb3185cccc43c0c19f1415b54527e4b8943", "parents": [ "98f4710b579296b336dfa11a7e98df08d05710c7" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Aug 27 15:12:36 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Aug 27 15:12:36 2012 +0000" }, "message": "ichspi: ignore bogus FREGs\n\nSome vendors forget to disable regions properly and set their FRAP bits\nand FREG to 0. While not documented publicly this is being ignored by the\nchipset(s)[1] and hence flashrom should do so too. Without this patch\nflashrom prints a warning and disables writes.\nThe check for i (region index) excludes the descriptor region which should not\nbe becessary because specs suggest that the descriptor region should not\nbe locked, but if vendors would follow the specs this patch would not have\nbeen necessary in the first place.\n\n[1]: http://www.flashrom.org/pipermail/flashrom/2012-May/009303.html\n\nCorresponding to flashrom svn r1587.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5a7cb847f096dacb0bf96b3aa909f79d76ae8204", "tree": "da511e990c1fdded61ee5dcefae38314c3a5a6cc", "parents": [ "dd73d830f7370b5f0bbdaa0780b0ff8d6ff1776a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Aug 25 01:17:58 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Aug 25 01:17:58 2012 +0000" }, "message": "Make struct flashchip a field in struct flashctx instead of a complete copy\n\nAll the driver conversion work and cleanup has been done by Stefan.\nflashrom.c and cli_classic.c are a joint work of Stefan and Carl-Daniel.\n\nCorresponding to flashrom svn r1579.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "dd73d830f7370b5f0bbdaa0780b0ff8d6ff1776a", "tree": "a8dff9c93a15d97e3af756ab3481e6c8080b5c17", "parents": [ "b4e06bde9b2a91d05c31b709d633464fca1c8815" ], "author": { "name": "Helge Wagner", "email": "Helge.Wagner@ge.com", "time": "Fri Aug 24 23:03:46 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Aug 24 23:03:46 2012 +0000" }, "message": "Fix VIA VX*** support\n\nHelge Wagner\u0027s patch that added VIA VX900 chipset support made me look\ncloser at the datasheets which led to some concise documentation about\nnewer VIA chipsets: http://flashrom.org/VIA\n\nBased on that this patch adds full support for VX800/VX820, VX855/VX875\nand VX900, including SPI and LPC. VT8237S was not changed (SPI support\nonly) because there is no public datasheet and it is not clear how to\ndistinguish between LPC and SPI strapping and investigations in (NDAed)\ndocuments have not brought up anything conclusively.\n\nenable_flash_vt823x could probably be enhanced too due to various\nignored LPC options of the chipset.\n\nCorresponding to flashrom svn r1578.\n\nSigned-off-by: Helge Wagner \u003cHelge.Wagner@ge.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nTested-by: Alexandru Gagniuc \u003cmr.nuke.me@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "d94d25d75be771eec26578355dc5c70cfb3e9c73", "tree": "d2cb1083a5fa9dd1274213c17bc4ede903913d3d", "parents": [ "a0fce5f459871840166348de1451fd8cd8bb9cb8" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jul 28 03:17:15 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Jul 28 03:17:15 2012 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 13\n\nTested Mainboards:\nOK:\n - ASRock A780FullHD\n http://www.flashrom.org/pipermail/flashrom/2012-July/009599.html\n - ASRock 880G Pro3\n http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html\n - ASRock N61P-S\n http://www.flashrom.org/pipermail/flashrom/2012-May/009316.html\n - ASUS M2N68-VM\n http://www.flashrom.org/pipermail/flashrom/2012-May/009334.html\n - ASUS M3N78 PRO\n http://www.flashrom.org/pipermail/flashrom/2012-July/009519.html\n - ASUS M4N68T V2\n http://www.flashrom.org/pipermail/flashrom/2012-May/009277.html\n - ASUS M5A78L-M LX\n reported by clavile on IRC\n - ASUS P8P67 PRO (rev. 3.0)\n http://www.flashrom.org/pipermail/flashrom/2012-April/009188.html\n - ASUS P8Z68-V\n reported by Kano on IRC\n http://paste.flashrom.org/view.php?id\u003d1232\n - ASUS SABERTOOTH 990FX\n http://paste.flashrom.org/view.php?id\u003d1214\n - Dell Inspiron 1420\n http://www.flashrom.org/pipermail/flashrom/2012-May/009196.html\n - ECS GF8200A\n http://www.flashrom.org/pipermail/flashrom/2012-May/009256.html\n - GIGABYTE GA-H61M-D2H-USB3\n http://www.flashrom.org/pipermail/flashrom/2012-May/009333.html\n - MSI MS-7250 (K9N SLI (rev 2.1))\n http://www.flashrom.org/pipermail/flashrom/2012-June/009436.html\n - MSI MS-7676 (Z68MA-G45 (B3))\n http://www.flashrom.org/pipermail/flashrom/2012-June/009424.html\n - Palit N61S\n http://www.flashrom.org/pipermail/flashrom/2012-May/009212.html\n\nNOT OK:\n - ASRock H61M-ITX\n http://www.flashrom.org/pipermail/flashrom/2012-May/009224.html\n - Dell Latitude E6520\n http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html\n - Dell Vostro 3700\n http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html\n - Intel DH61AG\n http://www.flashrom.org/pipermail/flashrom/2012-June/009417.html\n - Intel DQ965GF\n http://www.flashrom.org/pipermail/flashrom/2012-May/009295.html\n - HP/Compaq 8100 Elite CMT PC (304Bh)\n http://paste.flashrom.org/view.php?id\u003d1182\n - HP Z400 Workstation (0AE4h)\n http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html\n - Supermicro X9DR3-F\n http://www.flashrom.org/pipermail/flashrom/2012-June/009422.html\n \n\nTested flash chips:\n - mark AMIC A25L032 as TEST_OK_PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2012-June/009363.html\n - mark Atmel AT25DF321A as TEST_OK_PREW (+REW)\n http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html\n - mark Atmel AT26DF161 as TEST_OK_PR (+PR)\n http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html\n - mark Eon EN25QH16 as TEST_OK_PR (+PR)\n http://www.flashrom.org/pipermail/flashrom/2012-July/009566.html\n - mark SST SST39VF010 as TEST_OK_PREW (+W)\n http://www.flashrom.org/pipermail/flashrom/2012-June/009425.html\n - mark ST M25P64 as TEST_OK_PREW (+PREW)\n http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html\n\nTested chipset enables:\n - Intel 3420\n http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html\n\n - Add board enable for ASUS P5GD2-X\n lspci: http://paste.flashrom.org/view.php?id\u003d1234\n write: http://paste.flashrom.org/view.php?id\u003d1240\n\nMiscellaneous\n - Reorder some boards in print.c.\n - Remove broken abit URLs.\n - Whitespace changes.\n - Fix the maximum number of southbridge straps in the ICH descriptor structs.\n - Refine documentation regarding ICH region lock bits.\n - Demote verbosity of ICH Opcode reprogramming to -VV.\n - Exclude Pony-SPI for DOS targets (missing serial support).\n\nCorresponding to flashrom svn r1554.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "32508eb304428551cff40b291d44823aafec7574", "tree": "0641d77a791290f6842fd60446e87871f6867651", "parents": [ "3834c2d7e5a08e09e580be0dc7f9369c941b2a70" ], "author": { "name": "Patrick Georgi", "email": "patrick.georgi@secunet.com", "time": "Fri Jul 20 20:35:14 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jul 20 20:35:14 2012 +0000" }, "message": "Hide hwaccess.h from public API\n\nMove hwaccess.h #include from flash.h to individual drivers.\nlibflashrom users need flash.h, but they do not care about hwaccess.h\nand should not see its definitions because they may conflict with\nother hardware access functions and #defines used by the libflashrom\nuser.\n\nCorresponding to flashrom svn r1549.\n\nSigned-off-by: Patrick Georgi \u003cpatrick.georgi@secunet.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "7bca126561b80f626dea269d7a6284a7cde0a8ed", "tree": "45c6b31e39846a88d89d157d758134d7b8dc1db1", "parents": [ "3464d05eb41ab4c7a6faba9a1a36bfbeda0de850" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jun 15 22:28:12 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jun 15 22:28:12 2012 +0000" }, "message": "Let the programmer driver decide how to do AAI transfers\n\nCurrently spi_aai_write() is implemented without an abstraction\nmechanism for the programmer driver. This adds another function\npointer \u0027write_aai\u0027 to struct spi_programmer, which is set to\ndefault_spi_write_aai (renamed spi_aai_write) for all programmers\nfor now.\n\nA patch which utilises this abstraction in the dediprog driver will\nfollow.\n\nCorresponding to flashrom svn r1543.\n\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "dc704edad44995845727a231e3f1d6dda74708fd", "tree": "5f844aeb34346307f2b6dd7693bd6388a057ed5b", "parents": [ "e5449392a12cfbdbdf48ebfdaf713dae5d6dec56" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun May 06 15:11:26 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun May 06 15:11:26 2012 +0000" }, "message": "Refine reprogram_opcode_on_the_fly to indicate wrong readcnt/writecnt combinations\n\nCorresponding to flashrom svn r1531.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "ac427b22c4fa45936fe94af31a5e0422dd95c152", "tree": "185514486da4a8d244f71ba62f18261d948cd631", "parents": [ "8541d2312150943069bb96addeed564769057af2" ], "author": { "name": "Paul Menzel", "email": "paulepanter@users.sourceforge.net", "time": "Thu Feb 16 21:07:07 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Feb 16 21:07:07 2012 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 10\n\nTested mainboards:\nOK:\n - ABIT A-S78H\n http://www.flashrom.org/pipermail/flashrom/2012-January/008603.html\n - ASRock AM2NF6G-VSTA\n http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html\n - ASUS KFSN4-DRE/SAS\n reported by ted on IRC\n - ASUS M2A-VM (HDMI variant)\n http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html\n - ASUS M4N78 PRO\n http://www.flashrom.org/pipermail/flashrom/2012-January/008598.html\n - ASUS P5K-V\n http://www.flashrom.org/pipermail/flashrom/2012-February/008737.html\n - ASUS P5KPL-CM\n http://www.flashrom.org/pipermail/flashrom/2012-January/008522.html\n - ASUS P5N7A-VM\n http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html\n - ASUS P5QPL-AM\n http://www.flashrom.org/pipermail/flashrom/2012-January/008557.html\n - ECS GF7100PVT-M3\n http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html\n - ECS K7SEM\n http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html\n - ECS P4M800PRO-M V2.0\n http://www.flashrom.org/pipermail/flashrom/2012-January/008478.html\n - Gigabyte 880GMA-USB3\n http://www.flashrom.org/pipermail/flashrom/2012-February/008715.html\n - Gigabyte GA-EP31-DS3L\n http://www.flashrom.org/pipermail/flashrom/2012-January/008601.html\n - Gigabyte GA-X58A-UDR3\n http://www.flashrom.org/pipermail/flashrom/2012-January/008572.html\n - Gigabyte GA-Z68XP-UD3\n http://paste.flashrom.org/view.php?id\u003d1058\n - HP ProLiant N40L\n http://www.flashrom.org/pipermail/flashrom/2012-February/008650.html\n - MSI MS-7309 (K9N6PGM2-V2)\n http://www.flashrom.org/pipermail/flashrom/2011-December/008441.html\n - MSI MS-7548 (Aspen-GL8E used in HP Pavilion a6750f)\n http://www.flashrom.org/pipermail/flashrom/2012-February/008666.html\n - MSI MS-7676 (H67MA-ED55(B3))\n http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html\n - PC Engines Alix.6f2\n Reported by Philip Prindeville on IRC\n - Shuttle AV18E2\n http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html\n - Supermicro X8DTE-F\n http://www.flashrom.org/pipermail/flashrom/2011-November/008304.html\n - Supermicro X8DTT-HIBQF\n http://www.flashrom.org/pipermail/flashrom/2012-January/008520.html\nNOT OK:\n - ASUS P8H61-M LE/USB3\n http://www.flashrom.org/pipermail/flashrom/2012-January/008491.html\n - ASUS P8H67-M PRO\n http://www.flashrom.org/pipermail/flashrom/2011-December/008321.html\n - ASUS P8Z68-V PRO\n http://www.flashrom.org/pipermail/flashrom/2012-January/008469.html\n - Clevo P150HM (laptop)\n http://www.flashrom.org/pipermail/flashrom/2012-February/008717.html\n - Intel D425KT\n http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html\n - Supermicro X9SCA-F\n http://www.flashrom.org/pipermail/flashrom/2011-December/008313.html\n\nTested flash chips:\n - mark AT29C512 as TEST_OK_PREW\n http://paste.flashrom.org/view.php?id\u003d977\n - mark M25P40 as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-December/008351.html\n - mark M25PE80 as TEST_OK_PREW\n http://paste.flashrom.org/view.php?id\u003d1061\n - mark MX25L6405 as TEST_OK_PREW\n tested myself with an MX25L6436E variant on serprog\n - mark W39V080A as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html\n\nTested chipsets:\n - SiS 730 (:0730)\n http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html\n - NVIDIA MCP61 (:03e0)\n http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html\n - NVIDIA MCP73 (:07d7)\n http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html\n - NVIDIA MCP79 (:0aac)\n http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html\n - VIA VT82C69x (0691) and VT82C686A/B (:0686)\n http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html\n\n - AMD\u0027s SB950 (and presumably also SB920) have the same PCI ID as previous\n generations, hence change the chipset enable device string. Thanks to\n Christian Ruppert for the suggestion.\n - Fix the board enable of the abit NF-M2 nView which had the IDs of its onboard\n graphics card in its pattern. Change this to the LPC controller.\n - Intel X79 SPI registers are identical to 6 Series\u0027, so use the chipsetenable\n wrapper of it (enable_flash_pch6).\n - Fix two paranoid checks for address \u003c 0 in ichspi.c which became futile (and\n generate clang warnings) with the unsignify patch committed in r1470.\n - Rename AT25DF641 to AT25DF641(A). They are almost idencical, but could\n be distinguished by an extended RDID probe (Atmel\u0027s patented EDI procedure),\n which we do not support yet, hence handle them as one model for now.\n - Source format fixes and typos\n\nCorresponding to flashrom svn r1499.\n\nthe addition of the ASRock AM2NF6G-VSTA to print.c is\nSigned-off-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\neverything else is\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5210e72d136158ccadfb1b5641eb20ce34066f25", "tree": "2b02a07f60949c1e0fa8434b3dbc807a27a09e2b", "parents": [ "65922a3860654676ece5de12fa21abac49e21e5e" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Feb 16 01:13:00 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Feb 16 01:13:00 2012 +0000" }, "message": "ichspi.c: warn user and disable writes when a protected address range is detected\n\nThis includes not only the notorious read-only flash descriptors and locked ME\nregions, but also the more rarely used PRs (Protected Ranges).\nThe user can enforce write support by specifying ich_spi_force\u003dyes in the\nprogrammer options, but we don\u0027t tell him the exact syntax interactively. He\nhas to read it up in the man page.\n\nCorresponding to flashrom svn r1494.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "c40cff7b86848f5b248d7fcf20f7d517b60c385d", "tree": "7f9db61c7b4868e513c4702cfe57bb35ae695266", "parents": [ "8a3c60cdd0e5632173567923ae1927763e31e857" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Dec 20 00:19:29 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Dec 20 00:19:29 2011 +0000" }, "message": "Have all programmer init functions register bus masters/programmers\n\nAll programmer types (Parallel, SPI, Opaque) now register themselves\ninto a generic programmer list and probing is now programmer-centric\ninstead of chip-centric.\nRegistering multiple SPI/... masters at the same time is now possible\nwithout any problems. Handling multiple flash chips is still unchanged,\nbut now we have the infrastructure to deal with \"dual BIOS\" and \"one\nflash behind southbridge and one flash behind EC\" sanely.\n\nA nice side effect is that this patch kills quite a few global variables\nand improves the situation for libflashrom.\n\nHint for developers:\nstruct {spi,par,opaque}_programmer now have a void *data pointer to\nstore any additional programmer-specific data, e.g. hardware\nconfiguration info.\n\nNote:\nflashrom -f -c FOO -r forced_read.bin\ndoes not work anymore. We have to find an architecturally clean way to\nsolve this.\n\nCorresponding to flashrom svn r1475.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "8a3c60cdd0e5632173567923ae1927763e31e857", "tree": "3a5514d022392cf4d8fa368f9f02653da21a93ca", "parents": [ "63fd9026f1e82b67a65072fda862ba7af35839e1" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "message": "Add struct flashctx * parameter to all functions accessing flash chips\n\nAll programmer access function prototypes except init have been made\nstatic and moved to the respective file.\n\nA few internal functions in flash chip drivers had chipaddr parameters\nwhich are no longer needed.\n\nThe lines touched by flashctx changes have been adjusted to 80 columns\nexcept in header files.\n\nCorresponding to flashrom svn r1474.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "63fd9026f1e82b67a65072fda862ba7af35839e1", "tree": "7d9ffba077715cf9e75c9f4a36d0d7f11a3181f6", "parents": [ "83c92e983aaf11fb6f5bafb6744275c50add193c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Dec 14 22:25:15 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Dec 14 22:25:15 2011 +0000" }, "message": "Use struct flashctx instead of struct flashchip for flash chip access\n\nStruct flashchip is used only for the flashchips array and for\noperations which do not access hardware, e.g. printing a list of\nsupported flash chips.\n\nstruct flashctx (flash context) contains all data available in\nstruct flashchip, but it also contains runtime information like\nmapping addresses. struct flashctx is expected to grow additional\nmembers over time, a prime candidate being programmer info.\nstruct flashctx contains all of struct flashchip with identical\nmember layout, but struct flashctx has additional members at the end.\n\nThe separation between struct flashchip/flashctx shrinks the memory\nrequirement of the big flashchips array and allows future extension\nof flashctx without having to worry about bloat.\n\nCorresponding to flashrom svn r1473.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "c69c9c84e0341b701d9966fea8ce54d4e017bbb7", "tree": "2ea0b12abf9dd3483246423752239b88c6d7942e", "parents": [ "8ca4255d7968dbf6301367074cc7267d22a25658" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Nov 23 09:13:48 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Nov 23 09:13:48 2011 +0000" }, "message": "Unsignify lengths and addresses in chip functions and structs\n\nPush those changes forward where needed to prevent new sign\nconversion warnings where possible.\n\nCorresponding to flashrom svn r1470.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "745f6bbec2acf6a94111df385384067b01f6e567", "tree": "a566034a3539063a27b64dc4a523f0d724404395", "parents": [ "eaacd2d4e7485d747e4e0bbd54b7bb44cf3fd179" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Nov 13 15:17:10 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Nov 13 15:17:10 2011 +0000" }, "message": "ichspi: fix ich_init_opcodes() calls in ich_init_spi()\n\nBy calling it early ichspi_lock was not set up correctly in accordance\nwith the corresponding register, hence ich_init_opcodes() was always\ntrying to programming the opcodes instead of reading them in from the\nopmenu in case of a locked down configuration.\n\nThanks to Jonathan A. Kollasch for reporting this bug.\n\nCorresponding to flashrom svn r1464.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "eaacd2d4e7485d747e4e0bbd54b7bb44cf3fd179", "tree": "5e023363074cbe351bc6ded9f20c3f116e6c6f1c", "parents": [ "f382e352ac63108ec0f912ff52b538c99f46c340" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Nov 09 23:40:00 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Nov 09 23:40:00 2011 +0000" }, "message": "Register Parallel/LPC/FWH programmers the same way SPI programmers are registered\n\nAll programmers are now calling programmer registration functions and\ndirect manipulations of buses_supported are not needed/possible anymore.\n\nNote: Programmers without parallel/LPC/FWH chip support should not call\nregister_par_programmer().\n\nAdditional fixes:\nSet max_rom_decode.parallel for drkaiser.\nRemove abuse of programmer_map_flash_region in it85spi.\nAnnotate several FIXMEs in it85spi.\n\nCorresponding to flashrom svn r1463.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "f382e352ac63108ec0f912ff52b538c99f46c340", "tree": "524ef8de4281cf635f762607778d3e23c1e9311f", "parents": [ "50e7c603f7bd56c51b3f5f34ce8e8cd61074bbcf" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Nov 08 11:55:24 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Nov 08 11:55:24 2011 +0000" }, "message": "ichspi: print flash descriptor dependent information only when it is valid\n\nAlso, fix some coding style issues.\n\nCorresponding to flashrom svn r1462.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "50e7c603f7bd56c51b3f5f34ce8e8cd61074bbcf", "tree": "5aea00e4af9093f6fca3af0f1534ede33ad98f35", "parents": [ "a8d838d9d3a0373b51408a2ecb647c320e1aaff9" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Nov 08 10:55:54 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Nov 08 10:55:54 2011 +0000" }, "message": "ichspi: add support for Intel Hardware Sequencing\n\nBased on the new opaque programmer framework this patch adds support\nfor Intel Hardware Sequencing on ICH8 and its successors.\n\nBy default (or when setting the ich_spi_mode option to auto)\nthe module tries to use swseq and only activates hwseq if need be:\n- if important opcodes are inaccessible due to lockdown\n- if more than one flash chip is attached.\nThe other options (swseq, hwseq) select the respective mode (if possible).\n\nA general description of Hardware Sequencing can be found in this blog entry:\nhttp://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/\n\nBesides adding hwseq this patch also introduces these unrelated changes:\n\n- Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi.\n The whole error handling looks a bit odd to me, so this patch does\n change very little. Also, it does not touch the tunnelcreek method,\n which should be refactored anyway.\n\n- Add null-pointer guards to find_opcode and find_preop\n to matches the other opcode methods better:\n curopcodes \u003d\u003d NULL has some meaning and is actively used/checked in\n other functions.\n\nTODO: adding real documentation when we have a directory for it\n\nCorresponding to flashrom svn r1461.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "a8d838d9d3a0373b51408a2ecb647c320e1aaff9", "tree": "8524bb99c9ff890da6311769656a6480abb0a1d5", "parents": [ "532c717bccc95aa93bae7af8be0695bee83c32b5" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Nov 06 23:51:09 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Nov 06 23:51:09 2011 +0000" }, "message": "ichspi: use a variable to distinguish ich generations instead of spi_programmer-\u003etype\n\nThe type member is enough most of the time to derive the wanted\ninformation, but\n - not always (e.g. ich_set_bbar),\n - only available after registration, which we want to delay till the\n end of init, and\n - we really want to distinguish between chipset version-grained\n attributes which are not reflected by the registered programmer.\n\nHence this patch introduces a new static variable which is set up\nearly by the init functions and allows us to get rid of all \"switch\n(spi_programmer-\u003etype)\" in ichspi.c. We reuse the enum introduced\nfor descriptor mode for the type of the new variable.\n\nPreviously magic numbers were passed by chipset_enable wrappers. Now\nthey use the enumeration items too. To get this working the enum\ndefinition had to be moved to programmer.h.\n\nAnother noteworthy detail: previously we have checked for a valid\nprogrammer/ich generation all over the place. I have removed those\nchecks and added one single check in the init method. Calling any\nfunction of a programmer without executing the init method first, is\nundefined behavior.\n\nCorresponding to flashrom svn r1460.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "d0c5dc23e25f33439dd6166a5798ffbcaabf67f8", "tree": "46817260e91768863e9815741486d0f1b0a804bc", "parents": [ "836b26a423c5dad86646bc6bc24560d444181405" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Oct 20 12:57:14 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Oct 20 12:57:14 2011 +0000" }, "message": "ichspi: add (partially) dead support code for Intel Hardware Sequencing\n\nThis was done to ease the review. Another patch will hook up (and\nexplain) this code later.\n\nCorresponding to flashrom svn r1452.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "e3185c0599d77c06b9665c9721649b96108c894f", "tree": "a01dcf9a4d5caf86935037d9286c9d8b3a8ffaf6", "parents": [ "d196e7c1387b30ac35e7b0f605c79823ac9b5ec9" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 15:15:31 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 15:15:31 2011 +0000" }, "message": "ichspi: inform the user about the consequences of the security override strap\n\nIbex Peak SPI Programming Guide:\nThe PCH has a mechanism to set up to 5 address ranges from HOST access. These are\ndefined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT\nunlocked by assertion of Flash descriptor Override.\n\nAlso, the datasheets mention the bit in their description of FRAP but not PR[N].\n\nCorresponding to flashrom svn r1449.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "75da80c17bbb992ce2b60ae15ef2fba7d23bfd8e", "tree": "a332b8d1e0aa6b8bd1a15ca78db9bb942d5af2ff", "parents": [ "bf69aaa9ca14430c95f1506a77520e3eb540d315" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 22:21:55 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 22:21:55 2011 +0000" }, "message": "ichspi: unlock PR register restrictions on ICH8+ if not locked down\n\nTested-by: Shailendra Sodhi\n(predecessor/proof of concept patch)\nhttp://www.flashrom.org/pipermail/flashrom/2011-August/007717.html\n\nCorresponding to flashrom svn r1447.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "bf69aaa9ca14430c95f1506a77520e3eb540d315", "tree": "a6f37988bb9cb3a36db2e7b936c8d8cc181ccf9a", "parents": [ "7783f31249f55a452ed9dac806d27ccec59ce203" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 21:21:48 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 21:21:48 2011 +0000" }, "message": "ichspi: add prettyprinting for PR registers on ICH8+\n\nCorresponding to flashrom svn r1446.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "7783f31249f55a452ed9dac806d27ccec59ce203", "tree": "f47fa6421f4b61cd9cea6294dff909a2c1bc363e", "parents": [ "84e1ddea5f49b59d99ead53d9ed31ada107aae97" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 21:21:42 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 21:21:42 2011 +0000" }, "message": "ichspi: don\u0027t touch the nonexistent(?) BBAR register on ICH8\n\nThere is no sign of BBAR (BIOS Base Address Configuration Register)\nin the public datasheet (or specification update) of the ICH8. Also,\nthe offset of that register has changed between ICH7 (SPIBAR + 50h)\nand ICH9 (SPIBAR + A0h), so we have no clue if or where it is on\nICH8. Better don\u0027t try to touch it at all and assume/hope it is 0.\n\nCorresponding to flashrom svn r1445.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "84e1ddea5f49b59d99ead53d9ed31ada107aae97", "tree": "b274f6b1565e7f63344fbf08f1488606f789e12a", "parents": [ "1e14639f4268c21a9200fe45a8c8235472cde1c2" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 19:53:11 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 17 19:53:11 2011 +0000" }, "message": "ichspi: improve prettyprint_opcodes\n\nAdd headers for the columns and some decoding into human readable format.\n\nCorresponding to flashrom svn r1444.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "1e14639f4268c21a9200fe45a8c8235472cde1c2", "tree": "522d54a0740bb86c1e3307823a09c37098dfe667", "parents": [ "c93f5f123239121fdeba03c02f9e448ed97c52a4" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 15 23:52:55 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Sep 15 23:52:55 2011 +0000" }, "message": "ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD\n\nBased on the work of Matthias \u0027mazzoo\u0027 Wenzel this patch adds pretty\nprinting of those ICH/PCH flash descriptor sections that are\ncached/mapped by the chipset (and which are therefore reachable via\nFDOC/FDOD registers).\n\nthis includes the following:\n- content section:\n describes the image and some generic properties (number of\n sections, offset of sections, PCH/ICH and MCH/PROC strap\n offsets and lengths)\n- component section:\n identify the different SPI flash chips and their capabilities.\n- region section\n similarly to a partition table this describes the different regions.\n the content of FLREG* is derived from this section.\n- master section\n defines SPI master (host, ME, GbE) access rights of the\n individual regions. the content of PR* is derived from this section.\n\nthis is only a part of the data included in the descriptor. other\ninformation can be retrieved from a complete binary dump of the\ndescriptor region only.\n\nthis patch also adds macros and pretty printing for \"Vendor Specific\nComponent Capabilities\" registers: there are two of them: lower and\nupper. they describe the properties of the address space divided by\nFPBA (which allows to use multiple flash chips or partitions with\ndifferent properties). the properties of all supported flash chips\n(together with their RDIDs) are stored in the same format in table\nin a descriptor section (which is used by the ME apparently). a\nlater patch will use the macros outside of ichspi.c which is the\nreason why the prettyprinting function and the register bit macros\nare not defined in ichspi.c but ich_descriptors.h (else they would\nbe moved in the follow-up patch).\n\nbecause this patch relies on (compiler) implementation-specific\nlayouting of bit-fields, it checks for correct layout before taking\nany action on runtime.\n\nCorresponding to flashrom svn r1443.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "a63c7c449646147efe2bdeb80efeed479dc1d328", "tree": "da1a452c658ecb3120fffe6d084a46a85d5792a4", "parents": [ "082c8b559cd9f3262c9af58ac2f17f2cc8a09d8b" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 16 12:08:22 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 16 12:08:22 2011 +0000" }, "message": "Remove unneeded inclusions of chipdrivers.h\n\nThis is related to the spi split patch as discussed in:\nhttp://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364\nthe old commit (r914) log notes:\n\"Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c\n ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c\"\n\nthere still remain a few cases where chipdrivers.h is needed:\ndediprog.c (spi_read_chunked and spi_write_chunked)\nit87spi.c (due to spi_write_enable and spi_read_status_register)\nwbsio_spi.c (spi_programmer registration only)\n\nbesides that, there are also non-spi files that do not need it.\nalso, add flash.h to chipdrivers.h because it uses some types of it\nand remove flashchips.h from print.c\n\nCorresponding to flashrom svn r1414.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "8b391b8e278cf3ca0d86e6e255f9c802a6e93fca", "tree": "4418c7ce4f6c7aeb89ff099ff52dff13c24f6b65", "parents": [ "a9cbbacfd3effe26cfbcbc4a11225776f12fe582" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 09 01:49:34 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Tue Aug 09 01:49:34 2011 +0000" }, "message": "ichspi.c: refactor filling and reading the fdata/spid registers\n\n- add ich_fill_data to fill the chipset registers from an array\n- add ich_read_data to copy the data from the chipset register into an array\n- replace the existing code with calls to those functions\n- minor cosmetic changes\n\nCorresponding to flashrom svn r1409.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "91f4afa1108a35783e9d3d546fe8ea41dc87708f", "tree": "a94991ce77532b8767d5d3c6ac0e9ab58f4b9a2c", "parents": [ "1a227954f2c7d0a25d42bcea2ea0b901ceb0f464" ], "author": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Thu Jul 28 08:13:25 2011 +0000" }, "committer": { "name": "Uwe Hermann", "email": "uwe@hermann-uwe.de", "time": "Thu Jul 28 08:13:25 2011 +0000" }, "message": "Random whitespace and coding-style fixes\n\nAlso, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE\nwhere possible, wrap overly long line, etc.\n\nCompile-tested. There should be no functional changes.\n\nCorresponding to flashrom svn r1397.\n\nSigned-off-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" } ], "next": "1a227954f2c7d0a25d42bcea2ea0b901ceb0f464" }