)]}' { "log": [ { "commit": "47aa85c8fdf82b4e3b92dbcdfa3e4490c6782b69", "tree": "965bb18274b8fb44beb583b34a8a9098b4a87ad2", "parents": [ "84914db6304ccd0f6f41ba7b4f6c0a83ef66e5d0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 21 14:57:20 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "memory_bus: Turn flashbase into a par_master member `rom_base`\n\nGet rid of the global `flashbase`. Treat overrides for the `rom_base`\nsimilar to `max_rom_decode`: Gather the information in `internal_data`\nand then pass it to register_par_master().\n\nChange-Id: Ib9ed7234a849fe3550200fd602226d0036da15f0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/436\n" }, { "commit": "dfea68c563c4f23318e26897846fd2d79e27eefd", "tree": "e65d58355fbade12bc53832ed6893bc545256c76", "parents": [ "11136c210e382258a72df44ffe625260a6394a45" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 16:39:31 2026 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:28:06 2026 +0000" }, "message": "ichspi: Add Intel Wildcat Lake support\n\nLooks the same as Panther Lake except no 80 MHz options in the\nSPI guide nor the MFIT tool.\n\nChange-Id: I9d922687e5995ed34c9e8aee298554e976adfe0a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/403\n" }, { "commit": "f4d5f3294fd470830f2ec81d4bc803dccaeb9ae3", "tree": "a5408f9f92da87e86756af0b8951132dac22667b", "parents": [ "9c6b35f03ca30c60ee6d9d90b0a0309945e2714b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 08 18:42:55 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 10 15:56:47 2026 +0000" }, "message": "ichspi: Add Intel Panther Lake support\n\nPTL looks much like Lunar Lake. The only noticed differences so far are\na reserved frequency value that means 80MHz now, and that only 1.8V are\nsupported.\n\nTested `ich_descriptors_tool\u0027 output for the BIOS of an MSI Prestige 14\nFlip AI+ (D3MTG).\n\nDocuments used:\n * Intel® Core™ Ultra Processors (Series 3) Datasheet, Volume 1 of 2\n * Panther Lake H External Design Specification (EDS) Volume 2 of 2\n * Panther Lake-H Client Platform\n SPI Programming Guide\n\nChange-Id: Ifec90975cefc26bb7109d69fcdabcfe480516732\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/397\n" }, { "commit": "83d04387cfd38b2e286a7686c9373435665cea51", "tree": "80ba53deb613a54980f6bc73eb14c39f412238da", "parents": [ "96140c7c3e3d61445b996eba62f9ebb3a4a9c760" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 08 16:48:42 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 10 15:56:47 2026 +0000" }, "message": "chipset_enable: Add Arrow Lake H\n\nOther than the desktop Arrow Lake (S) and the high power mobile (HX)\nversions, Arrow Lake H doesn\u0027t use a discrete PCH but the SoC die\u0027s\nSPI controller. This makes it similar to Meteor Lake.\n\nChange-Id: I4aae1fb99eeb63de79abf336f7c76da42b555efe\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/395\n" }, { "commit": "a193983b9647f1364e30bba56a1eef72726ccbc0", "tree": "ffefc51cc344409cede664cc45ba79a7df03aad1", "parents": [ "1926900454166df3de18a1fa584e79dab8a48d75" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 07 21:58:02 2025 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 09 20:21:46 2026 +0000" }, "message": "amd: Fall back to reading rom3 range in case of ROM Armor\n\nAMD is pushing ROM Armor forward, which leaves the SPI handling to\nthe PSP and only a mailbox interface (guarded by SMM) for the main\nCPU. With the current ROM Armor 3, there is no opt-out in the BIOS\nsetup anymore.\n\nOnly access left for the main CPU is the read-only memory mapping.\nWe make this available when active ROM Armor is detected (SPI BAR\nregister reads all ff). Probing of the flash size is peculiar, we\ncan only try to guess it when memory contents look repetitive.\n\nTo not pollute the `amd_spi100` driver, we start a new one.\n\nStory: https://icon.sourcearcade.org/posts/amd_firmware_reading/\nChange-Id: Ib4866084fe80853fd66501176dbc6b766750062f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/350\n" }, { "commit": "c0124d13afa0b1399238b1ce94a3f20ea7ffbd91", "tree": "b171e11c317dff41aeb6a096c60016cef4428c33", "parents": [ "ee2401c7fa900c15f9c2801c46881c9413141ad1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 26 12:40:14 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 16 15:30:46 2026 +0000" }, "message": "chipset_enable: Suppress laptop warning for AMD SPI100\n\nChange-Id: I3f00e32cb182f7de366ff10725de50953e63a302\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/351\n" }, { "commit": "ee2401c7fa900c15f9c2801c46881c9413141ad1", "tree": "a55bd883e476fccb921a58b9b36e0904148d765d", "parents": [ "ffcf92fbfd04a3ac1a5d882bcd5c4b78255af495" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 09 15:48:07 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 16 15:30:29 2026 +0000" }, "message": "chipset_enable: Fix use-after-free of LPC PCI device\n\nWe ran pci_free_dev() too early, after some code moved around\nin enable_flash_amd_spi100(). Instead of trying to ensure that\nwe free the device handle on all paths, only use it early, and\nfree it right away.\n\nChange-Id: Ie71cdd2f98f67bc5016067404bb911f5629d0f03\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/352\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ffcf92fbfd04a3ac1a5d882bcd5c4b78255af495", "tree": "3ab6c036d9a0ab2f0f71c6c76fcb5d60bd3dd4de", "parents": [ "b6f4e73d4d76b61451869e2b0b353a1a5555c61e" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Apr 08 15:03:06 2025 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 17 20:58:48 2025 +0000" }, "message": "chipset_enable: Mark Raptor Lake-S as DEP\n\nAs usual, partial programming (BIOS region) is possible. Tested by\nrip_help on IRC.\n\nChange-Id: I259b9e7c6281120f6c5bea5ee468d7000930db8b\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/334\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "612519b2c54a008744891540407f2c8ff251083d", "tree": "f264bf5339ab332436dfd9acaa86d76b7492c1cf", "parents": [ "d5a61efe4e73675570eba7d537b4ec7e476946cb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 23:37:11 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Arrow Lake support\n\nARL looks much like a desktop version of Meteor Lake. Hardware registers\nseem to be the same, and the descriptor mostly differs in strap settings\n(as far as we are concerned).\n\nOdd enough, the old (pre 500 series) format for processor straps is used\nagain. For the descriptor detection, we shuffle the old default for Ibex\nPeak around, and make Arrow Lake the default for everything with over 80\nPCH traps.\n\nTested `ich_descriptors_tool\u0027 output for a GIGABYTE Z890M GAMING X BIOS.\n\nDocuments used:\n * Intel® Core™ Ultra 200S Series Processors Datasheet, Volumes 1 and 2\n * Arrow Lake-S and Arrow Lake-HX Client Platform\n SPI Programming Guide\n\nChange-Id: Ibaaeb896273eed3806561ba8c01d89770d27ff18\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/270\n" }, { "commit": "d5a61efe4e73675570eba7d537b4ec7e476946cb", "tree": "615c8bc476cf847c2d0bea4f7f1f154eede67e5a", "parents": [ "5e0d9b04a07f5646038020e1a45dd04c0b14e8f3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 23:55:44 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Lunar Lake support\n\nHardware looks much the same as Meteor Lake. The descriptor, however,\nknows 7 masters and regions are named a bit differently. Hence, add a\nnew enum entry for Lunar Lake.\n\nTested `ich_descriptors_tool\u0027 output for an MSI Prestige 13 A2VMG BIOS.\n\nDocuments used:\n * Intel® Core™ Ultra 200V Series Processors Datasheet, Volumes 1 and 2\n * Lunar Lake Client Platform\n SPI Programming Guide\n\nChange-Id: Ia377872cba56a3db6d853b7ce1bd495e5a03a868\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/271\n" }, { "commit": "5e0d9b04a07f5646038020e1a45dd04c0b14e8f3", "tree": "70386babe868ba7282cbbb0d8bc53880286025e8", "parents": [ "0ef2eb8f041ad6918dd41f4837d39be8811889c9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 21:44:52 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Meteor Lake SoC\n\nHardware looks the same as C740 series / Emmitsburg. The descriptor\nis somewhere between the latter and latest desktop platforms.\n\nOutput of `ich_descriptors_tool\u0027 with an image from Google/Rex looks\nreasonable.\n\nTested probing and reading on a Lenovo L16 ThinkPad.\n\nDocuments used:\n * Intel® Core™ Ultra Processor Datasheet, Volumes 1 and 2\n * Meteor Lake/Arrow Lake-U / H Client Platform\n SPI Programming Guide\n\nChange-Id: I7f1d162622a141fadcad715b064f92b1ccf7c72a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/189\n" }, { "commit": "0ef2eb8f041ad6918dd41f4837d39be8811889c9", "tree": "978d212a6cc5031e589162c49a36e4353e91c937", "parents": [ "42daab10a7704bfbe4a0af1a07748b8858649301" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 21:38:17 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Add Intel Snow Ridge SoC\n\nHardware looks the same as C740 series / Emmitsburg. The descriptor,\nhowever, has very different frequency settings and different regions\nand masters.\n\nThe output of `ich_descriptors_tool\u0027 tested with an image from Intel\nlooks reasonable.\n\nChange-Id: I9f9dc4414af63cbe48d22ef2955df28e297d7e4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/188\n" }, { "commit": "42daab10a7704bfbe4a0af1a07748b8858649301", "tree": "9a9aa5465db9f58aa9d0c55f9807a2f694a98e05", "parents": [ "af26008fbabdd780bc6966acca4ad2481520b304" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jul 16 00:27:27 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "ichspi: Properly add Emmitsburg PCH\n\nThe Emmitsburg or C740 series PCH is actually ahead of all the other,\ncurrently supported chipsets. Finally, Intel added new registers that\ncarry the read and write access permissions for all 16 regions.\n\nThe old FRAP register seems to be still around, so we print both new\nand old registers. For the detailed report we use the new registers,\nthough.\n\nWe also adapt the descriptor detection slightly: We check for `NM \u003d\u003d 6`\njust like we did for Lewisburg. This way we won\u0027t treat a huge range of\nISL (ICH/PCH strap length) values as Emmitsburg, which should result in\nless false positives.\n\nThe output of `ich_descriptors_tool\u0027 tested on some Supermicro firmware\nlooks reasonable. Also tested read/erase/write in `swseq\u0027 and `hwseq\u0027\nmodes with 7 series PCH, reading with ADL-P. All logs still report FRAP\nsettings correctly.\n\nChange-Id: Ibf5ebe2e2edfe5e5ae26bf1136648bf6354b0aa9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/187\n" }, { "commit": "8e4151ddb5b4533aa004594e5009ad92159b0651", "tree": "64a5d90d128a7e4997cf8e6c4af84e5c72a7498f", "parents": [ "6d72efaff26d50626008f7f52f710cf2e263b5c6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 25 13:01:23 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "chipset_enable: Remove hidden-spidev workaround for Elkhart Lake\n\nWe already use the ID of the SPI device here.\n\nChange-Id: I0edce3468399184f295d5be53893c7297a912e8f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/253\n" }, { "commit": "6d72efaff26d50626008f7f52f710cf2e263b5c6", "tree": "9feda016aaca2da0b89d55d4c2aab70dbca8f72b", "parents": [ "092a699d02a5003b323ed6df5a9e1b1241c4d620" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 25 13:01:23 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "chipset_enable: Remove hidden-spidev workaround for all 14nm PCHs\n\nWhen the 300 and 400 series PCH (Cannon Point, Comet Point) support\nwas added, we did not know if all firmware will be consistent in the\ndecision not to hide the SPI PCI devices. A few years later, we can\nconfirm that it is: Grepping[1] through the `linuxhw\u0027 database[2] re-\nveals that we actually gain some hardware support, when matching the\nSPI PCI device directly.\n\nH410 and B460 are actually 22nm \"PCH V\", so they keep the workaround.\n\nJasper Lake already used the PCI ID of the SPI device.\n\nTested read/erase/write on CM246 (Cannon Point).\n\n[1] diff -u \u003c(git grep -lE \u00271f.5.*8086:(9da4|02a4|34a4|a324|06a4)\u0027 \\\n | grep -v README) \\\n \u003c(git grep -lE \u00271f.0.*8086:(9d84|028[45]|a30[3-68-ac-e]|3482|068[457c-e]|0697)\u0027 \\\n | grep -v README)\n[2] https://github.com/linuxhw/LsPCI/\n\nChange-Id: I1b490207818d3a44c8037b6d4046eefe6ead7bda\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/252\n" }, { "commit": "092a699d02a5003b323ed6df5a9e1b1241c4d620", "tree": "b71c0d02ae41304cd22da77dd6c80da084a7cea7", "parents": [ "5bbd3241aa74908d916e42ce37ed94f1f0bce4f3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 25 12:45:18 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "chipset_enable: Remove hidden-spidev workaround for TGP+\n\nWhen the 500 series PCH (Tiger Point) support was added, we did\nnot know if all firmware will be consistent in the decision not\nto hide the SPI PCI devices. A few years later, we can confirm\nthat it is: Grepping[1] through the `linuxhw\u0027 database[2] shows\nthat we actually gain some hardware support, when matching the\nSPI PCI device directly.\n\nFor Alder Lake and Raptor Lake, we already used the PCI IDs of\nthe SPI device.\n\nTested read on Alder Lake P, read/erase/write on RM590E (Tiger\nPoint) which was previously not detected.\n\n[1] diff -u \u003c(git grep -lE \u00271f.5.*8086:(a0a4|43a4)\u0027 | grep -v README) \\\n \u003c(git grep -lE \u00271f.0.*8086:(a08[123678]|438[1-df])\u0027 | grep -v README)\n[2] https://github.com/linuxhw/LsPCI/\n\nChange-Id: I2474d94be53fe01f8bd01d924098fa28fd43d657\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/251\n" }, { "commit": "5bbd3241aa74908d916e42ce37ed94f1f0bce4f3", "tree": "2f06cb896db5c8b838e723319ae24b560c641251", "parents": [ "a08847581ff039e901644922c65efd07dba62cc1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 25 12:40:46 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "chipset_enable: Add missing PCI ID for Intel PCH H410\n\nThis is a Comet Point PCH V (22nm).\n\nChange-Id: I9b27163d63f7676391a9579d706caeee17979275\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/250\n" }, { "commit": "a08847581ff039e901644922c65efd07dba62cc1", "tree": "65fca18733796e382116eae9d3945a8c0a01cdf5", "parents": [ "5eb7a58c1bc34f64c43f98578ce5b9be21a3f152" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Aug 25 12:29:44 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 13:58:05 2024 +0000" }, "message": "chipset_enable: Factor PCH100 hidden-spidev workaround out\n\nIntel mandates that the SPI PCI device, usually 00:1f.5, is hidden\non all 22nm PCHs. This applies to the whole 100 and 200 series PCHs\nas well as some special 300 and 400 series PCHs, and the respective\nserver PCHs and small-core SoCs.\n\nTo cope with the hidden PCI device, we match the LPC PCI device and\nthen crudely assume that the SPI device exists too (only its vendor\nand device IDs are hidden). We don\u0027t need this workaround for newer\ngenerations where the PCI device isn\u0027t hidden anymore, hence split\nit out.\n\nTested read on Alder Lake P, read/erase/write on CM246 (Cannon Point).\n\nChange-Id: I77b5240b99015ecf56773f4a34436cfd3c83bdf6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/249\n" }, { "commit": "5a9d6ea76f7c1f06f60b9cbbda885add2fb0eaeb", "tree": "3d1a61cd5643bfbce077d48c74d2e66a0e82249e", "parents": [ "e149fbe31368a8502d31391346a679064014ac81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 16 13:47:49 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Nov 06 11:12:38 2024 +0000" }, "message": "chipset_enable: Fix memory leaks introduced with AMD SPI100\n\nThe libpci function pci_get_dev() allocates a device struct that\nneeds to be free\u0027d with pci_free_dev() manually.\n\nChange-Id: Ic14f0931beb660b05cfe3f6e6d43b649dce8fff4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/242\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "240531045697cde87ecddf731c15d7fa84d5628f", "tree": "5e467fea700ceeaea24b2241bd95bca67bf85630", "parents": [ "9897063f72c2290d312954d34e305f472101a73b" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Sep 10 17:13:05 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 03 18:03:32 2024 +0000" }, "message": "chipset_enable: Mark Intel QM87 as DEP\n\nThis one is used in the ThinkPad T440p and was tested with HEADS.\nAs usual, support depends on the chipset configuration and locks.\n\nChange-Id: Ife9475a9862804fdb5c3c166e2ba978aae962f48\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/258\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "56d236bda45dfe9069fd29773965aa269506e0a9", "tree": "8b8642038a81db8fe0eae273c7a6a59e571f6f5c", "parents": [ "3b9f152b4d53eef7f10f82cca6e808a223ac11e8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 13 15:51:37 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 16 22:02:16 2024 +0000" }, "message": "chipset_enable: Add some newer AMD code names\n\nThese were found in the `linuxhw\u0027 database[1] to\nuse the same id/revision.\n\n[1] https://github.com/linuxhw/LsPCI/\n\nChange-Id: I131cacc6712d11ecd96e6c7d1b802488f48cf246\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/171\n" }, { "commit": "3b9f152b4d53eef7f10f82cca6e808a223ac11e8", "tree": "4a99b0f7431ca0611607bb8b0331d7c0cc5f6360", "parents": [ "522160f57af9a3dd2054d6912d071b6210f61769" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 16:09:29 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 16 22:02:16 2024 +0000" }, "message": "chipset_enable: Probe AMD SPIBAR first and bail on ff\n\nTesting on a ThinkPad T14s Gen3 has shown that the LPC device\u0027s\nPCI config space can return all `ff\u0027 for everything from offset\n0x44 on. Reasons are unknown at this point, so it seems best to\ncheck for this and bail out.\n\nChange-Id: I92dcbdc2eb31652faaad1dba3ad6978de0c8024b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/200\n" }, { "commit": "140e22f260f7d96054207839bedf73aaae670d65", "tree": "5ebc8fb6d9d7f8c5eb5d175833ab434dce0bc88a", "parents": [ "869f0e77ad1203ae078163ddfd32b0b08bf3f135" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 23:18:53 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "chipset_enable: Make use of SPI_ENGINE_PCH100 marker\n\nTested with 7 series PCH and ADL-P, log output stays consistent.\n\nChange-Id: I5b0b4d4e5f5a383c5a54342472b29eb73e78754b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/179\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "a1f6476a65bda5262d46430724a3af4b49bcd9e7", "tree": "4c03ecc180e60864fcbf59952c01c58390921eed", "parents": [ "3f75d4476da015ae1ee033c1de1ad4dc08f66b0d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 14 20:23:28 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jul 28 15:02:49 2024 +0000" }, "message": "ichspi: Split ICH7 init out\n\nThe original, ICH7 init only shared about three lines with the newer,\never growing ICH9+ init. That\u0027s not worth an indentation level in an\nendlessly long function, so split it out.\n\nWe introduce a kind of \"breakpoint\" into the `ich_chipset\u0027 enum:\n\n SPI_ENGINE_ICH9\n\nThis marks all chipset entries below it as supporting this code path\nand should help to avoid long `case\u0027 lists.\n\nTested read/erase/write on ThinkPad T60 (ICH7).\n\nChange-Id: I41e46d12e02c1343e636b47b2378db86e76af95e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/173\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b", "tree": "bf0c3951886de60086d32ff6e1a850adad926da6", "parents": [ "929d2e1b17a448d3352dbecb6a620ee0c1e65a58" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 23:31:40 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n they advertise the whole default set (PAR, LPC, FWH), they only pro-\n vide a maximum decode size for one of them. The latter is probably\n wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n" }, { "commit": "929d2e1b17a448d3352dbecb6a620ee0c1e65a58", "tree": "dcbad4698ce5741a1080fc7ba89d4bd5c5804417", "parents": [ "7c717c36c533f56ddc7fbac2ff944870fa0249f8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 00:47:05 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "internal: Pass programmer context down into chipset enables\n\nChipset enables potentially need access to programmer data, e.g.\nto process parameters, register masters etc.\n\nChange-Id: Iad211ff97e92d1973f981156bfa3154d1ba71d45\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72528\n" }, { "commit": "d1b91532627cdfd1bfde530baa6975f8f5d63d88", "tree": "2c4178e9d2b7abfaa7810bb44fc508ccb00b74d3", "parents": [ "ddb6d926783d4f9cbee04c7392718ed8f89daa0e" ], "author": { "name": "Arthur Heymans", "email": "arthur@aheymans.xyz", "time": "Mon Mar 20 23:26:13 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Feb 23 20:52:40 2024 +0000" }, "message": "chipset_enable.c: Add Genoa to mendocino entry\n\nTESTED on AMD Onyx board.\n\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nChange-Id: Ib2c64026f89b57edf40b76893758b161145de265\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/73837\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "ad5b71994ef7cdf7ecacd967d27d13b487805607", "tree": "5fccb97c12eca8807c7403fe69b42a37bcb780ea", "parents": [ "c09fca49c925e62271632ac7bf6ad40fe53b5d98" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue May 16 11:13:17 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu May 18 13:54:53 2023 +0000" }, "message": "chipset_enable.c: Drop `_LARGEFILE64_SOURCE`\n\nThis file does not access any large files, so there\u0027s no need to define\nthis feature test macro.\n\nChange-Id: I866cfa2f996eeea5846e5d9189647ad7a4a4e3e4\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/75272\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "632131590aa13544515f84822f94eb8f54d78e38", "tree": "7ba2063d0a8136be60866dc40fa79f11b2415598", "parents": [ "7a480310de5f7ec35d2d2acc7b60ca1ff8296944" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Apr 24 12:00:58 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 02 14:28:17 2023 +0000" }, "message": "chipset_enable: Mark C236 as DEP\n\nAs reported working by Tomas on the ML:\nhttps://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/2YSYIYKBUL5K26ZR5XIBV2YCXSNRWTNT/\n\nChange-Id: I575956d7e121350530e5b3e4e21384c0ea338d8f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/74857\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "8c37eaa29e585ad5709dc306232cd21b2ab06b2c", "tree": "abcf1479206a3d7348ff98c5001de8bd16136297", "parents": [ "e0b92e0c8e88b19ed53c28ec71e3dd585f4b96dc" ], "author": { "name": "Christopher Lentocha", "email": "christopherericlentocha@gmail.com", "time": "Wed Jan 18 12:36:18 2023 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "Add missing Intel B460 flash chip id\n\nNote that while I can read the chip, on my Lenovo Legion T5 28IMB05,\ncannot write to the flash chip with any tools except upgrading with\nvendor tool, no downgrades are allowed, due to the fact of SMM, even if\nI did manage to flash the BIOS chip somehow, would still face bootguard\nsince this machine has bootguard. But if I read the chip, and verify my\nread bin file, it works fine, until changing the SMBIOS, which is in\nthe vendor BIOS update package.\n\nflashrom-stable:\nMarked as DEP as that is the convention for config-dependent chipsets.\n\nChange-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca\nSigned-off-by: Christopher Lentocha \u003cchristopherericlentocha@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/72056\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73486\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e0b92e0c8e88b19ed53c28ec71e3dd585f4b96dc", "tree": "41f402c9e215ab1731e58dc9451aa10190b436f0", "parents": [ "12d5eb9d2047cc15b7a4b1f46514e1151342dfa6" ], "author": { "name": "Jan Samek", "email": "jan.samek@siemens.com", "time": "Tue Dec 06 16:42:56 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "chipset_enable.c: add PCI ID for TGL-UP3\n\nAdd PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.\n\nChange-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407\nSigned-off-by: Jan Samek \u003cjan.samek@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "12d5eb9d2047cc15b7a4b1f46514e1151342dfa6", "tree": "9b1a6a63670e36607d08d33b4b20b9ce91a1012a", "parents": [ "d48318c92c88d35e9b90d61796d18df1266f2a82" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 00:11:10 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "chipset_enable: Add PCI ID for Raptor Lake S\n\nThe ID was found in [1].\n\n[1] Intel(r) 700 Series Chipset Family Platform Controller Hub\n Datasheet, Volume 1 of 2\n Doc. No.: 743835, Rev.: 002\n\nChange-Id: Iea4c6e856d2f153cef4906c7febbe895d958edae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73484\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d48318c92c88d35e9b90d61796d18df1266f2a82", "tree": "ada182ab55fe420fa36782479efbae6030c04dce", "parents": [ "c1fa3418ad546f1c6029174fa2f75c0e6b48e7a2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 14 23:37:18 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:59:16 2023 +0000" }, "message": "chipset_enable: Add missing Tiger Lake IDs\n\nIt is unclear if the SPI controller is never hidden on Tiger Lake,\nhence we keep stacking the IDs of the eSPI controller. Tiger Point H\nIDs are from [1], the UP3/4 IDs from [2].\n\n[1] Intel(r) 500 Series Chipset Family Platform Controller Hub\n Datasheet, Volume 1 of 2\n Doc. No.: 635218, Rev.: 008\n[2] `src/include/device/pci_ids.h` in coreboot\n\nChange-Id: I4e50df6d6511e0ecd1ead96c67247e433fbf271a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73483\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c1fa3418ad546f1c6029174fa2f75c0e6b48e7a2", "tree": "8d55916f42b24d8c68905ab901181594de33290a", "parents": [ "c152f53a12c11f9effe08671d9366d11a0a6587d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 23:56:12 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 14 23:48:20 2023 +0000" }, "message": "chipset_enable: Add a line break in debug output\n\nIf loglevel is \u003e\u003d debug, we should end all lines at\ninfo level with a line break.\n\nChange-Id: Ibf85869a9156facda58c5fb6a0a558d124ffd2b8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72586\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "96f964b419845e185ccd718d46dc38751fbc7967", "tree": "468e7139c3ad9d88758ab555b3f1b288d99a5b47", "parents": [ "4d51e07242459f86d00eaf522786695e46ec2511" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 23:47:51 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "chipset_enable: Mark AMD Pinnacle/Raven Ridge and Matisse as DEP\n\nTested Pinnacle Ridge and Raven Ridge on an ASRock A320M-HDV and\nMatisse on an ASRock A520M-HDV. Because there can be access pro-\ntections set up in the chipset, mark them as DEP.\n\nChange-Id: Id389786d2b2dcea0141322c94ac72e03161019db\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73157\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e3c305dfd234503faa23c5491962db8f52d0134c", "tree": "b86a019224a05586e18b98eae8ff0c9b51a1c701", "parents": [ "070587892b4af723bf8f1f423d0b26e12e061084" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 21:45:56 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Implement memory-mapped reads\n\nQuery the RomRange2 register for the memory range (usually top below 4G)\nand try to map that. Reads outside this range will still be served via\nthe command engine.\n\nChange-Id: I21aa67d550ccda0f55a9cf3ff14545a881624d11\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72583\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "735b186eeffb997a957075d7e610b9700b53cbe1", "tree": "1e27f0dc7f2cae492459530df208859221a1d3ca", "parents": [ "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 18:28:45 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 28 23:42:48 2023 +0000" }, "message": "amd_spi100: Add new driver for AMD SPI100 controllers\n\nStart with a very simple PIO driver. Reads are slow this way, but\nwe can optimize that later. A factor of 2 is possible simply by\naligning the FIFO reads, and another factor of 3 (at least) with\nmemory-mapped reads.\n\nWe override the SPI speed but choose a conservative value to be\non the safe side. Flashrom only supports normal read commands,\nhence we won\u0027t go over 33MHz. Also, if the firmware set a lower\nspeed for normal reads, we use that. We can\u0027t use dual/quad I/O\nwith the SPI command engine, and tests have shown that increasing\nthe SPI speed lifts the read speed only marginally. It seems to\nbe limited by the FIFO reads.\n\nChange-Id: I403d5f103b3ae72f3a91829d562984c54c2e2d00\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72577\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "78cd559d0eebeb2e725f19db89ab2f11aac05613", "tree": "6c7e68cca1b199aec9d6a9fce34da32171f12f8f", "parents": [ "e604d56cf5654db8b744cbe5fb4fdb5fbfecd4e8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 18:24:34 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Start new driver for AMD SPI100\n\nWe start with the known fam17h PCI devices. Handle what we can gather\nfrom the LPC device and then hand over to a to-be-written SPI driver.\n\nChange-Id: I8215d2bf30ac95ec2258f28267edfdb7af569bea\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72576\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e604d56cf5654db8b744cbe5fb4fdb5fbfecd4e8", "tree": "997104c21770b3a847d438004873691b39aea898", "parents": [ "019810f3fd083df5f6f61d19dda2d252709d02fe" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:34:57 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Split detection for AMD Merlin Falcon and Stoney\n\nSplit the chipset enable entries because future SoCs use the same\nPCI IDs. We use the SMBus device for this, just like `sb600spi`.\nHowever, as the latter expects the LPC device to be passed, we\nhave to look that up first.\n\nChange-Id: Iba02d8695d150f9be51c996932b845a487b0e4ce\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72574\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "019810f3fd083df5f6f61d19dda2d252709d02fe", "tree": "d9f2f1e6f8e10b6bb1d4b7f56f431f9073942fbc", "parents": [ "6d98aece44f6f3458c79160adf4dddc7f8500378" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 17:11:24 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Feb 21 22:52:42 2023 +0000" }, "message": "chipset_enable: Optionally check PCI revision field\n\nWe used to match compatible chipset devices by vendor and device ID\nonly. On some chipsets, e.g. AMD southbridges / SoCs, this is not\nenough, though, as the device IDs are rarely updated.\n\nIn the case of AMD chipsets, we can identify the chipset with the\nrevision ID of the SMBus device. So we add that field to the chipset\nenable list.\n\nChange-Id: I4021cf8e83c605fde4360c274b39481b1e0ff070\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72573\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f8d9a272845cd96cf5a33560fe0b4ad54a13bfc3", "tree": "b2cdc0459a6c7e99fcf925c05c309273e6b0e446", "parents": [ "5194d589bfc637fef26073252f312c853895eab9" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Wed Mar 16 09:19:19 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess_x86_msr: rename msr function to msr_xxx\n\nThis eliminates the need to redefine the rdmsr and wrmsr symbols,\nresulting in more understandable code. The common prefix clarify the\nrelation between the functions.\n\nChange-Id: Ie5ad54d198312578e0a1ee719eec67b37d2bf6a4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62851\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72318\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "19ce50d3746fb1d9e5238bac49cf88ffe654848e", "tree": "90852ac71da4bc563f5bda33dd2954cd990f1d4b", "parents": [ "6c73e27aa68e0e100f6573cd0910f6f54bff271d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Nov 13 17:59:18 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move pci_dev_find() from internal to canonical place\n\nAlso rename to `pcidev_find()` in fitting with pcidev.c helpers.\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: Ie21f87699481a84398ca4450b3f03548f0528191\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59280\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72310\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "48a946673fa770a9224c2b79a8f8440c51b109ed", "tree": "62f3bd1fee1f4e6cf45d42011d2dcbb435ca028e", "parents": [ "15004ba11d6c3b86c7824bb30a630c81e94cc9a4" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Sat Feb 26 11:36:17 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pcidev: Move scandev_inclass logic from internal to pcidev\n\nTested: ```sudo ./flashrom -p internal -r /tmp/bios\n\u003csnip\u003e\nFound Programmer flash chip \"Opaque flash chip\" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.\nReading flash... done.\n```\n\nChange-Id: I1978e178fb73485f1c5c7e732853522847267cee\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59277\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "df3672d08beb0d1946dccc702fc4df75b051cd22", "tree": "c4996a38aa040f3824f9360f698b89e3265cb369", "parents": [ "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77" ], "author": { "name": "Peter Marheine", "email": "pmarheine@chromium.org", "time": "Wed Jan 19 17:11:09 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: fix build on non-x86 targets\n\nThe changes to hwaccess in commit 49d758698a0d (hwaccess: move x86\nport I/O related code into own files) cause build failure on non-x86\nsystems because the hwaccess_x86_* headers are included in some files\nthat are built for all platforms (particularly those in the internal\nprogrammer) and those headers in turn include \u003csys/io.h\u003e which only\nexists on x86.\n\nThis change avoids including those headers on non-x86 platforms so\nthe internal programmer can be built without errors.\n\nThe comment on the stub implementation of rget_io_perms() is also\nmodified to remove references to non-x86 platforms, since that file is\nonly built on x86 now.\n\nTested: meson build succeeds for both x86 and ARM targets\n\nSigned-off-by: Peter Marheine \u003cpmarheine@chromium.org\u003e\nChange-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61194\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72279\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3f4d35daf4533650e75fcabb8f1ed9085e1fcf77", "tree": "ae3340f0a563d1d9ed48285cc861e7e90e2343ef", "parents": [ "a6b45c4516e15aeb405028e5095e86259fcd9e34" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Jan 17 15:11:43 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move mmio functions into hwaccess_physmap\n\nThe mmio_le/be_read/writex functions are used for raw memory access.\nBundle them with the physmap functions.\n\nChange-Id: I313062b078e89630c703038866ac93c651f0f49a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72278\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "74b4aa0b15439a2ab2474889a7abed978439757a", "tree": "a3e6d01052b04bbae7c71af7c1148d3619ba1ab1", "parents": [ "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:52:30 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "physmap: rename to hwaccess_physmap, create own header\n\nLine up physmap with the other hwaccess related code.\n\nChange-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72267\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b3287b43dc2fc90913686eb7ca9adfdedac2fdb4", "tree": "5432e2d6675b9f389ad95bf47f4e2e7decd5807f", "parents": [ "a065520a7c7eedcca961de1fc891cc0b04e6df77" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 17:25:49 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess physmap: move x86 msr related code into own files\n\nAllow x86 msr related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nflashrom-stable: Squashed fixup for FreeBSD\n\nChange-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60111\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72266\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a065520a7c7eedcca961de1fc891cc0b04e6df77", "tree": "f7a4c280f6d3114b98a52e147f988c4ae293271b", "parents": [ "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Dec 14 16:36:05 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "hwaccess: move x86 port I/O related code into own files\n\nAllow port I/O related code to be compiled independent from memory\nmapping functionality. This enables for a better selection of needed\nhardware access types.\n\nChange-Id: I372b4a409f036da766c42bc406b596bc41b0f75a\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60110\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72265\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d96c97c77309f1cf1ff1cbe9fa521a75fc9d5698", "tree": "2ca206a0bb2873472e243eb2138c7f1e0345abf2", "parents": [ "b7c6a66d5167a9cb6d83081f4c84b7a6c0d28046" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Nov 02 21:03:00 2021 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 29 12:29:02 2023 +0000" }, "message": "pci.h: move include into own wrapper\n\nSplit the include of hwaccess and libpci. There is no need to have pci.h\nincluded in hwaccess.\n\nChange-Id: Ibf00356f0ef5cc92e0ec99f8fe5cdda56f47b166\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58883\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72264\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ac90af6cdc747bfe3dc38c83c0b7272addf37659", "tree": "ec67fd7c4d01db82b5a1ffd8c8ed36a7229108dd", "parents": [ "bb4f3b06dcfb60a6ab84750c9b149482dc5ee579" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 18 00:22:47 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:34:15 2023 +0000" }, "message": "Change references to flashrom-stable\n\nAdapt all mentions of the mailing list and also the version print.\n\nChange-Id: Ib4a3271422ee6cf4d0efb8c3fa858b66a22c0a33\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70922\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0c8221bb4462d7410a4667ab3526502c5eaa241d", "tree": "f2264704cde0950882873089f8c8d16154c401a1", "parents": [ "e28d8e4e2332054fb4b7f61e8ce03f316e3a63f3" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Thu Oct 20 21:23:33 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "chipset_enable.c: Mark Intel C246 as DEP\n\nTested reading, writing and erasing the flash chip of a Prodrive\nHermes mainboard with an Intel C246 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I07d6c4a60e468c61eba836db91e1335f4a762048\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68594\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71493\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d1ab7d2bb0c4ea7be2e251caa564ab91d27ee7ea", "tree": "905816b92fb3759fcb82767cb94b49d6e0f02594", "parents": [ "8cfc7377ffa880659660b344e97333986aba9130" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 03:03:47 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `laptop_ok` with bool\n\nUse the bool type instead of an integer for the variable `laptop_ok`,\nsince this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I5d9fc3516bc2d29f11b056e35b3e5e324ce93423\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66891\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "980d6b8d712d26711dcd5a71007e4626c7198cd5", "tree": "38e926243e6a10734971066fd1602d373fd04784", "parents": [ "f25447e5724bd8664338b69b12399f101abed76b" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Fri Aug 19 02:48:15 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "tree: Retype variable `programmer_may_write` with bool\n\nUse the bool type instead of an integer for the variable\n`programmer_may_write`, since this represents its purpose much better.\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: I69958527ae018a92f1c42734a7990d0c532dee0c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71483\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "756b6b32e2a49c487d4bbc42d370e8826b41c922", "tree": "ce4db0712ab0fba0c5bed684ca67e012a2f2807d", "parents": [ "15095dbb7b9d7f1938d43e5ff3b99054b0798803" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 21 17:15:13 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Add Intel Jasper Lake support\n\nLoosely based on commit b01d7e9f (ichspi: Add Jasper Lake support)\non flashrom master.\n\nBesides a little change in descriptor detection, no difference to\nCannon Point was found. Hence, add new PCI IDs as 300 series.\n\nChange-Id: I9c715c1a5f1ceea32dc51669453d89b315ba8ca2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71453\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "29c23dd08474b2457ffd8a72ee3d8587676cd999", "tree": "73ccbc237df969f57ad5c9f7e044e0d4b9ca2656", "parents": [ "8efb0b337a46aaa5f2da902aa862d30e6a1305be" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Dec 21 15:25:09 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:35:01 2023 +0000" }, "message": "Add Alder Lake support\n\nLoosely based on commit 11680db4 (ichspi: Add Alder Lake support)\non flashrom master.\n\nBeside a little change in descriptor detection, no difference to\nTiger Lake was found. Hence, add new PCI IDs as 500 series.\n\nChange-Id: Icc1278755ff64f03128d8faadbca85a4ff76864d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71448\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e57d4e49fd2556f0fe267833d35cc57b7e252c06", "tree": "ef260430367f0d2025fd6c5c12c101f37639613e", "parents": [ "672bdcfd4ffeb065b7056042769e3cc512d87c06" ], "author": { "name": "Werner Zeh", "email": "werner.zeh@siemens.com", "time": "Mon Jan 03 09:44:29 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Elkhart Lake support\n\nElkhart Lake has a chipset called Mule Creek Canyon which is quite\ncompatible with 300 series chipsets. There are a few differences though,\ne.g. different encoding for the SPI clock values for read and write in\nthe FLCOMP register. In addition Elkhart Lake has a new PCI device ID\nfor the SPI controller which is added, too.\n\nTested: Read and flash complete flash on Siemens MC EHL1\n\nChange-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475\nSigned-off-by: Werner Zeh \u003cwerner.zeh@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fafc3d8048d9e26b708323805868d127eeecc12e", "tree": "dfe8d02595cde3456708d263a01033ba9754efac", "parents": [ "6ae640b1f33464969d401e00b44b3b5157f1ce09" ], "author": { "name": "Tim Crawford", "email": "tcrawford@system76.com", "time": "Wed Nov 17 06:23:25 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add TGP-H IDs\n\nAdd IDs for: H510, B560, H570, Q570, Z590, W580, HM570, QM570, WM590\n\nTested on system76/oryp8 (HM570). flashrom is able to read the image\nusing the internal programmer.\n\nChange-Id: I96f63253d42578151f99dcbb42347afecc03f49d\nSigned-off-by: Tim Crawford \u003ctcrawford@system76.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57533\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Benjamin Doron \u003cbenjamin.doron00@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71440\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "69c324a7d4015c3ca4ba8d39a1c42670369f5afb", "tree": "c24c0bbe9512d67ed1daa9f919beeea00672441e", "parents": [ "5c9f542bf8ce514c628c59e42e35fbcb615d8937" ], "author": { "name": "melvyn2", "email": "melvyn2@brcok.tk", "time": "Sat Oct 30 16:02:22 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Mark Intel Z390 as DEP\n\nTested read/write on GIGABYTE Z390 AORUS MASTER, incl. ME region with\nme_cleaner.\n\nChange-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nSigned-off-by: melvyn2 \u003cmelvyn2@brcok.tk\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58774\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71438\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937", "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744", "parents": [ "cce1e5b8636ebef59dd509680594e17b0a207857" ], "author": { "name": "Michał Żygowski", "email": "michal.zygowski@3mdeb.com", "time": "Wed Jun 16 15:13:54 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "eec477f1a6f4ba718e713438532c81d9a9b7db72", "tree": "ee51926458b3f9fcc18fc81a74f6fc3be2fc90a5", "parents": [ "a4e63e7957c5eb41d9e0dc237949102795494f31" ], "author": { "name": "Sophie van Soest", "email": "sophie@entropie.rocks", "time": "Sun Jul 04 13:54:26 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Mark Z97 as DEP\n\nTested on GIGABYTE GA-Z97-HD3.\n\nSigned-off-by: Sophie van Soest \u003csophie@entropie.rocks\u003e\nChange-Id: I73bdd9afefae8e7c013d400e17a15e56d84322f4\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/56060\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71421\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3bf7cfba9fca9b18d4ad5b843399bc00a3be1f49", "tree": "cc4c65492591a94835ad9a0c9617084ec8ab006e", "parents": [ "66565a7953b27a55cd963bb4f608c08f7d5237f0" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Mon Aug 30 23:25:06 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add support for Intel Emmitsburg PCH\n\nThis patch does the following:\n- Add PCIe ID for Intel Emmitsburg PCH\n- Based on ICH descriptor content, choose CHIPSET_C620_SERIES_LEWISBURG\n if ISL/PSL is 80.\n\nTested: tried on a server with Intel Emmitsburg PCH, flash update\nwas successful. This server, however, does not have flash chip\ninstalled, it instead has em100 emulator connected.\n\nChange-Id: I2a1bb7467e693d1583aa885fa0e277075edd4a3e\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nSigned-off-by: David Hendricks \u003cddaveh@amazon.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54965\nOriginal-Reviewed-by: Christian Walter \u003cchristian.walter@9elements.com\u003e\nOriginal-Reviewed-by: Johnny Lin \u003cJohnny_Lin@wiwynn.com\u003e\nOriginal-Reviewed-by: Tim Chu \u003cTim.Chu@quantatw.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71419\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1c7297fdbb34c6d211a31b4071c232d7e053289a", "tree": "141678ce4577d4743df0808f550b43329c7fd884", "parents": [ "4db0fdfdcb59f94e41c0967375c899e2d274e113" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon May 17 10:50:40 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add Gemini Lake eSPI PCI device ID\n\nTaken from coreboot `PCI_DEVICE_ID_INTEL_GLK_ESPI` macro, untested.\n\nChange-Id: Ie34527e56edcba4982f17b8e0aef0fc4280a52bc\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54354\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71355\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "4db0fdfdcb59f94e41c0967375c899e2d274e113", "tree": "5866347a6c5e63477f8e05cc32443085319c2df3", "parents": [ "771bb7952a91722d2d9f100e19b0566f06298126" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Jul 10 17:04:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "Add Gemini Lake support\n\nThe SPI hardware is pretty much unchanged from Apollo Lake. However, the\nIFD differs significantly enough to require special handling.\n\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nChange-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b499b67d1b112141792a71ad9119d51dd9052684", "tree": "e1477a95f0987cdaf6a4a9f1c774d7bbb7f9773b", "parents": [ "bc0285c9b3e6faa8538cb0d2a1d50c158a955919" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Thu Apr 22 17:08:00 2021 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add IDs for H310C and B365 PCHs\n\nThe device ID for H310C can be found in Intel document 335192-004, but\nthe device ID for B365 is not there. Other sites list these IDs:\n\nhttps://linux-hardware.org/index.php?id\u003dpci:8086-a2ca-1462-7c09 (H310C)\nhttps://linux-hardware.org/index.php?id\u003dpci:8086-a2cc-1849-a2cc (B365)\n\nBoth of these PCHs have been tested as well.\n\nChange-Id: If9f0a49a0f1821e5592213e07962ee48654cdc07\nOriginal-Tested-by: Timofey Komarov \u003chappycorsair@yandex.ru\u003e\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52605\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71349\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bc0285c9b3e6faa8538cb0d2a1d50c158a955919", "tree": "af7580298b29c029ef14f10b837388c16ee3c5a9", "parents": [ "d493baaa0c21c3b3f648b0349104978f4f589a33" ], "author": { "name": "Gaggery Tsai", "email": "gaggery.tsai@intel.com", "time": "Thu Dec 12 11:52:03 2019 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable.c: Add CMP-H IDs\n\nThis patch adds CMP-H support. They are HM470, WM490, QM480,\nW480, H470, Z490 and Q470.\n\nTested: build flashrom and run on CML-S with CMP-H\n flashrom -p internal -w ./coreboot.rom\n reboot and check the code is flashed correctly\n\nSigned-off-by: Gaggery Tsai \u003cgaggery.tsai@intel.com\u003e\nChange-Id: Ic7f04fc5cbe3422cbd219c46586c32fc847c921f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/37677\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Tim Crawford \u003ctcrawford@system76.com\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71348\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "d493baaa0c21c3b3f648b0349104978f4f589a33", "tree": "0ff6e28d593d487cc3b6da1265827b8d740c76fc", "parents": [ "0be623c3d88bef4c37d546e0970b0e8ac890be24" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.io", "time": "Sat Mar 06 21:14:39 2021 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:15:22 2023 +0000" }, "message": "chipset_enable: Mark QS67 as DEP\n\nTested on MacBook Air 4,2.\n\nChange-Id: Ia31c9d336d6ffe441323616174018b0f6a8897bd\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51320\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71347\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7630390672170718d6114f1439705d03765ac036", "tree": "266da495f6b51660caaa5110c45abe49d96a6715", "parents": [ "198bef39367088df36c88ecf93bd3b900a597735" ], "author": { "name": "Sam McNally", "email": "sammc@chromium.org", "time": "Thu Mar 11 11:41:46 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add PCI ID for Comet Lake U Base\n\nTested: `flashrom -r` on a kindred chromebook with a Celeron 5205U.\n\nChange-Id: I627dcacdad167343287ac0ec26b47505c2f823ee\nSigned-off-by: Sam McNally \u003csammc@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/51401\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71341\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "198bef39367088df36c88ecf93bd3b900a597735", "tree": "d4310f2f5618c92bd7dbada59a5015ed6a8d38f7", "parents": [ "9eeae3328682feadb663490eafaa26ee15cc0003" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Sat Feb 20 10:51:56 2021 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel C216 as DEP\n\nTested reading and writing internal flash on HP Z220 SFF.\n\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nChange-Id: I97538577c32e6c40374c414f005eb3165ed2e11d\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/50986\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71340\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "abb34fee66dc5255ac0ae770eb3d7f1c28f7b792", "tree": "af60db80459aba40d14cc08af031149c95ec598e", "parents": [ "2bb6792361f66a78473212d4dcddfe69d7b88aad" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Dec 06 23:09:13 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Intel H110 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\n280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71333\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "2bb6792361f66a78473212d4dcddfe69d7b88aad", "tree": "95924eefb318626978a4ee525f56ce2d123dfeac", "parents": [ "0a84d0d6950fef06ea0c0b0d220f9a97d2a958f0" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Tue Nov 03 17:19:52 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: mark \"Broadwell U Base\" as DEP\n\nTested probe/read/erase/write operations succeed with cros\nflashrom on rikku chromebox. Marking as DEP to follow\nconvention for ME-enabled chipsets.\n\nTested: Applied patch to cros flashrom and verified that\n`flashrom -VV` no longer prints a chipset warning on rikku\n\nChange-Id: I0b4d1dd2b271537faea15856442fe183d9de3318\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71332\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3b3fc9344d6cfd29007545826ecaf1e483b4bed4", "tree": "e249fbe857aee081ed4cdd2bf35feafac056673f", "parents": [ "55f6564524189f99097b3c6525b1b339a72cd063" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Fri Nov 20 10:05:29 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Intel Q67 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nElite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47797\nOriginal-Reviewed-by: Frans Hendriks \u003cfhendriks@eltan.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71330\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "55f6564524189f99097b3c6525b1b339a72cd063", "tree": "640e378ca1287a26f1a91ff4c0f088a84a7fa6bf", "parents": [ "0ad11992be40c7e1e9b8a1f45a48a3e5362f6f7c" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Mon Nov 02 14:43:10 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add Intel pch7 did\u003d0x1e4{1,2,3} support\n\nModified to be pch7 over pch6 as per-coreboot and review\ncomments.\n\nChange-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090\nOriginal-Reviewed-by: Sam McNally \u003csammc@google.com\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71329\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "4f29bb799b4672eebcc0bdfc6fb544b2b5544b6f", "tree": "8a27542cc468d103319c7c36afe894f57870f59a", "parents": [ "c753c40971c1481943e8a18dc24b33037e2a579d" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@gmail.com", "time": "Wed Aug 12 12:48:06 2020 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "Add support for Comet Lake-U/400-series PCH\n\nAdd enum CHIPSET_400_SERIES_COMET_POINT and treat it identically\nto CHIPSET_300_SERIES_CANNON_POINT.\n\nAdd PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT.\n\nTest: read/write unlocked CML-U board\n\nflashrom-stable:\nAs suggested above, treat it the same as 300 series. But don\u0027t add a\nnew enum.\n\nChange-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71325\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1592fe589725cccbc72db60fdb1858b6edb7432c", "tree": "caf214baffdfd692575632e27eec9c20b128f780", "parents": [ "c218a053aafbedc985ba448d9a1430116d38ad9b" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Aug 28 12:48:32 2020 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel Q77 as DEP\n\nTested reading and writing internal flash on Dell Optiplex 9010 SFF.\n\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nChange-Id: I4717959be1b79aa986f1276589d01ce7475bda8f\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44910\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71320\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "c218a053aafbedc985ba448d9a1430116d38ad9b", "tree": "ab4cc37bd2680e2c5c0337c1e580801ec7e009b0", "parents": [ "9f0641960c4b3a4d71d5876b12e9c1e354bec139" ], "author": { "name": "Jonathan Zhang", "email": "jonzhang@fb.com", "time": "Wed Aug 19 12:16:40 2020 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "add PCI IDs for additional c620 series PCH chips\n\nAdd PCI IDs for C621A, C627A and C629A.\n\nChange-Id: I636becd9f08bdf604c6af81ce396049655353b04\nSigned-off-by: Jonathan Zhang \u003cjonzhang@fb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71319\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "9f0641960c4b3a4d71d5876b12e9c1e354bec139", "tree": "8149dd59cba3645b9ea66faae3f2f1168f10f6b3", "parents": [ "5c639b32004925ae89ac6eb654344bad21cea9ef" ], "author": { "name": "Luka Kovacic", "email": "luka.kovacic@sartura.hr", "time": "Thu Jul 30 13:31:15 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller\n\nSupport for the Intel C620 Series Chipset SPI Controller (rev 04) is added\nto enable SPI flash access on the following platform:\n\n- Intel Xeon D-2187NT\n\nSupport for this controller was shortly tested on the platform above.\nThe flash is recognized, some regions of the flash are locked.\n\nSigned-off-by: Luka Kovacic \u003cluka.kovacic@sartura.hr\u003e\nOriginal-Tested-by: Jakov Petrina \u003cjakov.petrina@sartura.hr\u003e\nCc: Luka Perkov \u003cluka.perkov@sartura.hr\u003e\nChange-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71318\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "1f967c8acf61e2cc0d5e53c50bae11513a16755c", "tree": "3a38c1422300513fe68cbeafbd76603290abcd23", "parents": [ "7a6bce62a7b178c141a4dfc5e73b6b9ad80db84e" ], "author": { "name": "Jan Samek", "email": "jan.samek@siemens.com", "time": "Wed Jan 08 12:35:14 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: add PCI ID for APL-I (Broxton)\n\nChange-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324\nSigned-off-by: Jan Samek \u003cjan.samek@siemens.com\u003e\nSigned-off-by: Henning Schild \u003chenning.schild@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71315\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "abefc466e311de6b33eb0e0cf25fb72e558cc805", "tree": "620b775973797a6ec3312d9af47be0d509de3a81", "parents": [ "6d42d2ba8c718c5123286401bbcc61b0142aecef" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 29 15:23:59 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Spell `BIOS` in uppercase\n\nIntel document #336067 uses `BIOS Control` to refer to this register.\n\nChange-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: Marcello Sylvester Bauer \u003csylv@sylv.io\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71309\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "77a2a6e43576ab3c3b31263ec7464e30fa62b44d", "tree": "f4440424307f96043492269721d81ce396b19ef0", "parents": [ "a9335cc637c4d96ec37d8965628efbc0a7eb233a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Mon Mar 23 16:05:07 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Add more Lewisburg PCH IDs\n\nChange-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39780\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71304\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a9335cc637c4d96ec37d8965628efbc0a7eb233a", "tree": "0a5527d8e79de6d9c86848c87a88b3b5868b7853", "parents": [ "7113d17adc9f51400003bbdb4ed53e7b5d46b9dc" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Mon Mar 09 03:05:42 2020 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable: Mark Intel HM75 as DEP\n\nTested reading and writing on a Samsung laptop (see CB:39388).\n\nChange-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71303\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "7113d17adc9f51400003bbdb4ed53e7b5d46b9dc", "tree": "6e69cac79ec6a491aeef722d5536b604b98871a9", "parents": [ "de307c0d68ae46749a1dc392d983892b06f6a78a" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sat Feb 29 23:13:43 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 05 16:07:04 2023 +0000" }, "message": "chipset_enable.c: Mark Skylake U Premium as DEP\n\nTested reading, writing and erasing the internal flash chip using an\nAcer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173\nOriginal-Reviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nOriginal-Reviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71302\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@mailbox.org\u003e\n" }, { "commit": "2e3e10669d719545968ddec3b44b8a9363f4b432", "tree": "95f7807b9ec68fdc9d21590fc7c174ee0f391fca", "parents": [ "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Wed Dec 02 13:17:46 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:24 2022 +0000" }, "message": "chipset_enable.c: Validate physmap() return rcrb value\n\nValidate the physical mapping in enable_flash_silvermont().\n\nChange-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/48225\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67868\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "eaf701dc68e1b6a38542c3c856b0c9a2fb5a826d", "tree": "5541efefb64efc6611a315e12936608c37803c3c", "parents": [ "d92dd50bcac6b2d0dfffa9f983712f7400990f3d" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Thu Oct 15 19:19:05 2020 +1100" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:05:15 2022 +0000" }, "message": "chipset_enable.c: check return value from rphysmap() call\n\nPort from the ChromiumOS fork of flashrom.\n\nChange-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/46444\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Sam McNally \u003csammc@google.com\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67867\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "399a4dd721a64a1d22e2f8028cc39d6496515ed6", "tree": "6a40ff5ca048148294b209d8cb99ab9558fdc44f", "parents": [ "b57f48f77f367c43cd83878d92aa55de151c0798" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Apr 15 12:59:42 2020 +0200" }, "committer": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Sep 29 17:04:53 2022 +0000" }, "message": "chipset_enable.c: Disable SPI on ICH7 if booted from LPC\n\nCommit 92d6a86 (\"Refactor Intel Chipset Enables\") eliminated a check\nto disable SPI when ICH7 has booted from LPC, as the hardware does not\nsupport it. Therefore, when flashrom probes the SPI bus, it times out\nwaiting for the hardware to react, for each and every SPI flash chip.\nThis results in very long delays and countless instances of the error:\n\n Error: SCIP never cleared!\n\nTo prevent this, bring back part of the lost check. Probing for LPC and\nFWH when booted from SPI does not seem to cause any problems on desktop\nmainboards with ICH7, so don\u0027t disable LPC nor FWH if that is the case.\n\nTested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.\n\nChange-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40401\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67863\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n" }, { "commit": "b5433b782ff7cbde14ebd91aeac27efaec83e9d0", "tree": "facd5500f80682ce09fe7135362df5f4e7a87609", "parents": [ "3eae69531936cc41f227a532efea4cc3598d0f68" ], "author": { "name": "Johanna Schander", "email": "git@mimoja.de", "time": "Sun Dec 29 15:16:14 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Sun Feb 09 06:00:51 2020 +0000" }, "message": "chipset_enable.c: Add Ice Lake U to known and tested systems\n\nIntel Ice Lake systems use an 495 Series Chipset\nthat behaves compatible to pch300 chips but chip names\nare undocumented at this point.\n\nThis change was tested in read/write/erase on the Razer\nBlade Stealth (late 2019) with intel 1065G7 CPU and\n\"Ice Lake U Premium PCH\".\n\nChange-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15\nSigned-off-by: Johanna Schander \u003cgit@mimoja.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37987\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Christoph Pomaska \u003cgithub@slrie.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3799a1cc1adda28bb8bd4464020a7bbadd3960f1", "tree": "d654267ccdf97429733da5e0c07560be27a9d6f1", "parents": [ "e4c2b48f39902c7ff49a6a9e29525bdd3092c412" ], "author": { "name": "Wim Vervoorn", "email": "wvervoorn@eltan.com", "time": "Mon Jan 20 15:01:54 2020 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 22 14:15:33 2020 +0000" }, "message": "chipset_enable: Add Kaby Lake U Prem. to known and tested systems\n\nIntel Kaby Lake U (with the 9d4e device id) support is available but\nmarked not tested.\n\nTested reading, writing and erasing both internal flash chips on the\nFacebook Monolith system with the Intel i3 7100U SoC. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall follow\nsuit as well.\n\nSigned-off-by: Wim Vervoorn \u003cwvervoorn@eltan.com\u003e\nChange-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec\nReviewed-on: https://review.coreboot.org/c/flashrom/+/38481\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "728062f7ff7c2dca31bc99fe45eb5cacd7cf2d53", "tree": "8df82988b92b7b091358e72570671d908016a08a", "parents": [ "a9d6d1a817ce20e834fe7c354629976e3e5f1108" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Wed Dec 18 00:26:15 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 21 11:47:21 2019 +0000" }, "message": "chipset_enable.c: Mark Intel HM76 as DEP\n\nTested reading, writing and erasing the internal flash chip using a\nSamsung NP530U3C laptop with an Intel HM76 PCH. However, since all\nME-enabled chipsets are marked as DEP instead of OK, this one shall\nfollow suit as well.\n\nChange-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/37803\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\n" }, { "commit": "d58128eb83e59e09113666c80da81c891d76e949", "tree": "8ef79ded03a5d02eac66c0dde923a24fcd8408b2", "parents": [ "9e2dc2fc818cc9c1b46924e103ce669ad154b7ab" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun Oct 06 21:07:44 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 08 09:59:22 2019 +0000" }, "message": "chipset_enable.c: Mark Intel Q75 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\nPro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/35826\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ea0c093246fbaba9ab89348400ba4e99032aa4e0", "tree": "f5982cd4b2d3e207d064612083a286fcd5ad5cfc", "parents": [ "bde44a1989342859240c6993d1f782945bb4ce94" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 17:34:16 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:33:25 2019 +0000" }, "message": "chipset_enable: Mark Intel CM236 and CM246 as DEP\n\nThe usual ME-lock limitations apply, so this is DEP instead of OK.\n\nTested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also\nregression tested on Apollo Lake. Flashrom works fine, and logs and\ndescriptor dumps look good. Also, register and descriptor output\nagree on the flash layout and permissions.\n\nChange-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34073\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "bde44a1989342859240c6993d1f782945bb4ce94", "tree": "8887b05e3561727001e0dd6ad14ee1d040ff9ee3", "parents": [ "2a5dfaf140eb8f22c923a026df855da0c5e9bf82" ], "author": { "name": "Matt DeVillier", "email": "matt.devillier@puri.sm", "time": "Thu Jul 04 17:52:40 2019 -0500" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:46 2019 +0000" }, "message": "chipset_enable: Add support for Cannon Lake U Premium\n\nAdd support for Cannon Lake U Premium (CFL-U/WHL-U).\nSame as discrete 300-series CNP PCH.\n\nTested on a WHL-U laptop w/unlocked IFD.\n\nChange-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead\nSigned-off-by: Matt DeVillier \u003cmatt.devillier@puri.sm\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34076\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2a5dfaf140eb8f22c923a026df855da0c5e9bf82", "tree": "a1d231512e360758c35367d3b9b71e69f1ccbc57", "parents": [ "5ec84b3c096c9ace0bf3650206a0a9412e977c64" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Jul 04 16:01:51 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:37 2019 +0000" }, "message": "ichspi: Add support for discrete Cannon Lake PCHs\n\nOnly minor differences in the Firmware Descriptor, compared to their\npredecessors.\n\nWe extend our check on the `ICCRIBA` field in the descriptor to dis-\ntinguish it from older generation. Alas, the `freq_read` field was\nrepurposed, so we can\u0027t use it as sanity check any more.\n\nChange-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34072\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\n" }, { "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64", "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d", "parents": [ "045b97ebd97426b70706db7338a7fd76790b8781" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Tue Mar 19 17:00:03 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Aug 08 21:29:24 2019 +0000" }, "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n Chipset Family Platform Controller Hub\n Datasheet - Volume 1 of 2\n Revison 4 (Dec 2018)\n Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n Datasheet - Volume 2 of 2\n Revision 2? (Oct 2018)\n Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n" }, { "commit": "a508ca0acdc5cbd0ae8c2342d865d363ef24f185", "tree": "8fe50245d5bb3b8817427287510f199df1015e73", "parents": [ "519be66fc59558971dd653afe69ccaf1a633b492" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 24 19:34:43 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jul 31 08:27:57 2019 +0000" }, "message": "chipset_enable: Fix recent -Wmissing-field-initializer trouble\n\nChange-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34551\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\n" }, { "commit": "d2d3993a25c3236d397209f9c2118c3b17ce4f95", "tree": "8c91f0f2d588e66963c13e48dd972de555985bf4", "parents": [ "3750986348cb99b8f0d828b73972b545a2f9c878" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 16:49:37 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:23:53 2019 +0000" }, "message": "ichspi: Add Apollo Lake support\n\nIt\u0027s almost identical to 100 series PCHs and later. There are some\nadditional FREGs (12..15). To not clutter the `if` conditions further,\nmake more use of `switch` statements.\n\nTested on Kontron mAL10. Mark it as DEP as usually the last sector\nis not covered by the descriptor layout and can\u0027t be read.\n\nChange-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30995\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "3750986348cb99b8f0d828b73972b545a2f9c878", "tree": "62b7c2d2a5b84561596fdbbeddc6111d27dfc315", "parents": [ "908adf4589d34eaf3bd8395afa52aed8c8887cfd" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jan 18 14:23:02 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jul 06 17:15:58 2019 +0000" }, "message": "chipset_enable: Add Apollo Lake\n\nIt works the same as 100 series PCHs and on. The SPI device is at\n0:0d.2, though. Mark as BAD until `ichspi` is revised.\n\nChange-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/30994\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "2e50cdc494bf4e44c01e9e331b82a3633b1d9ef2", "tree": "78a7f9d9a0dd67f97d25e60c02a10e9785590fbf", "parents": [ "ba22411335f26601a76dbdf0d74a71e932b7cff8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 23 20:20:26 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 06 15:54:46 2019 +0000" }, "message": "Rework internal bus handling and laptop bail-out\n\nWe used to bail out on any unknown laptop. However, modern systems with\nSPI flashes don\u0027t suffer from the original problem. Even if a flash chip\nis shared with the EC, the latter has to expect the host to send regular\nJEDEC SPI commands any time.\n\nSo instead of bailing out, we limit the set of buses to probe. If we\nsuspect to be running on a laptop, we only allow probing of SPI and\nopaque programmers. The user can still use the existing force options\nto probe all buses.\n\nThis will obsolete some board-enables that could be moved to `print.c`\nin follow-up commits.\n\nChange-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28716\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\nReviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\n" }, { "commit": "17890b37f362e551e886506f39e7bf7181419457", "tree": "9278586896099d40869319f64cd3124e1c4f902a", "parents": [ "f9632d82634bbbdc7e90357d3ea7c4a631ab4376" ], "author": { "name": "Evgeny Zinoviev", "email": "me@ch1p.com", "time": "Sun Jun 02 23:07:52 2019 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jun 03 20:21:58 2019 +0000" }, "message": "chipset_enable: Mark Intel QS77 as DEP\n\nTested reading and writing with `-p internal` on MacBook Air 5,2 with\nIntel QS77.\n\nChange-Id: I508b6379507c2881c976d6baf7348b1161449cfe\nSigned-off-by: Evgeny Zinoviev \u003cme@ch1p.io\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33164\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "0cacb11c6252b6e1f4f0a2a33b47717ff22995d9", "tree": "062ee516f90ae51baf0f5c0f8ffe27c8c91bc4bb", "parents": [ "1cf369fb59546e705c5ca9368e629681c98b2893" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Feb 04 12:16:38 2019 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 04 15:46:25 2019 +0000" }, "message": "Remove trailing whitespace\n\nChange-Id: I1ff9418bcf150558ce7c97fafa3a68e5fa59f11e\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/31227\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cf4bug@amsat.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "099c8b2d5faae4d7f49c01c856f78398b743baa3", "tree": "738cd19feef5a59b0b4b8cfaf9beac3ed9145a67", "parents": [ "e7cbfae69e2bdf22018f14fbaf076a78995a2b60" ], "author": { "name": "Tristan Corrick", "email": "tristan@corrick.kiwi", "time": "Sat Dec 22 00:41:54 2018 +1300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Dec 22 13:07:34 2018 +0000" }, "message": "chipset_enable.c: Mark Intel C224 as DEP\n\nTested on a Supermicro X10SLM+-F. The flash chip has been read, written,\nand erased many times without issue. Most boards with this chipset will\nhave the ME region locked, hence the selection of DEP.\n\nChange-Id: I25126b94e691289a7b29dd81d5c864854a4e0245\nSigned-off-by: Tristan Corrick \u003ctristan@corrick.kiwi\u003e\nReviewed-on: https://review.coreboot.org/c/30361\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" } ], "next": "7fb508dc137818587bf142ec1f28fbc1c3a371fc" }