)]}' { "log": [ { "commit": "dae9022046be147c87c32d56678053b2f85cdb1a", "tree": "2b4551057e1e770283b71b180b29738a49215bc1", "parents": [ "2ae63016844097ae1046c861e88b4d8bfb0ff43e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 09 20:36:56 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "probing: Pass full struct flashchip into probes\n\nIn case we want to probe for a particular chip, we can filter the\nactual probing sequences by its properties.\n\nWe\u0027ll use `struct flashchip` internally and `struct flashprog_chip`\nwill be used only close to the libflashprog API. This way, we can\nseparate the two later again if necessary.\n\nChange-Id: Id8b13d28fcaefee62746c9391fe86b4b3b09a428\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/441\n" }, { "commit": "10337f785ebd621b544d7f5929bb1050eb975431", "tree": "2efbd04d3f00fa7a71a46cd68e61ee5a142a4d1c", "parents": [ "dd6e07ab3ab12346ab68f9e93f725d651a90964d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 04 19:57:27 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "memory_bus: Move related declarations into new `chipdrivers/memory_bus.h`\n\nChange-Id: I2bef65de77860d049ec3d9938ae777c5f929c258\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/438\n" }, { "commit": "64f53a1c9f5bd11b8b35cff757ac6d4aa37b0c59", "tree": "d64e96af9998a13ba3e22eb1cce5a65d434b7be2", "parents": [ "4312576b49dc77b53d5ebfa6686e3072c9368ea0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 15 16:04:29 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Use bus probing for REMS, RES and AT25F\n\nChange-Id: Ic5d2a5283c5fb5e52c58c0b5937922371f56249f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/417\n" }, { "commit": "4312576b49dc77b53d5ebfa6686e3072c9368ea0", "tree": "5802bfef2623095f5fdccd98df15bdabac35f785", "parents": [ "fbc41d2a932ede9c02aa7803472c31f39ec200f2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 15:56:16 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Use bus probing for RDID\n\nWe put 3 and 4 byte RDID into a single function. Only if we can\u0027t\nread 4 bytes, we try again with 3. There are no conflicts because\nthe only RDID4 manufacturer ID contains the 0x7f prefix, hence it\ncan\u0027t match any 3-byte ID.\n\nChange-Id: I5d35bc30255aae66da35d58431628512e50b39f0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74900\n" }, { "commit": "fbc41d2a932ede9c02aa7803472c31f39ec200f2", "tree": "8b72b78abfd99bf8737b90cc2fece11f2dbe93d3", "parents": [ "966dc9b776c2897d1245937639ab41fc834d7cb9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 22 23:04:01 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Move SPI related things into new chipdrivers/spi.h\n\nA few things that rely heavily on `flash.h` are moved there instead:\n* function signatures containing `erasefunc_t`,\n* the inline default_wrsr_target() that needs to know struct flashctx.\n\nThis allows to keep the new header file free of a transitive `flash.h`\ninclude.\n\nChange-Id: Ib215821feeb822ea3fc11bf9f48c0328f9a394d4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/416\n" }, { "commit": "11136c210e382258a72df44ffe625260a6394a45", "tree": "376f66e9e7a826dcf13f833e90291db7663205a4", "parents": [ "610c1aad71bfa118c4f49ac01761f586b8dede69" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 12:00:09 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "flashchips: Add a type enum to the chip identification\n\nWe used to imply what kind of ID (e.g. RES, REMS, RDID) a chip entry\nprovides, based on the given probing function. This works well as long\nas we call the respective probing function for every single chip entry.\nWith our ever growing chip database, however, this slows probing signi-\nficantly down. Especially with external programmers with a long command\nround-trip.\n\nWith the type of identification information stored in the chip entries\nexplicitly, we\u0027ll be able to implement bus-specific probing functions.\nThese would be called only once and their results would be used to look\na matching chip up in the chip database. Instead of looking for every\npossible chip on the buses, we can turn it around and search for the\nactually present chips in the database.\n\nChange-Id: Ie658ebf58f21c8994b9b66f7683f9490e8d12267\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74898\n" }, { "commit": "e3f648c3146be28c642782b11187011dfd6f258d", "tree": "272af33324401b45fc68bef0e1d697bf502998c1", "parents": [ "32f1ea8df501b41362058bb699a7ea96482e4db3" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 02:55:23 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 22:42:55 2026 +0000" }, "message": "spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected. This was originally the only read-\nprotection mechanism, introduced with ICH7. The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits. Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible. The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits. Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone, we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74896\n" }, { "commit": "648dfdc9272f02aaca0217fcdab542a10f45476e", "tree": "023250eb9cd99ffaa07ab8b19bf6ee5b2fd13038", "parents": [ "cfd607d36b8009eb41a7ca8e2a3e96eb9243d37b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 06 23:00:30 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Feb 24 14:18:46 2025 +0000" }, "message": "spi25: Fix cosmetic debug-print error due to unitialized buffer\n\nspi_prepare_address() expects `cmd_buf[0]` to be filled already,\nfor proper debug prints.\n\nChange-Id: I03b45be7e00d00d37b32553df0991a1b608aae35\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/322\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4e6155afd4b0e1f5cf190cdd21fa83a656c4088a", "tree": "395a5592506087f34ec696887eb965ec335f8b5d", "parents": [ "9512c9c16c73e46b6190c9c9fd9ea0555a4d7e24" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 02 23:05:09 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 17:23:14 2025 +0000" }, "message": "spi25: Add SPI25_EEPROM enum and handle \u003c 3-byte addresses\n\nChange-Id: I043f6ea987a07853b8c50e34b3cd63faf995ecbc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/314\n" }, { "commit": "1b1deda80bbd7f56b8047fad32badb749eeefffb", "tree": "e7058d9d175d08ed2542f6e34be0842a7ade8f57", "parents": [ "a1b7f3521f66a19a2d4c9a6a373c5a7ab36e1473" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Apr 18 00:35:48 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "Implement QPI support\n\nWith the quad-i/o support in place, this is actually straight-\nforward:\n* we check for compatibility of the flash chip and programmer,\n* select an appropriate fast-read function, and\n* always set the respective io-mode when passing a SPI command\n to the programmer.\n\nTested with FT4222H + W25Q128FV and linux_gpio_spi + MX25L25645G.\n\nChange-Id: I2287034f6818f24f892d66d1a505cb719838f75d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/165\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "a1b7f3521f66a19a2d4c9a6a373c5a7ab36e1473", "tree": "fd996296810ab45fe99d29d8dc254f6d496f3091", "parents": [ "008a44fa1c33b8a77c90b4e9dba267ae23c01056" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 25 18:32:11 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "dediprog: Implement multi-i/o reads\n\nThis implements i/o-mode switches and opcode handling for multi-i/o\nreads with protocol versions 2 and 3. The mode switching is done by\na simple command that takes an enum just as our internal `io_mode`\nas argument.\n\nThe opcode handling differs between protocol versions. For protocol\nv2, we keep the current behavior for single-i/o operations and only\nset the matching opcode. Tests with an SF600Plus-G2 have shown that\nthe programmer automatically chooses the address length and number\nof dummy cycles. It is unknown, however, if it chooses these para-\nmeters based on the opcode or the configured i/o mode. For dual-out\nreads, it seems to choose the wrong number of dummy cycles. Hence,\nwe mask the respective support bit for the v2 case.\n\nFor protocol v3, a new `read mode\u0027 was discovered in traces of the\nDediprog Windows application. It allows to explicitly specify the\nopcode, the address length, and the number of dummy cycles. We call\nthis READ_MODE_CONFIGURABLE. As this is the only way to make use of\nthe additional command bytes of the v3 protocol, we can assume that\nthis mode always works with v3.\n\nFor partial reads, i.e. not multiples of 512B blocks, that have to\ngo through dediprog_spi_send_command(), we temporarily disable the\nchosen `.spi_fast_read` function. This is necessary, because multi-\nio is not supported on this path.\n\nWe enable dual i/o by default for protocol v3 devices. This should\nwork out of the box with many compatible flash chips. The command-\nline logic is a little convoluted this way, but can be refactored\nonce protocol v2 devices are tested.\n\nChange-Id: Ib07b1b61eccc19c7ead9f64c980b37feabfa70a8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/114\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4760b6ec1f7fbcee1bf238a25e3df56a86327a5a", "tree": "a4c3762b1228f901f62d40b53ed1a953b25926b4", "parents": [ "0c9af0a639bf9180839d548f91547b58de921ca9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 23:45:28 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Implement multi-i/o reads\n\nWe describe a read operation in a new `struct spi_read_op`. It\u0027s\ncomprised of the i/o mode, its opcode, an optional mode byte, and\nthe number of dummy bytes.\n\nBased on this information about the various read operations, and\nthe flash and master feature flags, we select the read operation\nwith the highest throughput.\n\nThe following assumption is made about 4BA chips: When it supports\nnative-4BA fast reads and a multi-i/o version of the regular fast\nread, then it should also support the respective native-4BA, multi-\ni/o version (yes, JEDEC, there are too many read commands!). So far\nthis seems to hold for the chips in our database.\n\nChange-Id: I3c93e71d85f769831d637c14d3571f7ddb54d8b2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/49\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "8d0f4650c73eb7bcda0b71e514c0effdf37d90b5", "tree": "f27db276221972c6451278fa41806260ebfa7046", "parents": [ "044c9dc9290565ab7b9866bb26a8d077d9c3a5d7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 04 18:52:51 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Extract 4BA preparations into new `spi25_prepare.c`\n\nWe will have more preparation steps for fast-read operations and\nQPI in the future. Better start a new file, as `spi25.c` already\nis rather long.\n\nChange-Id: I253b270ce6796fb09e6d74903bd65a6fbc06c7d6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/162\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d518563f197241cc72f5da4b2108b2df10f00372", "tree": "8ec807be43adf3b5c9f66a2701b7bf0ea3a4a11f", "parents": [ "bd72a470b9b58386b52ca4568313be71b4d2c472" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 05 18:44:41 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Prepare for multi i/o and dummy bytes\n\nMulti-i/o commands split SPI transactions into multiple phases that\ncan be transferred over 1, 2 or 4 wires. For this, we adapt `struct\nspi_command` with a new enum, specifying the transfer mode, and ad-\nditional size fields. While we are at it, move everything related\ninto a new header file `spi_command.h` so we won\u0027t further clutter\n`flash.h`.\n\nOn the master side, we add respective feature flags for the multi-\ni/o modes.\n\nSee also the comment in `spi_command.h` about multi-i/o commands.\n\nChange-Id: I79debb845f1c8fec77e0556853ffb01735e73ab8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/44\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "7679b5ccf987e4999fefed6c6100a7a8f50d4350", "tree": "d904cf0a8e68feb831380054ce5956cb3b96fdca", "parents": [ "ca1c7fdd6bd6f61029492fb7a194bd47119e465f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 28 21:48:53 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "spi25: Replace spi_read_chunked() with more abstract version\n\nThe new flashprog_read_chunked() takes a low-level reading function as\nargument. This allows us to make use of the chunking with non-SPI read\nfunctions.\n\nChange-Id: Ica1b616e75e4e7682120928588e231c82cf4cf70\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74865\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "ca1c7fdd6bd6f61029492fb7a194bd47119e465f", "tree": "6e0063b18b7b8e9b3b1ddc4da95620213331efb6", "parents": [ "e36e3dc90f81fc2a718e4b367eebff900af21126" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 28 21:44:41 2023 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "spi25: Normalize parameters of spi_nbyte_read()\n\nMost other reading functions have the destination buffer\nas second parameter.\n\nChange-Id: Id3f91f3d23132b0706b3b33bbf156356c9bf5ebc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74864\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "842d678f07439e133e69fc775a848dcd66369446", "tree": "c01716fbc4220c1211749772d6a566e6d70701d7", "parents": [ "aa714dd3dd7090e1fa7175f3a32a252b04817261" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Fri Jan 15 09:48:12 2021 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 08:32:15 2024 +0000" }, "message": "libflashrom: Return progress state to the library user\n\nProjects using libflashrom like fwupd expect the user to wait for the\noperation to complete. To avoid the user thinking the process has\n\"hung\" or \"got stuck\" report back the progress complete of the erase,\nwrite and read operations.\n\nAdd a new --progress flag to the CLI to report progress of operations.\n\nInclude a test for the dummy spi25 device.\n\nTested: ./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus\u003d7 -r /dev/null --progress\n\nflashrom-stable:\n* Closer to original libflashrom API.\n* Split update_progress() into progress_start/_set/_add/_finish:\n Simplifies progress calls scattered through the code base. We let\n the core code in `flashprog.c` handle the total progress. Only API\n is flashprog_progress_add(). Erase progress is completely handled\n in `flashprog.c`. Fine grained read/write progress can be reported\n at the chip/programmer level.\n* Add calls to all chip read/write paths and opaque programmers\n except for read_memmapped() (which is handled in follow ups).\n* At least one wrinkle left: Erasing unaligned regions will slightly\n overshoot total progress.\n\nChange-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nSigned-off-by: Daniel Campello \u003ccampello@chromium.org\u003e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74731\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "ab6b18f0e0d4f4b2b8348306576b701b63372bd2", "tree": "f9adeb7ab53e6fed6d940f852979b5da86dd7de1", "parents": [ "901fb957742edef9307948c397bdd28c8b5ebfac" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 23:38:20 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "spi25: Move 4BA preparations into spi_prepare_4ba() hook\n\nThese preparations are specific to 4BA SPI chips and don\u0027t have to\nclutter `flashprog.c`.\n\nChange-Id: I842244c57e575f93b9c505e16f1f20c7afd23733\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72517\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "3561451faed250ced4a55e15d1abe5e3d94abfc4", "tree": "dd5c68bd13dee2adfb609540c64bac463848b941", "parents": [ "e2ff4e90125680a48623a2a908bff38d5b91e44e" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Sep 19 23:46:58 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcode\n\nThis function works only with spi25 chips\n\nChange-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67716\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72541\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "e2ff4e90125680a48623a2a908bff38d5b91e44e", "tree": "20d7cec6607c5ffd1d64d57a88148275d02a715f", "parents": [ "0cea753aff33b78051febadf8786df83144b5ee7" ], "author": { "name": "Thomas Heijligen", "email": "thomas.heijligen@secunet.com", "time": "Mon Sep 19 23:31:08 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi25.c: Move spi_get_opcode_from_erasefn() to spi.c\n\nSplit spi_get_opcode_from_erasefn() out into spi.c to add support for\nnon spi25 flashes next.\n\nChange-Id: Id654e998d0af2d3f5845336bb98b38d724519038\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67715\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72540\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ab9f25893f1fa87cbbaf656869e346391eccdb31", "tree": "f21fc6e6e4541cd6905a17bcf3ace937a6e9b5ac", "parents": [ "b725c0cd0e1c3fb56807c197b965620ac37b996b" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Thu Jun 23 16:21:23 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi25.c: Add function to return opcode of passed erase fucntion pointer\n\nThere is a function, spi_get_erasefn_from_opcode, which returns the\nerase function for given opcode. Add a function which does the opposite\ni.e. returns the opcode for given erase function.\n\nChange-Id: Ia3aefc9b9465efdd16b1678bb2ada9a23f00d316\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65355\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72538\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b725c0cd0e1c3fb56807c197b965620ac37b996b", "tree": "c3a2dee921479ffe469f95717254eda0c864c592", "parents": [ "a7cb7e959e4510820f452d6d8da2df3b4bd4ba02" ], "author": { "name": "Aarya Chaumal", "email": "aarya.chaumal@gmail.com", "time": "Thu Jun 23 16:12:12 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 19 13:50:18 2023 +0000" }, "message": "spi25.c: Add a list to lookup erasefn and opcode instead of switch case\n\nAdd a list (erasefn, opcode) which maps opcodes to erase functions.\nModify the spi_get_opcode_from_erasefn to use this list.\n\nChange-Id: I126f88c313ad309b509b367f9087235b87df6136\nSigned-off-by: Aarya Chaumal \u003caarya.chaumal@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65351\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Simon Buhrow\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72537\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "30aba3419cde195bd2039920077cb433b768d1d0", "tree": "0fbe83b8aaae5da049d4a728b63d49cf8c897a72", "parents": [ "518674c20d8dab1d6b877535b8b154079243fd32" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Oct 16 12:15:08 2020 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jan 22 00:55:18 2023 +0000" }, "message": "spi25.c: Replace tab with space after \u0027\u003d\u0027 symbol\n\nTrivial, only noticed while diff\u0027ing with ChromiumOS fork.\n\nChange-Id: I247d9cb1910a9afdb0e7bfe81515d51514da6550\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/46481\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72162\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c92f6876ed82488365c3ef1c59dd4669eb512527", "tree": "b1926b71b105e94f826c646e13d85d84a295e4e5", "parents": [ "a60f641a7f8b1a4cd602eecb8ddc247e40777400" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Mar 31 15:32:10 2020 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:34:15 2023 +0000" }, "message": "spi25.c: Add a null check\n\nChange-Id: I5fcc23d81b8404af90768afa2954509bf334ab2c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/39974\nOriginal-Reviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71734\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "ac90af6cdc747bfe3dc38c83c0b7272addf37659", "tree": "ec67fd7c4d01db82b5a1ffd8c8ed36a7229108dd", "parents": [ "bb4f3b06dcfb60a6ab84750c9b149482dc5ee579" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Dec 18 00:22:47 2022 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 01:34:15 2023 +0000" }, "message": "Change references to flashrom-stable\n\nAdapt all mentions of the mailing list and also the version print.\n\nChange-Id: Ib4a3271422ee6cf4d0efb8c3fa858b66a22c0a33\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70922\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d", "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35", "parents": [ "542b1f04869e7ac42b84800675f08f617ddf3f2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:07:34 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n instructions (and some programmers may be picky about which\n instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "542b1f04869e7ac42b84800675f08f617ddf3f2d", "tree": "9516bc3f06c3fc5d67203328e524b967b5d36901", "parents": [ "a8258d76aa2fb7c5f2e2085a0d1bab6804bf7a7c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 14:30:12 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Rename FEATURE_4BA_EXT_ADDR -\u003e _EAR_C5C8\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\nTo prepare for other instructions than the default 0xc5/0xc8, rename\nthe original feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70992\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "fffc48d247cef5102113d97538054066546b2297", "tree": "cdb49567c3d7c2291fa33221989516afb1b03abf", "parents": [ "3f3c1f3238dcede30d0d15d36da6326b428b8b12" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 28 14:26:06 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:51 2022 +0100" }, "message": "flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L\n\nThese chips seem to be rather regular, supporting 2.7V..3.6V, the\ncommon erase block sizes 4KiB, 32KiB, 64KiB and the usual block-\nprotection bits.\n\nStatus/configuration register naming differs from other vendors,\nthough. These chips have 2 status registers plus 3 configuration\nregisters. Configuration registers 1 \u0026 2 match status registers\n2 \u0026 3 of what we are used from other vendors. Read opcodes match\ntoo, however writes are always done through the WRSR instruction\nwhich can write up to 4 bytes (SR1, CR1, CR2, CR3).\n\nS25FL256L supports native 4BA commands and entering a 4BA mode.\nHowever, it uses an unusual opcode (0x53) for the 32KiB 4BA block\nerase.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I356df6649f29e50879a4da4183f1164a81cb0a09\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "b8a90d0a8c4b9b1a037f763e8792ae4c5363b4fb", "tree": "85191d34786a8297b7618919e50b64095fa2cee0", "parents": [ "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Thu Oct 28 16:18:28 2021 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:47 2022 +0100" }, "message": "spi25_statusreg: delete spi_read_status_register()\n\nDelete the spi_read_status_register() function because the generic\nspi_read_register() function can be used instead.\n\nThis patch also converts all call sites over to spi_read_register().\nA side effect is that error codes are now properly propagated and\nchecked.\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n Read SR1/SR2 with --wp-status and activated various WP ranges\n that toggled bits in both SR1 and SR2.\n\nChange-Id: I146b4b5439872e66c5d33e156451a729d248c7da\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70975\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "5800f5841de2fd74bfc6590978bd034a6c9e6102", "tree": "929fbfc5ca19a359b7bf1743ac138e1cac63e34d", "parents": [ "3384fb6ddae9583c2e201fc9c8a819e9df530369" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Thu Jul 18 14:30:47 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jul 19 16:17:58 2019 +0000" }, "message": "spi25: Remove dead increment\n\nValue stored in \u0027pos\u0027 is never read.\n\nFound-by: scan-build 7.0.1-8\nChange-Id: I9a70593f182d7558e71e831fc2b834ac58a25b2a\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34404\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "959aafa53eeae4f22766b9d098e5ca952af8c070", "tree": "12b2cf5512e0331370f75645a73372750f273d46", "parents": [ "afc3ad64300bbcc14266e645beec897ef06df13d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:13:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jun 27 10:24:47 2019 +0000" }, "message": "spi25: Fix layering violation in probe_spi_rdid4()\n\nMove the message to a lower level where we can do a more generic check\nand don\u0027t need internal knowledge of the SPI-master driver.\n\nChange-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33650\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n" }, { "commit": "beeb8bc925bef6973e1c9fa6c4fd26a4113a1777", "tree": "30c63cf4ae4bb14a19849b1680622ad6eed86d63", "parents": [ "cb44eb7dad17522f47792dca4fc499310ff7d6f3" ], "author": { "name": "Jacob Garber", "email": "jgarber1@ualberta.ca", "time": "Fri Jun 21 15:24:17 2019 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 23 21:39:31 2019 +0000" }, "message": "tree: Make internal functions static\n\nNone of these functions are used outside of the files they are defined\nin, so make them all static.\n\nChange-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1\nSigned-off-by: Jacob Garber \u003cjgarber1@ualberta.ca\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33667\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "504215b9f68e26938eea75afcbc22bdf389af991", "tree": "85f3be7cd8fb2512a2eca63eb2ac3f3cf2456ce9", "parents": [ "477e1693c830d3246c4fd7caae8a2f2b8e9f49c1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Apr 22 00:13:15 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 12:00:34 2019 +0000" }, "message": "spi25: Fix layering violation in default_spi_write_aai()\n\nChange-Id: I8aa3e2992f64906edc669060936f9522d32637fb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33649\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d8b2e808cd46986f945ba9cf3b90c70fe58de9c6", "tree": "4094be4996c4ae32a78e0e13c558ee78bcdd85dc", "parents": [ "0373ce31fe5b11dcf23b27fbc221ba019a1cf7f1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jun 18 23:39:56 2019 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jun 21 11:54:19 2019 +0000" }, "message": "spi: Move 16MiB partitioning up into spi_chip_read()\n\nWe enforced a 16MiB limit in spi_read_chunked() for multi-die flash\nchips that can\u0027t be fully read at once. The same limit can be useful\nfor dediprog programmers. So move it into a more generic place.\n\nChange-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/33613\nReviewed-by: Ryan O\u0027Leary\nReviewed-by: ron minnich \u003crminnich@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "7eb38aa7dbd45cbc040ac513ed4375995246aa93", "tree": "0b96573c7ec755ca09aa8799501e307284f337e6", "parents": [ "17890b37f362e551e886506f39e7bf7181419457" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Thu Mar 21 15:42:54 2019 +0100" }, "committer": { "name": "David Hendricks", "email": "david.hendricks@gmail.com", "time": "Tue Jun 04 13:54:54 2019 +0000" }, "message": "dediprog: Implement 4BA EAR mode for protocol v1\n\nWith an SF100 and protocol version 1, using the extended address\nregister of the flash chip seems safe. Make use of that and remove\nthe broken 4BA modes flag.\n\nTested with SF100 V:5.1.9 and W25Q256FV.\n\nChange-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/32016\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "df4905822754ac1f303f7939f5b77b35e5ac4a67", "tree": "547a0248de382233cecfc018a25996ffc0195b2d", "parents": [ "93e1625f9fb5f1080c40685488d006b2982062d7" ], "author": { "name": "Richard Hughes", "email": "richard@hughsie.com", "time": "Wed Dec 19 11:57:15 2018 +0000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 03 18:44:16 2019 +0000" }, "message": "Fix several -Wno-missing-field-initializers warnings\n\nChange-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7\nSigned-off-by: Richard Hughes \u003crichard@hughsie.com\u003e\nReviewed-on: https://review.coreboot.org/c/30405\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "86bddb5d52659f23531282db137350cbf7fb5992", "tree": "2f2b2da3f475065c9e86218b79ded18547c6b2c3", "parents": [ "57dbd64b33143964bb8eb91d33d72a2147f0091c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:14:52 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:14:57 2018 +0000" }, "message": "Enable 4BA mode for Spansion 25FL256S\n\n4BA mode is entered by setting bit 7 for the extended address register.\n\nChange-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25133\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "57dbd64b33143964bb8eb91d33d72a2147f0091c", "tree": "1606d103406bf36144602971ca2ac970d3a61482", "parents": [ "3eb5a8c82c00769bffc95c2c6c479de6d20dbd09" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Mar 13 18:01:05 2018 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Oct 03 13:10:17 2018 +0000" }, "message": "flashchips: Add Spansion 25FL256S......0\n\nThe Spansion 25SFL256S supports 4BA through an extended address register,\na 4BA mode set by bit 7 of that register, or native 4BA instructions.\nEnable the former only for now.\n\nUnfortunately the S25SF256S uses another instruction to write the exten-\nded address register. So we add an override for the instruction byte.\n\nChange-Id: I0a95a81dfe86434f049215ebd8477392391b9efc\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Michael Fuckner \u003cmichael@fuckner.net\u003e\nReviewed-on: https://review.coreboot.org/25132\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "e083880279119677e443fc16b4694f8c81bf2c40", "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5", "parents": [ "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b" ], "author": { "name": "Elyes HAOUAS", "email": "ehaouas@noos.fr", "time": "Mon Apr 02 11:14:02 2018 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Apr 24 20:21:41 2018 +0000" }, "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "fe34d2af28bd81aaa1e23ba38febaa98ec4bb90c", "tree": "53bda4d3445a94505455ffb12a96da602ba97af6", "parents": [ "1cf407b4f8d56035816efaf936a40553441eca46" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 21:10:20 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:15:30 2018 +0000" }, "message": "spi25: Revise decision when to enter/exit 4BA mode\n\nInstead of arbitrarily deciding whether to enter 4BA mode in the flash\nchip\u0027s declaration, advertise that entering 4BA mode is supported and\nonly enter it if the SPI master supports 4-byte addresses. If not, exit\n4BA mode (the chip might be in 4BA mode after reset). If we can\u0027t assure\nthe state of 4BA mode, we bail out to simplify the code (we\u0027d have to\nensure that we don\u0027t run any instructions that can usually be switched\nto 4BA mode otherwise).\n\nTwo new feature flags are introduced:\n\n* FEATURE_4BA_ENTER:\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.\n* FEATURE_4BA_ENTER_WREN\n Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.\n\nFEATURE_4BA_SUPPORT is dropped, it\u0027s completely implicit now.\n\nAlso, draw the with/without WREN distinction into the enter/exit\nfunctions to reduce code redundancy.\n\nChange-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22422\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "1cf407b4f8d56035816efaf936a40553441eca46", "tree": "c8e41e1172aaeb567af161a9763521c53073bdc4", "parents": [ "ed098d62d66d91cf7330a37f9b83e303eb7f56d8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 10 20:18:23 2017 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Jan 02 20:14:34 2018 +0000" }, "message": "spi_master: Introduce SPI_MASTER_4BA feature flag\n\nAdd a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises\nprogrammer-side support for 4-byte addresses in generic commands (and\nread/write commands if the master uses the default implementations). Set\nit for all masters that handle commands address-agnostic.\n\nDon\u0027t prefer native 4BA instructions if the master doesn\u0027t support them.\n\nChange-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22421\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "ed098d62d66d91cf7330a37f9b83e303eb7f56d8", "tree": "639b6233e588fd8b4150b42112da36e239ba7fa4", "parents": [ "7e3c81ae7122120fe10d43fcba61a513e2461de9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Apr 21 23:47:08 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:49:05 2017 +0000" }, "message": "spi: Move ICH BBAR quirk out of the way\n\nGet rid of the layering violations around ICH\u0027s BBAR. Move all the weird\naddress handling into (surprise, surprise) `ichspi.c`. Might fix writes\nfor the `BBAR !\u003d 0` case by accident.\n\nBackground: Some ICHs have a BBAR (BIOS Base Address Configuration\nRegister) that, if set, limits the valid address range to [BBAR, 2^24).\nCurrent code lifted addresses for REMS, RES and READ operations by BBAR,\nnow we do it for all addresses in ichspi. Special care has to be taken\nif the BBAR is not aligned by the flash chip\u0027s size. In this case, the\nlower part of the chip (from BBAR aligned down, up to BBAR) is inacces-\nsible (this seems to be the original intend behind BBAR) and has to be\nleft out in the address offset calculation.\n\nChange-Id: Icbac513c5339e8aff624870252133284ef85ab73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22396\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7e3c81ae7122120fe10d43fcba61a513e2461de9", "tree": "f505342cd2879b9cc77c2cbf66dda0231869ee9c", "parents": [ "0ee2dc06839d2f4f3197dd0ef51202e51e945bea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:56:50 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:48:28 2017 +0000" }, "message": "spi25: Merge remainder of spi4ba in\n\nChange-Id: If581e24347e45cbb27002ea99ffd70e334c110cf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22388\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "7a077222566c84546dca4a56c1a509626036e429", "tree": "b4cd487275dd4ffc92ad6ac885268842efbe9eb3", "parents": [ "a1672f829328e877d9b8dea7777f25e2eba52d0e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:18:30 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:46:54 2017 +0000" }, "message": "spi25: Remove now obsolete `four_bytes_addr_funcs` path\n\nChange-Id: Idb7c576cb159630da2268813388b497cb5f46b43\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22386\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "a1672f829328e877d9b8dea7777f25e2eba52d0e", "tree": "8f90cab7e18bc875241ff66eef153b80e7c4a71b", "parents": [ "f43c654ad0dcb11b2738bbfac9246d09bb1949e5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 18:00:20 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:45:46 2017 +0000" }, "message": "spi25: Enable native 4BA read and write using feature bits\n\nPrefer the native 4BA instruction when they are supported. In this\ncase, override our logic to decide to use a 4BA address.\n\nChange-Id: I2f6817ca198bf923671a7aa67e956e5477d71848\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22385\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "f43c654ad0dcb11b2738bbfac9246d09bb1949e5", "tree": "1d1f74d771dc2e8e8a67dab985945c00f68e0097", "parents": [ "0ecbacbfca7f919f1780f5062c775d94c7869d81" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 17:47:28 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:44:17 2017 +0000" }, "message": "spi25: Integrate 4BA support\n\nAllow 4-byte addresses for instructions usually used with 3-byte\naddresses. Decide in which way the 4th byte will be communicated\nbased on the state of the chip (i.e. have we enabled 4BA mode)\nand a new feature bit for an extended address register. If we\nare not in 4BA mode and no extended address register is available\nor the write to it fails, bail out.\n\nWe cache the state of 4BA mode and the extended address register\nin the flashctx.\n\nChange-Id: I644600beaab9a571b97b67f7516abe571d3460c1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22384\nReviewed-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0ecbacbfca7f919f1780f5062c775d94c7869d81", "tree": "2f84f6406d00bc89dd13dfeff3e69f77671a8f9e", "parents": [ "a3140d0b18058610a2694fc3592031a849b0c92a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 14 16:50:43 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:42:49 2017 +0000" }, "message": "spi25: Use common code for nbyte read/write and block erase\n\nIntroduce spi_prepare_address() and spi_write_cmd() and use them in\nnbyte_program, nbyte_read and block-erase procedures. The former\nabstracts over the address part of a SPI command to make it exten-\nsible for 4-byte adressing. spi_write_cmd() implements a WREN + write\noperation with address and optionally up to 256 bytes of data. It\nprovides a common path to reduce overall redundancy.\n\nAlso, reduce the polling delay in spi_block_erase_c4() from 500s to\n500ms as the comment suggests.\n\nChange-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22383\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "a3140d0b18058610a2694fc3592031a849b0c92a", "tree": "194083a9889bb76a70cb447a14660d6ec449506c", "parents": [ "c8801734727e1e510cbd99e305007b73f9f57e93" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 11:20:58 2017 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 28 10:41:38 2017 +0000" }, "message": "spi25: Introduce spi_simple_write_cmd()\n\nspi_simple_write_cmd() executes WREN plus a single byte write and polls\nWIP afterwards. It\u0027s used to replace current spi_erase_chip_*() imple-\nmentations.\n\nChange-Id: Ib244356fa471e15863b52e6037899d19113cb4a9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22382\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n" }, { "commit": "9912718de18e455e16d26458aca4eac37f792aa2", "tree": "d447b47feb1d0f497c17ab6941e0b4c9afbed5cb", "parents": [ "b1f88360fc806ee69d7cf1b9404b3977bc53aace" ], "author": { "name": "Boris Baykov", "email": "dev@borisbaykov.com", "time": "Sat Jun 11 18:29:00 2016 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 15 12:30:26 2017 +0000" }, "message": "4BA: Flashrom integration for the 4-bytes addressing extensions\n\nThis patch integrates code of the previous patch into Flashrom\u0027s code.\nAll the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program\nand spi_byte_program. After this patch then are not static and can be called\nby their pointers saved in flashchips array. Also I added to flashrom.c some\ncode to switch a chip to 4-bytes addressing mode. And one error message is\ncorrected in spi.c because it\u0027s not suitable for 32-bit addresses.\n\nPatched files\n-------------\nflash.h\n+ added set of 4-bytes address functions to flashchip structure definition\n\nflashrom.c\n+ added switch to 4-bytes addressing more for chips which support it\n\nserprog.c\n+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read\n\nspi.c\n+ fixed flash chip size check in spi_chip_read\n\nspi25.c\n+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked\n+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked\n+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1\n\nConflicts:\n\tserprog.c\n\nChange-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049\nSigned-off-by: Boris Baykov \u003cdev@borisbaykov.com\u003e, Russia, Jan 2014\n[clg: ported from\n https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]\nSigned-off-by: Cédric Le Goater \u003cclg@kaod.org\u003e\nReviewed-on: https://review.coreboot.org/20505\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "731316a9128c4015bc0facd1743afeb3a080129e", "tree": "841a0f5b86816f556254d45c26859981561c3c81", "parents": [ "026c7416515985f47fe26a0478a37c0a1c2466c5" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Thu Jun 15 13:32:01 2017 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jul 13 16:23:16 2017 +0000" }, "message": "Enable continuous SPI reads\n\nPrevious unnecessary page-by-page reading is repurposed to\nread by big naturally aligned areas (now chip size limited\nto 16MB for future-proofing of 4 byte addressed multi-die chips)\nand serprog hack for continuous reads is removed.\n\nChange-Id: Iadf909c9216578b1c5dacd4c4991bb436e32edc9\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/20223\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "0a5f6e43d15c50409eb49369895ba2a56a173d47", "tree": "ac3c8c94e8163897b6efa0710dc544b1fe15f26b", "parents": [ "2a1aabaf90dc68a60fcf9c5d85744f386a4d920a" ], "author": { "name": "Urja Rannikko", "email": "urjaman@gmail.com", "time": "Mon Jun 22 23:59:15 2015 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Mon Jun 22 23:59:15 2015 +0000" }, "message": "spi25: ignore 0x00 as a manufacturer id in the generic match\n\nSaying that manufacturer id 0x00 is an \"unknown SPI chip\"\njust confuses people with external programmers without a\nproper connection to a chip and makes them think flashrom\ndoesn\u0027t support the chip they\u0027re trying to use.\nAlso causes unnecessary -c requirement with a multiple-slot\n(FWH/LPC and SPI) serprog device i was testing.\n\nCorresponding to flashrom svn r1893.\n\nSigned-off-by: Urja Rannikko \u003curjaman@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "a5bcbceb581f27cfc0055369d3dd9cfd1ae00bfa", "tree": "5daecd880a16b7011be28e064fb7550f3e6b7e58", "parents": [ "82b6ec1df30d3fca55547f230c76718d6e613b2a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Jul 19 22:03:29 2014 +0000" }, "message": "Rename programmer registration functions\n\nRegister_programmer suggests that we register a programmer. However,\nthat function registers a master for a given bus type, and a programmer\nmay support multiple masters (e.g. SPI, FWH). Rename a few other\nfunctions to be more consistent.\n\nCorresponding to flashrom svn r1831.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "f20b7beff054eb316088d590094d9efbc68dbee1", "tree": "6324be451385c9f9cea27381f35f300fbaa7f454", "parents": [ "20da4aa82cc11f25a6a4a52fd2bed219e6e1d829" ], "author": { "name": "Mark Marshall", "email": "mark.marshall@omicron.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri May 09 21:16:21 2014 +0000" }, "message": "Add \u0027const\u0027 keyword to chip write and other function prototypes\n\nCorresponding to flashrom svn r1789.\n\nInspired by and mostly based on a patch\nSigned-off-by: Mark Marshall \u003cmark.marshall@omicron.at\u003e\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "59c4d790bd5cc172041f780e103a85eb1595c23f", "tree": "649c9bf865c2160cdd0802bcd3246ea03a8d9cc7", "parents": [ "87ace663df470f7aadc5f5a71258d43f743f05a9" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Apr 26 16:13:09 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Apr 26 16:13:09 2014 +0000" }, "message": "Report if we are not able to disable AAI mode again\n\nCorresponding to flashrom svn r1780.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "87ace663df470f7aadc5f5a71258d43f743f05a9", "tree": "40907ddf7d721ff6e1c55948357f5998db9c710d", "parents": [ "1838591b684b515962b941018288366eb7276a2b" ], "author": { "name": "Stefan Reinauer", "email": "stefan.reinauer@coreboot.org", "time": "Sat Apr 26 16:12:55 2014 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Apr 26 16:12:55 2014 +0000" }, "message": "CID1130000: Unchecked return value in default_spi_write_aai()\n\nAlso, try to always disable WRDI because else the user is stuck\nwith a chip in AAI mode that won\u0027t return by itself w/o a reset.\n\nCorresponding to flashrom svn r1779.\n\nSigned-off-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "6f59b0bc5124f47294e261bb20924f9a8e505d89", "tree": "4fb4121d32185587067e5d50723ec879d56b8dbe", "parents": [ "c80c4a35a0d4eb51c142fc53ee4ae6d82f4dc37a" ], "author": { "name": "Nikolay Nikolaev", "email": "evrinoma@gmail.com", "time": "Fri Jun 28 21:29:51 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:29:51 2013 +0000" }, "message": "Add support for remaining Numonyx (Micron) N25Q chips\n\nAdd...\n - N25Q128..3E\n - N25Q128..1E\n - N25Q256..1E (defunct due to addressing)\n - N25Q256..3E (defunct due to addressing)\n - N25Q512..1E (defunct due to addressing)\n - N25Q512..3E (defunct due to addressing)\n - N25Q00A..3G (defunct due to addressing)\n\nAlso, refine existing family members.\n\nCorresponding to flashrom svn r1693.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "579f1e0b67a49282684a39f6c08bcf0813bd3c5c", "tree": "d14c6dfdb3bebba760dc9d83e14f0d5d5641abbe", "parents": [ "278ba6e96766f1d17202642a720f4e4eac007c74" ], "author": { "name": "Nikolay Nikolaev", "email": "evrinoma@gmail.com", "time": "Fri Jun 28 21:28:37 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Jun 28 21:28:37 2013 +0000" }, "message": "Introduce spi_block_erase_db()\n\nUsed for page erase on some chips (e.g. Numonyx M45PE and\nSanyo LF25FW series).\n\nCorresponding to flashrom svn r1682.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "730e7e74ebf11560d1c852934b18e98d1200ce53", "tree": "f9bc3f738776ff40df3d128e7dbc145ac580cb0c", "parents": [ "f44516121aecbd307a9398fe9bc1ec9ce25bfb09" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed May 01 14:04:19 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed May 01 14:04:19 2013 +0000" }, "message": "Update spi_get_erasefn_from_opcode()\n\nWe forgot to add a few SPI erase functions to the helper function that is\nused for SFDP. Also, sort the declarations in the header.\n\nCorresponding to flashrom svn r1672.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "3f5e35db4b22d36918adc7ee28b0d77ee50af568", "tree": "22d04b8a8c66a4f8be377c54b759215f12faf1bf", "parents": [ "e33c40eb7db5dc16763cd7c245578a968306a757" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Apr 19 01:58:33 2013 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Apr 19 01:58:33 2013 +0000" }, "message": "Refine PMC Pm25LV series\n\n - Add missing bits and resort chips\n - Refine Pm25LV512(A) and Pm25LV010\n Due to manufacturer ID continuation this one needs a new probing\n function: probe_spi_res3() which should be refactored in the future.\n The datasheet describes a very weird order of ID bytes:\n Vendor byte, model byte, vendor continuation byte. Let\u0027s pretend we did\n not read that or the datasheet is bogus (although the datasheet of the\n successor series describes the same but luckily additionally to RDID).\n - Add Pm25LV010A\n This was tested by Chi Zhang:\n http://paste.flashrom.org/view.php?id\u003d1573\n\nCorresponding to flashrom svn r1670.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "57794ac1580fc5efee3ba01a0c3e4539bb58d088", "tree": "4212a02023a6a8c6dd0b03d234e66471ddb5d634", "parents": [ "54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:04:20 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:04:20 2012 +0000" }, "message": "Add support for Atmel\u0027s AT25F series of SPI flash chips\n\nThis adds support for the following chips:\n - AT25F512, AT25F512A, AT25F512B\n - AT25F1024, AT25F1024A\n - AT25F2048\n - AT25F4096\n\nBesides the definitions of the the chips in flashchips.c this includes\n- a dedicated probing method (probe_spi_at25f)\n- pretty printing methods (spi_prettyprint_status_register_at25f*), and\n- unlocking methods (spi_disable_blockprotect_at25f*)\n\nCorresponding to flashrom svn r1637.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "6ee37e28365f2a8ea498d03b08def0dcb1cc6494", "tree": "3328db4647bba505d32ebc5755c511728cec438e", "parents": [ "2c421199ab37e691a83ad09b542ed43ee5811603" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:03:51 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Dec 29 15:03:51 2012 +0000" }, "message": "Improve SPI status register pretty printing\n\n - Move all functions related to SPI status registers to a new file\n spi25_statusreg.c. This includes the generic as well as the\n SST-specific functions from spi25.c and the chip-specific functions\n from a25.c and at25.c.\n - introduce helper functions\n * spi_prettyprint_status_register_hex()\n * spi_prettyprint_status_register_bpl()\n * spi_prettyprint_status_register_plain()\n Use the latter on every compatible flash chip that has no better printlock\n function set and get rid of the implicit pretty printing in the SPI probing\n functions.\n - remove\n * spi_prettyprint_status_register_common()\n * spi_prettyprint_status_register_amic_a25lq032() because it can be fully\n substituted with spi_prettyprint_status_register_amic_a25l032().\n * spi_prettyprint_status_register() (old switch, no longer needed)\n - promote and export\n * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1().\n * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2().\n * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3().\n - add #define TEST_BAD_REW and use it for a number of Atmel chips which\n had only TEST_BAD_READ set even though they dont have erasers or a write\n function set.\n\nCorresponding to flashrom svn r1634.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "94b39b47e475d3d8f153acea4a3fdcd6bbc81ea7", "tree": "42a78390b7e92346efe9c97c93e458eb91a75d86", "parents": [ "d956f822490e10be505355a59fc2498800d33c1d" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Oct 27 00:06:02 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Oct 27 00:06:02 2012 +0000" }, "message": "Add support for Atmel AT26DF041\n\nWicked chip: No WRSR, no write enable command (but swallows our\ndefault one without a problem), supports an auto-erasing page write\n(but even without that page writes are recommended to write the\nwhole page i.e. operate on a completely erased page), mad\nrequirements on block refreshments if only partly written.\n\nFound on my Intel D946GZIS and tested with my serprog in situ.\nUsing the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using\nthe spi_chip_write_256 command greatly improves performance and works\nflawlessly.\n\nCorresponding to flashrom svn r1616.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5609f9d408645657ef0dd2ca986ada5aaad4c875", "tree": "61f34750e39b1c9ec0be45555a8ca5b4125bc75b", "parents": [ "eb58257b9650b9191d8b987e0b214fed1ad2b77a" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 22 01:38:06 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat Sep 22 01:38:06 2012 +0000" }, "message": "Generify a25.c\u0027s SRWD printing function and move it to spi25.c\n\nCorresponding to flashrom svn r1602.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "3c0fcd0f30f2b3c0df57b66e645859d923e68d16", "tree": "55a94a70e9662a8558667c171b33bdfe99be483e", "parents": [ "14fbc4b40045c6fcb345da52ab048d961fc15c6c" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:46:56 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Sep 21 12:46:56 2012 +0000" }, "message": "Add spi_block_erase_62\n\nThis is used by the AT25F series (only?), but is generic enough to\nreside in spi25.c. The only currently supported chip is the AT25F512B.\nOther members of that series need some additional infrastructure code,\nhence this patch adds the erase function to the AT25F512B only.\n\nCorresponding to flashrom svn r1600.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "5a7cb847f096dacb0bf96b3aa909f79d76ae8204", "tree": "da511e990c1fdded61ee5dcefae38314c3a5a6cc", "parents": [ "dd73d830f7370b5f0bbdaa0780b0ff8d6ff1776a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Aug 25 01:17:58 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sat Aug 25 01:17:58 2012 +0000" }, "message": "Make struct flashchip a field in struct flashctx instead of a complete copy\n\nAll the driver conversion work and cleanup has been done by Stefan.\nflashrom.c and cli_classic.c are a joint work of Stefan and Carl-Daniel.\n\nCorresponding to flashrom svn r1579.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "87fbb77866b3d87086715f2602f7d54ecb83d97f", "tree": "2542f35c5f8d527ed3b0dbef126c74c345eaacdd", "parents": [ "1ba08f6d417921d9cb37b8b8823f4cb9d68f5895" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 02 23:56:49 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 02 23:56:49 2012 +0000" }, "message": "Refine messages of SPI block protection disables\n\nMake them real progress indicators with a final \"done\" message on success.\n\nCorresponding to flashrom svn r1561.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "1ba08f6d417921d9cb37b8b8823f4cb9d68f5895", "tree": "1dba91fd092949624eaaa4e73dd43719c06dc3f0", "parents": [ "cb30158fbf1a63d65de53080d0cdbcb23efd95d6" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 02 23:51:28 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Aug 02 23:51:28 2012 +0000" }, "message": "Clean up a25.c, at25.c, spi25.c\n\n- introduce spi_prettyprint_status_register_atmel_at25_wpen()\n- use spi_prettyprint_status_register_bit() where possible\n- generify spi_prettyprint_status_register_bp3210 and use it in at25.c too\n\nCorresponding to flashrom svn r1560.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "7bca126561b80f626dea269d7a6284a7cde0a8ed", "tree": "45c6b31e39846a88d89d157d758134d7b8dc1db1", "parents": [ "3464d05eb41ab4c7a6faba9a1a36bfbeda0de850" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Jun 15 22:28:12 2012 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Jun 15 22:28:12 2012 +0000" }, "message": "Let the programmer driver decide how to do AAI transfers\n\nCurrently spi_aai_write() is implemented without an abstraction\nmechanism for the programmer driver. This adds another function\npointer \u0027write_aai\u0027 to struct spi_programmer, which is set to\ndefault_spi_write_aai (renamed spi_aai_write) for all programmers\nfor now.\n\nA patch which utilises this abstraction in the dediprog driver will\nfollow.\n\nCorresponding to flashrom svn r1543.\n\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "5e695ab4d7555952f0b020f235d868955251e3ae", "tree": "2fbeddbc906b96de794bd02794d73360124277d6", "parents": [ "dc704edad44995845727a231e3f1d6dda74708fd" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun May 06 17:03:40 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun May 06 17:03:40 2012 +0000" }, "message": "dummyflasher: Add a status register to SPI chips\n\nCorresponding to flashrom svn r1532.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e \nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "96c2dfc10f35cca18dc9643dd23c8663d42ed53d", "tree": "9cd6a4035cfd1b102078d47c0078999a48c02d75", "parents": [ "3603a28a6d23efea90efb51216a08244e6645bcd" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed May 02 20:08:01 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed May 02 20:08:01 2012 +0000" }, "message": "spi25.c: Refactor spi_write_status_register helpers\n\nIn r1115 \"Write protection handling for Atmel AT25*\" the old\nspi_write_status_register function was duplicated to send WREN and\nEWSR commands respectively controlled by a new common wrapper function\nspi_write_status_register without a reason. Both functions\u0027 resulting\ncode is equal apart from the opcode used. The code itself does also\ndiffer in the macros used, but their value (apart from the opcode) is\nequal. This patch adds a new parameter for the opcode to the helper\nfunction which allows removal of the other one. This relies on the fact\nthat EWSR and WREN have the same INSIZE and OUTSIZE though. If that is\nreally seen as an issue, the sizes could be made parameters too.\n\nThis patch also changes the wrapper so that it no longer sets the\nfeature bits of the struct flash(ctx) argument. This may result in\nchanged output, because it no longer implicitly disables the debug\nmessage in following executions. Since almost all chips had their\nfeature bits fixed in the previous commit, this is a minor problem.\n\nAlso, spi_write_status_enable has been dead code since r658 or so.\nRemove it.\n\nCorresponding to flashrom svn r1528.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "ac1b4c8bd707c07e9636bedbd823ed5cb46f89ad", "tree": "5553eec8f0f86f363220a979342d59e3c55eae58", "parents": [ "ac427b22c4fa45936fe94af31a5e0422dd95c152" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Feb 17 14:51:04 2012 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Feb 17 14:51:04 2012 +0000" }, "message": "Add support for SFDP (JESD216)\n\nSimilar to modules using the opaque programmer framework (e.g. ICH Hardware\nSequencing) this uses a template struct flashchip element in flashchips.c with\na special probe function that fills the obtained values into that struct.\n\nThis allows yet unknown SPI chips to be supported (read, erase, write) almost\nas if it was already added to flashchips.c.\n\nDocumentation used:\nhttp://www.jedec.org/standards-documents/docs/jesd216 (2011-04)\nW25Q32BV data sheet Revision F (2011-04-01)\nEN25QH16 data sheet Revision F (2011-06-01)\nMX25L6436E data sheet Revision 1.8 (2011-12-26)\n\nTested-by: David Hendricks \u003cdhendrix@google.com\u003e\non W25Q64CV + dediprog\nTested-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\non a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog\n\nThanks also to Michael Karcher for his comments and preliminary review!\n\nCorresponding to flashrom svn r1500.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "c40cff7b86848f5b248d7fcf20f7d517b60c385d", "tree": "7f9db61c7b4868e513c4702cfe57bb35ae695266", "parents": [ "8a3c60cdd0e5632173567923ae1927763e31e857" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Dec 20 00:19:29 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Dec 20 00:19:29 2011 +0000" }, "message": "Have all programmer init functions register bus masters/programmers\n\nAll programmer types (Parallel, SPI, Opaque) now register themselves\ninto a generic programmer list and probing is now programmer-centric\ninstead of chip-centric.\nRegistering multiple SPI/... masters at the same time is now possible\nwithout any problems. Handling multiple flash chips is still unchanged,\nbut now we have the infrastructure to deal with \"dual BIOS\" and \"one\nflash behind southbridge and one flash behind EC\" sanely.\n\nA nice side effect is that this patch kills quite a few global variables\nand improves the situation for libflashrom.\n\nHint for developers:\nstruct {spi,par,opaque}_programmer now have a void *data pointer to\nstore any additional programmer-specific data, e.g. hardware\nconfiguration info.\n\nNote:\nflashrom -f -c FOO -r forced_read.bin\ndoes not work anymore. We have to find an architecturally clean way to\nsolve this.\n\nCorresponding to flashrom svn r1475.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "8a3c60cdd0e5632173567923ae1927763e31e857", "tree": "3a5514d022392cf4d8fa368f9f02653da21a93ca", "parents": [ "63fd9026f1e82b67a65072fda862ba7af35839e1" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Dec 18 15:01:24 2011 +0000" }, "message": "Add struct flashctx * parameter to all functions accessing flash chips\n\nAll programmer access function prototypes except init have been made\nstatic and moved to the respective file.\n\nA few internal functions in flash chip drivers had chipaddr parameters\nwhich are no longer needed.\n\nThe lines touched by flashctx changes have been adjusted to 80 columns\nexcept in header files.\n\nCorresponding to flashrom svn r1474.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "63fd9026f1e82b67a65072fda862ba7af35839e1", "tree": "7d9ffba077715cf9e75c9f4a36d0d7f11a3181f6", "parents": [ "83c92e983aaf11fb6f5bafb6744275c50add193c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Dec 14 22:25:15 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Dec 14 22:25:15 2011 +0000" }, "message": "Use struct flashctx instead of struct flashchip for flash chip access\n\nStruct flashchip is used only for the flashchips array and for\noperations which do not access hardware, e.g. printing a list of\nsupported flash chips.\n\nstruct flashctx (flash context) contains all data available in\nstruct flashchip, but it also contains runtime information like\nmapping addresses. struct flashctx is expected to grow additional\nmembers over time, a prime candidate being programmer info.\nstruct flashctx contains all of struct flashchip with identical\nmember layout, but struct flashctx has additional members at the end.\n\nThe separation between struct flashchip/flashctx shrinks the memory\nrequirement of the big flashchips array and allows future extension\nof flashctx without having to worry about bloat.\n\nCorresponding to flashrom svn r1473.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "c69c9c84e0341b701d9966fea8ce54d4e017bbb7", "tree": "2ea0b12abf9dd3483246423752239b88c6d7942e", "parents": [ "8ca4255d7968dbf6301367074cc7267d22a25658" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Nov 23 09:13:48 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Wed Nov 23 09:13:48 2011 +0000" }, "message": "Unsignify lengths and addresses in chip functions and structs\n\nPush those changes forward where needed to prevent new sign\nconversion warnings where possible.\n\nCorresponding to flashrom svn r1470.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "018d482536f2fa7897a03849374b5ec9cd2414f5", "tree": "7caa605a8a4cca7500139f1ec413577a49b43d9e", "parents": [ "7189a5ff8cb8cfc33ef2c0be3268204064a2771b" ], "author": { "name": "Paul Menzel", "email": "paulepanter@users.sourceforge.net", "time": "Fri Oct 21 12:33:07 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Fri Oct 21 12:33:07 2011 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 8\n\nTested mainboards:\nOK:\n- ASUS Crosshair II Formula\n http://www.flashrom.org/pipermail/flashrom/2011-September/007888.html\n- ASUS K8N\n http://paste.flashrom.org/view.php?id\u003d856\n- ASUS M2N-E SLI\n http://www.flashrom.org/pipermail/flashrom/2011-September/007909.html\n- ASUS M3N78-VM\n http://www.flashrom.org/pipermail/flashrom/2011-May/006496.html\n- ASUS M4A78LT-M LE\n http://www.flashrom.org/pipermail/flashrom/2011-September/007869.html\n- ASUS M4A89GTD PRO\n http://www.flashrom.org/pipermail/flashrom/2011-February/005824.html\n- MSI A75MA-G55 (MS-7696)\n http://www.flashrom.org/pipermail/flashrom/2011-October/008055.html\n- PCCHIPS M598LMR (V9.0)\n http://www.flashrom.org/pipermail/flashrom/2011-October/008051.html\n- ECS P4VXMS (V1.0A)\n http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html\n- Foxconn P4M800P7MA-RS2\n http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html\n- GIGABYTE GA-P67A-UD3P\n http://www.flashrom.org/pipermail/flashrom/2011-September/007930.html\n- GIGABYTE Z68MX-UD2H-B\n http://www.flashrom.org/pipermail/flashrom/2011-October/008080.html\n- ZOTAC Fusion-ITX WiFi (FUSION350-A-E)\n http://www.flashrom.org/pipermail/flashrom/2011-October/008011.html\nNOT OK:\n- ASUS P8B-E/4L\n http://www.flashrom.org/pipermail/flashrom/2011-October/008047.html\n- ASUS P8B WS\n http://www.flashrom.org/pipermail/flashrom/2011-October/008081.html\n\nTested chipsets:\n- MCP78S (:075d)\n http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html\n- VT8233 (:3074)\n http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html\n- SiS 530 (:0530)\n http://www.flashrom.org/pipermail/flashrom/2011-October/008051.html\n- P67 (:1c46)\n http://www.flashrom.org/pipermail/flashrom/2011-September/007930.html\n - Z68 (:1c44)\n http://www.flashrom.org/pipermail/flashrom/2011-October/008080.html\n\nTested flash chips:\n- mark AMIC A29002T as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-October/008085.html\n- mark Eon EN29F002(A)(N)T as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-October/008053.html\n- mark EonEN25F16 as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-February/005824.html\n- mark Macronix MX29F002(N)T as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-October/008083.html\n- mark Pm39LV040 as TEST_OK_PR\n http://www.flashrom.org/pipermail/flashrom/2011-September/007942.html\n- mark Pm39LV010 as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-September/007942.html\n- mark SST49LF008A as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-September/007989.html\n- mark SyncMOS {F,S,V}29C51002T as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-October/008052.html\n- mark W39V040B as write tested\n http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html\n- mark W39V040C as TEST_OK_PREW\n http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html\n\n- remove superfluous line break in enable_flash_ich_dc_spi\n- m-\u003eM in \"min\" and \"max\" (voltage) in print_wiki.c\n\nCorresponding to flashrom svn r1454.\n\n- spi25: get rid of unneccessary line breaks (on failed probes)\nwhich is\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n\n- rayer_spi.c: Remove double word: `s/the the/the/`\nwhich is\nSigned-off-by: Paul Menzel \u003cpaulepanter@users.sourceforge.net\u003e\n\nThe parts added until 2011-10-14 (most of this patch) were\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n\neverything else is\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "8c35745fcf3ed6eb2769beda0c8b941df07f6175", "tree": "2f3c43a3589edc55e7143b39d40df4a0cd039183", "parents": [ "e3185c0599d77c06b9665c9721649b96108c894f" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 22:42:18 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 22:42:18 2011 +0000" }, "message": "Revert \"Unsignify lengths and addresses in chip functions and structs\"\n\n- probe_timing was changed to unsigned although we use negative values\n for special cases\n- some code was not changed along hence did no longer compile:\n * dediprog\u0027s read and write functions\n * linux_spi\u0027s read and write functions\n- it introduced a number of new sign conversion warnings\n (http://paste.flashrom.org/view.php?id\u003d832)\n\nTo be safe this patch reverts all changes made in r1448, a corrected\npatch will follow later.\n\nThanks to idwer for pointing out the problem first!\n\nCorresponding to flashrom svn r1450.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "d196e7c1387b30ac35e7b0f605c79823ac9b5ec9", "tree": "e0f40df44cb94c62f150a84080bf7171f8623aa8", "parents": [ "75da80c17bbb992ce2b60ae15ef2fba7d23bfd8e" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 00:41:33 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sun Sep 18 00:41:33 2011 +0000" }, "message": "Unsignify lengths and addresses in chip functions and structs\n\nCorresponding to flashrom svn r1448.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "9932c7bebfe3b1500edd31d478ede058f8c5b096", "tree": "956be8456c22c23e69fdc69b49fb645079678fb8", "parents": [ "91199a1edd56e2a277c43c3d28000bb75e4d3525" ], "author": { "name": "Cristian Măgherușan-Stanciu", "email": "cristi.magherusan@gmail.com", "time": "Thu Jul 07 19:56:58 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Thu Jul 07 19:56:58 2011 +0000" }, "message": "Add a bunch of new/tested stuff and various small changes 4\n\n- add Asus E35M1-I DELUXE to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-June/006918.html\n- add Asus M3A to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-July/007085.html\n- add Freetech P6F91i to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html\n- add GA-M720-US3 to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-July/007096.html\n- add GA-MA770-UD3 (rev. 2.1) to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-June/006879.html\n- add GA-965GM-S2 to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-June/006746.html\n- add HP xw4400 (0A68h) to boards_known\n http://paste.flashrom.org/view.php?id\u003d686\n- add MSI MS-6566 (845 Ultra-C) to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-June/006908.html\n- add MSI MS-7698 (E350IA-E45) to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-June/007003.html\n- add PCCHIPS M863G (V5.1A) to boards_known\n http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html\n\n- modify the X8SIE entry in boards_known with the information from \"fuzzy\"\n http://paste.flashrom.org/view.php?id\u003d669\n\n- mark W29C020(C)/W29C022 as fully tested\n http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html\n- mark W49V002A as fully tested\n http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html\n- mark M25P128 as fully tested\n http://www.flashrom.org/pipermail/flashrom/2011-June/006843.html\n- mark SST39SF010A as fully tested\n http://www.flashrom.org/pipermail/flashrom/2011-July/007115.html\n\n- correct entries for GA-K8NS Pro-939 (was ultra before. thanks uwe!)\n- another tiny fix for \"a small fix\"/r1321\n Without this you will get broken bus names \"Unknow\" and \"Non-SP\".\n Note to self: don\u0027t self-ack even fairly trivial patches.\n- fix spew output of spi_rems in spi25.c\n- add URL to ASUS M3A76-CM\n- rename all Winbond W25x chips to W25X\n- fixes some common misspellings/typos in comments:\n lenght-\u003elength 2\n ocassional-\u003eoccasional 1\n unsucessfull-\u003eunsuccessful 1\n upto-\u003eup to 5\n\nCorresponding to flashrom svn r1367.\n\nthe patch for M25P128 is\nSigned-off-by: Cristian Măgherușan-Stanciu \u003ccristi.magherusan@gmail.com\u003e\n\nthe typos are\nSigned-off-by: Peter Huewe \u003cpeterhuewe@gmx.de\u003e\n\neverything else is\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "b4061f61cdf951760020c6d4789023d4001b9782", "tree": "99b4aec1edbe35372a0fe653b5448f52c0fe98c8", "parents": [ "bfa021dd80594e51fa25feee56457d545849e312" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 26 17:04:16 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 26 17:04:16 2011 +0000" }, "message": "Move erase verification to generic code\n\nErase functions are no longer called from chip drivers and thus their\ninternal erase verification can be moved to generic code. This also\nmakes it easier to skip the verify step if desired and to differentiate\nbetween failed command submission and failed erase verification.\n\nCorresponding to flashrom svn r1353.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "db45ab5eace5e984f533f3ee3e2d18b0a4eeaeae", "tree": "a0da8d004677bfd7373fa4f2246a612b27cb64bc", "parents": [ "355cbfdbef1fbd41b635a5b92195689fd4d3c0b1" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat May 28 22:59:05 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat May 28 22:59:05 2011 +0000" }, "message": "Tiny fix for a small fix\n\nThere was one line break added too much in the previous commit, sorry.\nthe probing functions need to output at least one \u0027\\n\u0027 for satisfactory output.\nthat means even in error cases they have to do that.\nOTOH they should not output a sequence of \"\\n\\n\" because\nit would distort the verbose probing output with empty lines.\n\nCorresponding to flashrom svn r1322.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "355cbfdbef1fbd41b635a5b92195689fd4d3c0b1", "tree": "bf90deeafdc4ff48c7778e0f48e716befa48cf7c", "parents": [ "0fbba98c27433c97f42936e9e16805089ce3a296" ], "author": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat May 28 02:37:14 2011 +0000" }, "committer": { "name": "Stefan Tauner", "email": "stefan.tauner@alumni.tuwien.ac.at", "time": "Sat May 28 02:37:14 2011 +0000" }, "message": "Small fixes\n\n- missing spaces in code and output\n- improved documentation/naming/output\n- missing line breaks in spi probing functions\n\nCorresponding to flashrom svn r1321.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "7a3bd8f28f3b8dd854e453703efb702f07294ae5", "tree": "b2a63e7607e23f2f2913f7ec5b3d5b692d87c2c0", "parents": [ "c965c2de64b695ef18865ac8220abd57b56c364c" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu May 19 00:06:06 2011 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu May 19 00:06:06 2011 +0000" }, "message": "Refine status register and lock printing of Atmel and AMIC SPI chips\n\nAdd lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU,\nA25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU,\nA25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032\nto a25.c.\n\nAdd lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A,\nAT26DF321.\n\nMove Atmel AT25*/AT26* lock related functions originally added in r1115\nfrom spi25.c to at25.c.\n\nFor SPI chips the lock printing was handled by one common function, but\nsharing a common function which only is a big switch() statement doesn\u0027t\nmake sense, especially if we can define lock printing functions per\nflash chip anyway.\n\nThe printlock function pointer in struct flashchip is used to print\nstatus register and locking information, and serves as replacement for\nimplicit status register and lock printing during probe. That code will\nlater be changed to store locking info in a machine- accessible data\nstructure so flashrom can handle locked regions correctly.\n\nCorresponding to flashrom svn r1316.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n" }, { "commit": "b9dbe48b77384e2faf0619161fc5c55afe388ea9", "tree": "8b556f82073e824bc1e9a4cc9547d67b1d902cee", "parents": [ "627975196d0630a137548df631756e656a8139af" ], "author": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Wed May 11 17:07:07 2011 +0000" }, "committer": { "name": "Michael Karcher", "email": "flashrom@mkarcher.dialup.fu-berlin.de", "time": "Wed May 11 17:07:07 2011 +0000" }, "message": "Kill central list of SPI programmers\n\nRemove the array spi_programmer, replace it by dynamic registration\ninstead. Also initially start with no busses supported, and switch to\nthe default non-SPI only for the internal programmer.\n\nAlso this patch changes the initialization for the buses_supported variable\nfrom \"everything-except-SPI\" to \"nothing\". All programmers have to set the\nbus type on their own, and this enables register_spi_programmer to just add\nthe SPI both for on-board SPI interfaces (where the internal programmer\nalready detected the other bus types), as well as for external programmers\n(where we have the default \"none\").\n\nCorresponding to flashrom svn r1299.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "a60faab83ef86bcf2884311db07cf13f445d7f47", "tree": "9de9787987eb6a3374e18835b196b7ac6cb9ad19", "parents": [ "2c3afa34fcfc72abe6b3e0fd034632226fa75522" ], "author": { "name": "Mathias Krause", "email": "mathias.krause@secunet.com", "time": "Mon Jan 17 07:50:42 2011 +0000" }, "committer": { "name": "Mathias Krause", "email": "mathias.krause@secunet.com", "time": "Mon Jan 17 07:50:42 2011 +0000" }, "message": "Convince compilers to put constant data into the .rodata section\n\nThis patch reduces the stack usage by declaring \u0027const\u0027 stack variables\nas \u0027static const\u0027 so they end up in the .rodata section instead of being\ncopied from there to the stack for every invocation of the corresponding\nfunction.\n\nAs a plus we end up in having a smaller binary as the \"copy from .rodata\nto stack\" code isn\u0027t emitted by the compiler any more (roughly -100\nbytes).\n\nCorresponding to flashrom svn r1252.\n\nSigned-off-by: Mathias Krause \u003cmathias.krause@secunet.com\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coreboot.org\u003e\n" }, { "commit": "ccfe0acbbf5256ecc5ee6d1fe964d634d08e391f", "tree": "5b8d6ec01a60208129a46e24a33ab0c18f9012c9", "parents": [ "f59e2637d184eef8e3ef8914ac500161804fc526" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 27 22:07:11 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 27 22:07:11 2010 +0000" }, "message": "Fix internal offset calculations for SPI BYTE PROGRAM and SPI AAI PROGRAM\n\nThe bug was invisible so far because we always started at offset 0. The\npending partial write patch uses nonzero start offsets and trips over\nthis bug.\n\nClarify a few comments in IT87 SPI.\n\nThanks to Idwer Vollering for reporting write breakage with my latest\npartial write patch. This should fix the underlying problem.\n\nCorresponding to flashrom svn r1217.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\n" }, { "commit": "75a58f94cc641e8051169ec6bb9894a390a8e2bf", "tree": "eb3c0573cecfe70ded0b96003dc6f4d5e55975d4", "parents": [ "79e6757d269b91ee759bd569df7093225f4f3715" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 13 22:26:56 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Oct 13 22:26:56 2010 +0000" }, "message": "Switch all flash chips to partial write\n\nThe inner write functions which handle partial write are renamed to the\noriginal name of their wrappers. The write wrappers are removed.\n\nCorresponding to flashrom svn r1211.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Maciej Pijanka \u003cmaciej.pijanka@gmail.com\u003e\nTested-by: Andrew Morgan \u003cziltro@ziltro.com\u003e\nTested-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nAcked-by: Idwer Vollering \u003cvidwer@gmail.com\u003e\nTested-by: Sean Nelson \u003caudiohacked@gmail.com\u003e \nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e \n" }, { "commit": "f52f784bb300ec0acbd6c6bd9e6c3e5b435c4a90", "tree": "957964a468245432abbd23cd06839898b64105ce", "parents": [ "92c8b0cec2ed06db9c24c4d93cf38a596edf23ab" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Oct 08 18:52:29 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Oct 08 18:52:29 2010 +0000" }, "message": "Move implicit erase out of chip drivers\n\nFlashrom had an implicit erase-on-write for most flash chip and\nprogrammer drivers, but it was not entirely consistent.\n\nSome drivers had their own hand-rolled partial update functionality\nwhich made handling partial updates from generic code impossible.\n\nMove implicit erase out of chip drivers, and kill some dead erase\nfunctions at the same time. A full chip erase is now performed in the\ngeneric code for all flash chips on write, and after that the whole chip\nis written.\n\nCorresponding to flashrom svn r1206.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "174f55bdec62b5deaa0ed52fa335c1ee9ac9a72c", "tree": "ee72939ddee85b2483d90ca0d4f2706482a30433", "parents": [ "ef69783a8356a6d7967746d3a0902a6d04ae82f0" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Oct 08 00:37:55 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Fri Oct 08 00:37:55 2010 +0000" }, "message": "Fix timing of SPI status register writes (WRSR)\n\nSPI write status register (WRSR) may take longer than 100 ms, and it\nmakes sense to poll for completion in 10 ms steps until 5 s are over.\nThis patch complements r1115.\n\nCorresponding to flashrom svn r1201.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Joshua Roys \u003croysjosh@gmail.com\u003e\n" }, { "commit": "1db7a448b37f1f699bd9a64d2187f3883e0f4503", "tree": "90d10ef4b79f1e9fdeb2ad9cdb165f0d04f429c7", "parents": [ "738e252112271f63c8ad4c9a135cfe17ff98e87d" ], "author": { "name": "Helge Wagner", "email": "helge.wagner@ge.com", "time": "Tue Oct 05 22:29:08 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Oct 05 22:29:08 2010 +0000" }, "message": "Massive speedups for SST25VF032B and SST25VF064C\n\nUse AAI write for SST SST25VF032B.\nSpeedup from 228 to 113 seconds.\n\nUse page (256 byte) write for SST SST25VF064C.\nSpeedup from 3091 to 123 seconds.\n\nCorresponding to flashrom svn r1194.\n\nSigned-off-by: Helge Wagner \u003chelge.wagner@ge.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "6eabe282fe54a69df92f0e8cf3c251c9165202eb", "tree": "ec68d59a682c8591e4a5cb9a78998ac86d18d924", "parents": [ "85835d891d87981cbd0859b03d814f43eaff2826" ], "author": { "name": "Mattias Mattsson", "email": "vitplister@gmail.com", "time": "Wed Sep 15 23:31:03 2010 +0000" }, "committer": { "name": "Mattias Mattsson", "email": "vitplister@gmail.com", "time": "Wed Sep 15 23:31:03 2010 +0000" }, "message": "This patch changes the prefix of chip constant #defines in the following way\n\nAM_* -\u003e AMD_AM*\nAT_* -\u003e ATMEL_AT*\nEN_* -\u003e EON_EN*\nHY_* -\u003e HYUNDAI_HY*\nMBM* -\u003e FUJITSU_MBM*\nMX_ID -\u003e MACRONIX_ID\nMX_* -\u003e MACRONIX_MX*\nPMC_* -\u003e PMC_PM*\nSST_* -\u003e SST_SST*\n\nIt leaves the Intel #defines alone because there is another pending\npatch for that:\nhttp://patchwork.coreboot.org/patch/1937/\n\nSome background discussion here:\nhttp://www.flashrom.org/pipermail/flashrom/2010-July/004059.html\n\nCorresponding to flashrom svn r1175.\n\nSigned-off-by: Mattias Mattsson \u003cvitplister@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "fd7075ae75c04df49f61a7617e772c54e0b4984d", "tree": "c95adc0c593268590615032f0d297e7190bcf2a7", "parents": [ "f792c7d4cb43e8c34719e015f20e8049579e34af" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 29 13:09:18 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 29 13:09:18 2010 +0000" }, "message": "Add detailed status register printing and unlocking for all ATMEL AT25* chips\n\nAdd support for Atmel AT25DF081A and AT25DQ161.\n\nSome chips require EWSR before WRSR, others require WREN before WRSR,\nand some support both variants. Add feature_bits to select the correct\nSPI command, and default to EWSR.\n\nCorresponding to flashrom svn r1115.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Steven Rosario\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "5b997c3ed66ddbbb9470f27d4e27ab4c263bc9cf", "tree": "adbaace5de6bb0d97a58143c7e3ae775a15d47ff", "parents": [ "1d3a2fefbc636fb569bd1d018fb97b1b17c08e99" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jul 27 22:41:39 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Tue Jul 27 22:41:39 2010 +0000" }, "message": "Split off programmer.h from flash.h\n\nProgrammer specific functions are of absolutely no interest to any file\nexcept those dealing with programmer specific actions (special SPI\ncommands and the generic core).\n\nThe new header structure is as follows (and yes, improvements are\npossible):\nflashchips.h flash chip IDs\nchipdrivers.h chip-specific read/write/... functions\nflash.h common header for all stuff that doesn\u0027t fit elsewhere\nhwaccess.h hardware access functions\nprogrammer.h programmer specific functions\ncoreboot_tables.h header from coreboot, internal programmer only\nspi.h SPI command definitions\n\nCorresponding to flashrom svn r1112.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n" }, { "commit": "df90d3a38fb926bad04a46835eafa00661c46cd8", "tree": "978f3887548191e960dcb6007fa27fbd56256e70", "parents": [ "74a828a6ddada5dc71c77580d597d6af5603a440" ], "author": { "name": "Daniel Lenski", "email": "dlenski@gmail.com", "time": "Thu Jul 22 11:44:38 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Thu Jul 22 11:44:38 2010 +0000" }, "message": "Add support for the following AMIC SPI chips\n\nhttp://www.amictechnology.com/pdf/A25L20P.pdf covers:\nAMIC A25L05PT\nAMIC A25L05PU\nAMIC A25L10PT\nAMIC A25L10PU\nAMIC A25L20PT\nAMIC A25L20PU\nhttp://www.amictechnology.com/pdf/A25L16P.pdf covers:\nAMIC A25L16PT\nAMIC A25L16PU\n\nClarify the situation surrounding the A25L40PT and A25L40PU chips which\nshare the same RDID values, despite the fact that their erase block\nlayouts are different. Rudolf Marek tested and confirmed the distinct\nerase block layouts of these chips.\n\nAdd a pretty-printer for the AMIC SPI chip status register\nAdd a generic AMIC chip type.\n\nCorresponding to flashrom svn r1096.\n\nSigned-off-by: Daniel Lenski \u003cdlenski@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n" }, { "commit": "29a1c66a23bc8685f456d548361b735bf36dcf2b", "tree": "963d487fa71ce4b6ad998d89fde9e167ce11e6bb", "parents": [ "ca812d40d461e70a70df6079978e96642775e7b2" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 20:21:22 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 20:21:22 2010 +0000" }, "message": "Use generic unlocking infrastructure for SPI chips\n\nActually check if the unlock worked instead of just assuming it worked.\n\nCorresponding to flashrom svn r1082.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "9a795d83fbb8842a271d5e037dc983a57b0419fd", "tree": "a9049f708d0ab7d42d122fecd23855aaa819c5bc", "parents": [ "1748c5701f77ab7164ab3311f37abc356d825ccb" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 16:19:05 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Wed Jul 14 16:19:05 2010 +0000" }, "message": "Convert SPI chips to partial write\n\nHowever, wrap the write functions in a compat layer to allow converting\nthe rest of flashrom later. Tested on Intel NM10 by David Hendricks.\n\nCorresponding to flashrom svn r1080.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n" }, { "commit": "3a25fea9e7726109df0c09aaacefb446ab1a9d0d", "tree": "7e0d39872f7c96eec1cc3be521eb99b33ac91fd2", "parents": [ "1b0ba893529cf93ae54b91607d93d3ad49c259e5" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 11:02:33 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 11:02:33 2010 +0000" }, "message": "The SPI opcode 0xd8 is not a chip erase opcode on any chip out there\n\nBesides that, the function as implemented just walks the chip and\nignores sector sizes.\nSector erase with SPI opcode 0xd8 is of course still supported.\nKill a declaration for a nonexisting function while we\u0027re at it.\n\nCorresponding to flashrom svn r1054.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n" }, { "commit": "9c62d11d55a492f59781874cb74ce84f8dde1bfc", "tree": "204c545093f263b9187aa9cdc220efba2fb57a72", "parents": [ "8ae500e09dc4c55d0a8e39b6f751ca476afd21c4" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 10:41:35 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 10:41:35 2010 +0000" }, "message": "Refine SPI AAI support\n\nModernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run\nwithout warnings on ICH/VIA SPI. Add some code to make conversion to\npartial write possible for AAI.\n\nCorresponding to flashrom svn r1052.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n" }, { "commit": "8ae500e09dc4c55d0a8e39b6f751ca476afd21c4", "tree": "41d248006fe015d9b382728a9defb987427611e3", "parents": [ "80a59ea2d56c57490692ba76fc1b5dc71a2dc97a" ], "author": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 10:39:33 2010 +0000" }, "committer": { "name": "Carl-Daniel Hailfinger", "email": "c-d.hailfinger.devel.2006@gmx.net", "time": "Sun Jun 20 10:39:33 2010 +0000" }, "message": "Fix message printing for SPI RES on spew level\n\nUse a blacklist instead of a whitelist for 4-byte SPI RDID.\nTell users where to report bugs.\n\nCorresponding to flashrom svn r1051.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n" } ], "next": "71127727dcff4f7e70b318d7a5eb87f0c8fcc4d7" }