)]}'
{
  "log": [
    {
      "commit": "4760b6ec1f7fbcee1bf238a25e3df56a86327a5a",
      "tree": "a4c3762b1228f901f62d40b53ed1a953b25926b4",
      "parents": [
        "0c9af0a639bf9180839d548f91547b58de921ca9"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Jan 06 23:45:28 2024 +0100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi25: Implement multi-i/o reads\n\nWe describe a read operation in a new  `struct spi_read_op`. It\u0027s\ncomprised of the i/o mode, its opcode, an optional mode byte, and\nthe number of dummy bytes.\n\nBased on this information  about the various read operations, and\nthe flash and master feature flags,  we select the read operation\nwith the highest throughput.\n\nThe following assumption is made about 4BA chips: When it supports\nnative-4BA fast reads  and a multi-i/o version of the regular fast\nread, then it should also support the respective native-4BA, multi-\ni/o version (yes, JEDEC, there are too many read commands!). So far\nthis seems to hold for the chips in our database.\n\nChange-Id: I3c93e71d85f769831d637c14d3571f7ddb54d8b2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/49\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n"
    },
    {
      "commit": "bd72a470b9b58386b52ca4568313be71b4d2c472",
      "tree": "078afe70db3836ef41b37ce2c64fb6de67c38747",
      "parents": [
        "3d728e7524fe086e90779ea76bf2f9bd02cdf6de"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Sun Jul 24 17:11:05 2022 +0300"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi25_statusreg: support reading/writing configuration register\n\nOne more variation of registers.\n\nThis one is read via a separate RDCR command, but written as if it\u0027s\nSR2 using WRSR_EXT2.\n\nPorted to flashprog w/o the FEATURE_CFGR flag, we\u0027ll already have that\ninformation in the register description.\n\nChange-Id: I45f9afcc31f1928ef6263a749596380082963de4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOrignal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211\nOrignal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOrignal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/71007\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "3d728e7524fe086e90779ea76bf2f9bd02cdf6de",
      "tree": "74d3bec50d87ac2fc45c1c2beaf5d780e6acda4a",
      "parents": [
        "a358b14d2e7e93e317499a687223ada2d221a36a"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Sat Nov 27 15:14:27 2021 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Jul 22 10:08:47 2024 +0000"
      },
      "message": "spi25_statusreg.c: support reading security register\n\nNot to be confused with \"secure registers\" of OTP.\n\nSecurity register is a dedicated status register for security-related\nbits. You don\u0027t write its value directly, issuing special write commands\nwith no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL\ncommands). No WREN is necessary, but at least some datasheets indicate\nBUSY state after those write commands.\n\nUnlike cases where OTP bit is part of SR and can only be written while\nin OTP mode, security register can only be written outside of the mode.\n\nThe register is found in at least these chips by Macronix:\n * MX25L6436E\n * MX25L6445E\n * MX25L6465E\n * MX25L6473E\n\nPorted to flashprog w/o the FEATURE_SCUR flag, we\u0027ll already have that\ninformation in the register description.\n\nChange-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/71006\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8",
      "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0",
      "parents": [
        "a02df33fbf1c196395a61049e60895d4ae0e0a5b"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Aug 12 01:13:45 2023 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Mon Sep 18 19:24:39 2023 +0000"
      },
      "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n"
    },
    {
      "commit": "58015c25eb05fa77966d1c53261a83b56a3cf6b3",
      "tree": "a1df11881a074c8c66de756f846be9030ce0443a",
      "parents": [
        "e276765eca031c6900d37b22b89e686283f39c91"
      ],
      "author": {
        "name": "Thomas Heijligen",
        "email": "thomas.heijligen@secunet.com",
        "time": "Thu Apr 14 13:50:55 2022 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Jan 29 12:29:02 2023 +0000"
      },
      "message": "Introduce an `include` directory for header files\n\nMove all header files to the new `include` directory.\nAdapt include directives and build systems to the new directory.\n\nChange-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf\nSigned-off-by: Felix Singer \u003cfelix.singer@secunet.com\u003e\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72322\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n"
    },
    {
      "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d",
      "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35",
      "parents": [
        "542b1f04869e7ac42b84800675f08f617ddf3f2d"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue May 24 15:07:34 2022 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:52 2022 +0100"
      },
      "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n  flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n  instructions (and some programmers may be picky about which\n  instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "3f3c1f3238dcede30d0d15d36da6326b428b8b12",
      "tree": "9adc4f207793fe401c9ffd28e2f7c60460766533",
      "parents": [
        "478e179f2d5ecf6a8b82984444b9111913a8f50f"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat May 28 16:48:26 2022 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:50 2022 +0100"
      },
      "message": "spi25_statusreg: Allow WRSR_EXT for Status Register 3\n\nSpansion flash chips S25FL128L and S25FL256L use the WRSR instruction to\nwrite more than 2 registers. So align SR2 and SR3 support: The current\nFEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3\nis added. Also, WRSR3 needs a separate flag now.\n\nVerified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "0b2e7dd80847f19f30db35e6e0d47f3c7b02ffbf",
      "tree": "020dea176939135afa15e8f328088e808b6c812a",
      "parents": [
        "9bf829d9a0b08323ca0ef8f2b52737f3eafbfe21"
      ],
      "author": {
        "name": "Sergii Dmytruk",
        "email": "sergii.dmytruk@3mdeb.com",
        "time": "Sun Dec 19 18:37:51 2021 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:48 2022 +0100"
      },
      "message": "spi25_statusreg.c: add SR3 read/write support\n\nAdds support for reading and writing the third status register.\n\nFeature flag is not needed because it would never on its own control\nwhether SR3 access occurs.  If added, it would be in one of three\npossible states: wrong, useless or redundant.\n\nChange-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70980\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "9de3f8710d5c46d35cd9869018c85e5aa51483b0",
      "tree": "b742b7c1631b89e1cfa18a5553fc3da57ed2b8df",
      "parents": [
        "0167522794a2e66f00248347122c1bb8ce3b001d"
      ],
      "author": {
        "name": "Nikolai Artemiev",
        "email": "nartemiev@google.com",
        "time": "Wed Oct 20 22:32:25 2021 +1100"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Dec 30 01:16:44 2022 +0100"
      },
      "message": "spi25_statusreg,flashchips: add SR2 read/write support\n\nThis patch adds support for reading and writing the second status\nregister and enables it on a limited set of flash chips.\n\nChip support for RDSR2/WRSR2/extended WRSR is represented using feature\nflags to be consistent with how other SPI capabilities are represented.\n\nTested: flashrom -{r,w,E}\nTested: flashrom --wp-{enable,disable,range,list,status} at end of patch series\nTested: logged SR2 read/write values during wp commands\n\nChange-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "3d8868c2b46548be6885198987492d91933c9ff7",
      "tree": "2277db98f8b19982802f812b2a984a2591009e37",
      "parents": [
        "4a84ec273a487c27f91bd3df70cbdf8894af70e1"
      ],
      "author": {
        "name": "Konstantin Grudnev",
        "email": "grudnevkv@gmail.com",
        "time": "Tue Jul 23 00:48:54 2019 +0300"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Fri Oct 04 17:41:01 2019 +0000"
      },
      "message": "Add support for M95M02-A125\n\nAutomotive 2 Mbit (256KiB) serial SPI bus EEPROM\nPREW tested successfully with use of ch341a programmer\non Linux host 5.2.0-1-MANJARO x86_64\n\nSigned-off-by: Konstantin Grudnev \u003cgrudnevkv@gmail.com\u003e\nChange-Id: Ic29cd9051c7eac4822d620c299834134f987f01b\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34496\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "93db6e16895287b7ac3a8a8f7f4a4f176547b7ed",
      "tree": "5f7d8dcfce6b7bb62829251b381526fbdc2f5497",
      "parents": [
        "cb97368328bc68698ab7e58a6d692635dfb1b1c7"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sun Sep 30 01:18:43 2018 +0200"
      },
      "committer": {
        "name": "David Hendricks",
        "email": "david.hendricks@gmail.com",
        "time": "Mon Apr 15 18:44:22 2019 +0000"
      },
      "message": "dediprog: Enable 4BA support for SF600, protocol V2\n\nThe only combination we could successfully test so far is the SF600 with\nprotocol version V2 (firmware 7.2.21) and native 4BA commands. Let\u0027s\nenable that at least.\n\nChange-Id: I665d0806aec469a3509620a760815861fbe22841\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/28804\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n"
    },
    {
      "commit": "e083880279119677e443fc16b4694f8c81bf2c40",
      "tree": "03413b996779bc4c86ec41590f3e7bcdd97d0ef5",
      "parents": [
        "124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b"
      ],
      "author": {
        "name": "Elyes HAOUAS",
        "email": "ehaouas@noos.fr",
        "time": "Mon Apr 02 11:14:02 2018 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Tue Apr 24 20:21:41 2018 +0000"
      },
      "message": "Remove address from GPLv2 headers\n\nChange-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4\nSigned-off-by: Elyes HAOUAS \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/25381\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n"
    },
    {
      "commit": "7e3c81ae7122120fe10d43fcba61a513e2461de9",
      "tree": "f505342cd2879b9cc77c2cbf66dda0231869ee9c",
      "parents": [
        "0ee2dc06839d2f4f3197dd0ef51202e51e945bea"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Oct 14 18:56:50 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Dec 28 10:48:28 2017 +0000"
      },
      "message": "spi25: Merge remainder of spi4ba in\n\nChange-Id: If581e24347e45cbb27002ea99ffd70e334c110cf\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22388\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n"
    },
    {
      "commit": "0ecbacbfca7f919f1780f5062c775d94c7869d81",
      "tree": "2f84f6406d00bc89dd13dfeff3e69f77671a8f9e",
      "parents": [
        "a3140d0b18058610a2694fc3592031a849b0c92a"
      ],
      "author": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Sat Oct 14 16:50:43 2017 +0200"
      },
      "committer": {
        "name": "Nico Huber",
        "email": "nico.h@gmx.de",
        "time": "Thu Dec 28 10:42:49 2017 +0000"
      },
      "message": "spi25: Use common code for nbyte read/write and block erase\n\nIntroduce spi_prepare_address() and spi_write_cmd() and use them in\nnbyte_program, nbyte_read and block-erase procedures. The former\nabstracts over the address part of a SPI command to make it exten-\nsible for 4-byte adressing. spi_write_cmd() implements a WREN + write\noperation with address and optionally up to 256 bytes of data. It\nprovides a common path to reduce overall redundancy.\n\nAlso, reduce the polling delay in spi_block_erase_c4() from 500s to\n500ms as the comment suggests.\n\nChange-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/22383\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n"
    },
    {
      "commit": "6f59b0bc5124f47294e261bb20924f9a8e505d89",
      "tree": "4fb4121d32185587067e5d50723ec879d56b8dbe",
      "parents": [
        "c80c4a35a0d4eb51c142fc53ee4ae6d82f4dc37a"
      ],
      "author": {
        "name": "Nikolay Nikolaev",
        "email": "evrinoma@gmail.com",
        "time": "Fri Jun 28 21:29:51 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:29:51 2013 +0000"
      },
      "message": "Add support for remaining Numonyx (Micron) N25Q chips\n\nAdd...\n - N25Q128..3E\n - N25Q128..1E\n - N25Q256..1E (defunct due to addressing)\n - N25Q256..3E (defunct due to addressing)\n - N25Q512..1E (defunct due to addressing)\n - N25Q512..3E (defunct due to addressing)\n - N25Q00A..3G (defunct due to addressing)\n\nAlso, refine existing family members.\n\nCorresponding to flashrom svn r1693.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "579f1e0b67a49282684a39f6c08bcf0813bd3c5c",
      "tree": "d14c6dfdb3bebba760dc9d83e14f0d5d5641abbe",
      "parents": [
        "278ba6e96766f1d17202642a720f4e4eac007c74"
      ],
      "author": {
        "name": "Nikolay Nikolaev",
        "email": "evrinoma@gmail.com",
        "time": "Fri Jun 28 21:28:37 2013 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Jun 28 21:28:37 2013 +0000"
      },
      "message": "Introduce spi_block_erase_db()\n\nUsed for page erase on some chips (e.g. Numonyx M45PE and\nSanyo LF25FW series).\n\nCorresponding to flashrom svn r1682.\n\nSigned-off-by: Nikolay Nikolaev \u003cevrinoma@gmail.com\u003e\nReviewed-by: Steven Zakulec \u003cspzakulec@gmail.com\u003e\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "57794ac1580fc5efee3ba01a0c3e4539bb58d088",
      "tree": "4212a02023a6a8c6dd0b03d234e66471ddb5d634",
      "parents": [
        "54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:20 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Dec 29 15:04:20 2012 +0000"
      },
      "message": "Add support for Atmel\u0027s AT25F series of SPI flash chips\n\nThis adds support for the following chips:\n - AT25F512, AT25F512A, AT25F512B\n - AT25F1024, AT25F1024A\n - AT25F2048\n - AT25F4096\n\nBesides the definitions of the the chips in flashchips.c this includes\n- a dedicated probing method (probe_spi_at25f)\n- pretty printing methods (spi_prettyprint_status_register_at25f*), and\n- unlocking methods (spi_disable_blockprotect_at25f*)\n\nCorresponding to flashrom svn r1637.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "94b39b47e475d3d8f153acea4a3fdcd6bbc81ea7",
      "tree": "42a78390b7e92346efe9c97c93e458eb91a75d86",
      "parents": [
        "d956f822490e10be505355a59fc2498800d33c1d"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Oct 27 00:06:02 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sat Oct 27 00:06:02 2012 +0000"
      },
      "message": "Add support for Atmel AT26DF041\n\nWicked chip: No WRSR, no write enable command (but swallows our\ndefault one without a problem), supports an auto-erasing page write\n(but even without that page writes are recommended to write the\nwhole page i.e. operate on a completely erased page), mad\nrequirements on block refreshments if only partly written.\n\nFound on my Intel D946GZIS and tested with my serprog in situ.\nUsing the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using\nthe spi_chip_write_256 command greatly improves performance and works\nflawlessly.\n\nCorresponding to flashrom svn r1616.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "3c0fcd0f30f2b3c0df57b66e645859d923e68d16",
      "tree": "55a94a70e9662a8558667c171b33bdfe99be483e",
      "parents": [
        "14fbc4b40045c6fcb345da52ab048d961fc15c6c"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Sep 21 12:46:56 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Sep 21 12:46:56 2012 +0000"
      },
      "message": "Add spi_block_erase_62\n\nThis is used by the AT25F series (only?), but is generic enough to\nreside in spi25.c. The only currently supported chip is the AT25F512B.\nOther members of that series need some additional infrastructure code,\nhence this patch adds the erase function to the AT25F512B only.\n\nCorresponding to flashrom svn r1600.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n"
    },
    {
      "commit": "5e695ab4d7555952f0b020f235d868955251e3ae",
      "tree": "2fbeddbc906b96de794bd02794d73360124277d6",
      "parents": [
        "dc704edad44995845727a231e3f1d6dda74708fd"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun May 06 17:03:40 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Sun May 06 17:03:40 2012 +0000"
      },
      "message": "dummyflasher: Add a status register to SPI chips\n\nCorresponding to flashrom svn r1532.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e  \nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "ac1b4c8bd707c07e9636bedbd823ed5cb46f89ad",
      "tree": "5553eec8f0f86f363220a979342d59e3c55eae58",
      "parents": [
        "ac427b22c4fa45936fe94af31a5e0422dd95c152"
      ],
      "author": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Feb 17 14:51:04 2012 +0000"
      },
      "committer": {
        "name": "Stefan Tauner",
        "email": "stefan.tauner@alumni.tuwien.ac.at",
        "time": "Fri Feb 17 14:51:04 2012 +0000"
      },
      "message": "Add support for SFDP (JESD216)\n\nSimilar to modules using the opaque programmer framework (e.g. ICH Hardware\nSequencing) this uses a template struct flashchip element in flashchips.c with\na special probe function that fills the obtained values into that struct.\n\nThis allows yet unknown SPI chips to be supported (read, erase, write) almost\nas if it was already added to flashchips.c.\n\nDocumentation used:\nhttp://www.jedec.org/standards-documents/docs/jesd216 (2011-04)\nW25Q32BV data sheet Revision F (2011-04-01)\nEN25QH16 data sheet Revision F (2011-06-01)\nMX25L6436E data sheet Revision 1.8 (2011-12-26)\n\nTested-by: David Hendricks \u003cdhendrix@google.com\u003e\non W25Q64CV + dediprog\nTested-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\non a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog\n\nThanks also to Michael Karcher for his comments and preliminary review!\n\nCorresponding to flashrom svn r1500.\n\nSigned-off-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "eb0e7fc4f08dcc704565ae07c83878171cc71a44",
      "tree": "e9eb1f6a1701f8bbe8fdabf6bcfad87870e2547a",
      "parents": [
        "a84b0bd6ad4b5ab7220deb799f30515a9eb0d7fc"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Wed Aug 18 15:12:43 2010 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Wed Aug 18 15:12:43 2010 +0000"
      },
      "message": "Add paranoid checks to sb600spi driver\n\nAdd paranoid checks for correct values in essential registers in the SB600/SB700/... SPI driver. If something else changes the values we\nwrote, we will see severe read/write corruption.\nsb600spi will now abort the access and return an error if it detects\nthis sort of corruption.\n\nNote: This corruption can be caused by a few different events:\n- IPMI/BMC/IMC accesses flash\n- Other software accesses flash\nThe nature of flash access (read/write/ID/...) is irrelevant. Each such\naccess will cause corruption for all other accesses happening at the\nsame time.\n\nThanks to Matthias Kretz for testing this patch.\n\nCorresponding to flashrom svn r1145.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Matthias Kretz \u003ckretz@kde.org\u003e\n"
    },
    {
      "commit": "d99b8d3b6e6912a1b09394bc6a03f148fdb8e7ed",
      "tree": "66b3b09a1cdc85bd0dec6f18f9eaab9d9e49c260",
      "parents": [
        "04e18bea9fb28f64825b1c1edd28aeae9cb6919a"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Thu Jul 29 16:32:24 2010 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Thu Jul 29 16:32:24 2010 +0000"
      },
      "message": "Fix bug introduced in AAI code rewrite (r1052)\n\nThe AAI code rewrite in r1052 introduced a bug: The writelen of AAI\ncontinuation is 3 bytes, but the code incorrectly had 6 bytes there.\nThis causes all AAI writes (except the first two bytes of a chip) to\nfail. Thanks to den_m for reporting the bug and for testing the fix.\n\nCorresponding to flashrom svn r1121.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n"
    },
    {
      "commit": "fd7075ae75c04df49f61a7617e772c54e0b4984d",
      "tree": "c95adc0c593268590615032f0d297e7190bcf2a7",
      "parents": [
        "f792c7d4cb43e8c34719e015f20e8049579e34af"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Thu Jul 29 13:09:18 2010 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Thu Jul 29 13:09:18 2010 +0000"
      },
      "message": "Add detailed status register printing and unlocking for all ATMEL AT25* chips\n\nAdd support for Atmel AT25DF081A and AT25DQ161.\n\nSome chips require EWSR before WRSR, others require WREN before WRSR,\nand some support both variants. Add feature_bits to select the correct\nSPI command, and default to EWSR.\n\nCorresponding to flashrom svn r1115.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Steven Rosario\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n"
    },
    {
      "commit": "9c62d11d55a492f59781874cb74ce84f8dde1bfc",
      "tree": "204c545093f263b9187aa9cdc220efba2fb57a72",
      "parents": [
        "8ae500e09dc4c55d0a8e39b6f751ca476afd21c4"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Sun Jun 20 10:41:35 2010 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Sun Jun 20 10:41:35 2010 +0000"
      },
      "message": "Refine SPI AAI support\n\nModernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run\nwithout warnings on ICH/VIA SPI. Add some code to make conversion to\npartial write possible for AAI.\n\nCorresponding to flashrom svn r1052.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n"
    },
    {
      "commit": "dc1cda15d48cdbc7d53e4cf86cf39844e4af2a8b",
      "tree": "f7d7123a8b474227d45bd9f0eae5b819d499b3a8",
      "parents": [
        "80f3d05e7356ec85f9ea27ae2e11245e0b6bb3c6"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Fri May 28 17:07:57 2010 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Fri May 28 17:07:57 2010 +0000"
      },
      "message": "Add support for two-byte RES probes\n\nSome chips implement the RES (0xab) opcode, but they use a non-standard\ntwo byte response instead of the usual one byte response. A two-byte\nresponse has the accuracy of REMS and RDID, so don\u0027t check for REMS/RDID\navailability before running a two-byte RES.\n\nCorresponding to flashrom svn r1017.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n"
    },
    {
      "commit": "5643c0782e5cd8ef19010ed9bba7286386b2b584",
      "tree": "339d115b6865e7c0c3b3330df5f81072fb12803a",
      "parents": [
        "db7c153cdd0eb3de235bfcfac23709c2feef52e1"
      ],
      "author": {
        "name": "Sean Nelson",
        "email": "audiohacked@gmail.com",
        "time": "Tue Jan 19 03:23:07 2010 +0000"
      },
      "committer": {
        "name": "Sean Nelson",
        "email": "audiohacked@gmail.com",
        "time": "Tue Jan 19 03:23:07 2010 +0000"
      },
      "message": "Block eraser conversions and support for Eon EN25B series\n\nConvert chips to block_erasers:\nST_M25PE10\nST_M25PE20\nST_M25PE40\nST_M25PE80\nST_M25PE16\nPMC_25LV010\nPMC_25LV016B\nPMC_25LV020\nPMC_25LV040\nPMC_25LV080B\nPMC_25LV512\nPMC_39F010\nPMC_49FL002\nPMC_49FL004\nSANYO_LE25FW203A\nSPANSION_S25FL016A\n\nAdded spi_block_erase_d7 for PMC chips.\n\nCorresponding to flashrom svn r867.\n\nSigned-off-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "5cca01f3943d888f9ee5f1efcf9faa0269bf8533",
      "tree": "1978ce52ae758b879635c7a8a9c2651f739844f8",
      "parents": [
        "e51ea10a8889544b942d3490bb721f160fe09517"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Tue Nov 24 00:20:03 2009 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Tue Nov 24 00:20:03 2009 +0000"
      },
      "message": "Cleanly validate ICH SPI preopcodes\n\nThe code should work on Linux/*BSD/MacOSX and relies on the serial code\nimplementation in serial.c. Support for additional platforms (Windows)\nwill have to be added to serial.c for this to work. For tests without a\nBus Pirate (or with non-functional serial code) it is possible to\n#define FAKE_COMMUNICATION in buspirate_spi.c.\nThanks to Sean Nelson for the SPI mode settings code. I tweaked it a bit\nto make configuration from a commandline easier should anybody want that\nfeature.\n\nTested-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n\nCorresponding to flashrom svn r772.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\nAcked-by: Sean Nelson \u003caudiohacked@gmail.com\u003e\n"
    },
    {
      "commit": "142e30fcaa1c3a63a1f0baf0b802ef888a0c250b",
      "tree": "c286d89dadacecee2e68b84ce5606467e9ae33e8",
      "parents": [
        "78e4e127129398454813d1552b516638837c423e"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Tue Jul 14 10:26:56 2009 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Tue Jul 14 10:26:56 2009 +0000"
      },
      "message": "Use a distinct return code for SPI commands with unsupported/invalid length\n\nSome drivers support only a few combinations of read/write length and\nreturn error otherwise. Having a distinct return code for this error\nmeans we can handle it in upper layers.\n\nCorresponding to flashrom svn r653.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n"
    },
    {
      "commit": "3e9dbea1ce9c94a879deccc48bd72c60eb4b3454",
      "tree": "507387aa6b99ba2538d054a6662233927750ba19",
      "parents": [
        "b4dcb7188ff557c6722f862a61e806f901c17889"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Wed May 13 11:40:08 2009 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Wed May 13 11:40:08 2009 +0000"
      },
      "message": "There are various reasons why a SPI command can fail\n\nAmong others, I have seen the following problems: - The SPI opcode is\nnot supported by the controller. ICH-style controllers exhibit this if\nSPI config is locked down. - The address in in a prohibited area. This\ncan happen on ICH for any access (BBAR) and for writes in chipset write\nprotected areas. - There is no SPI controller.\n\nIntroduce separate error codes for unsupported opcode and prohibited\naddress.\n\nAdd the ability to adjust REMS and RES addresses to the minium supported\nread address with the help of spi_get_valid_read_addr(). That function\nneeds to call SPI controller specific functions like reading BBAR on\nICH.\n\nCorresponding to flashrom svn r500.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n"
    },
    {
      "commit": "0faf03e6475c6e2b7a695cbe92b3bfc4fe13b5c1",
      "tree": "31d0d6c348dcfb6b75c6a5e647dc50b94a0b51f0",
      "parents": [
        "6a0a25cada03fc6a36a065db18b29ca832288aa6"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Fri Nov 28 23:47:55 2008 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Fri Nov 28 23:47:55 2008 +0000"
      },
      "message": "Declare special commands to support the Atmel AT25F512A\n\nCorresponding to flashrom svn r353 and coreboot v2 svn r3781.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n"
    },
    {
      "commit": "a3f04be761d45aed2f6113eb2a6d08679370f546",
      "tree": "b1e437eb9e184676bc4ca62472bfb103ca4d2196",
      "parents": [
        "7f30022fb0fb62a484514e50d5b3f15157a5885d"
      ],
      "author": {
        "name": "Jason Wang",
        "email": "Qingpei.Wang@amd.com",
        "time": "Fri Nov 28 21:36:51 2008 +0000"
      },
      "committer": {
        "name": "Uwe Hermann",
        "email": "uwe@hermann-uwe.de",
        "time": "Fri Nov 28 21:36:51 2008 +0000"
      },
      "message": "Add support for the AMD/ATI SB600 southbridge SPI functionality\n\nThis has been tested by Uwe Hermann on an RS690/SB600 board.\n\nCorresponding to flashrom svn r351 and coreboot v2 svn r3779.\n\nSigned-off-by: Jason Wang \u003cQingpei.Wang@amd.com\u003e\nReviewed-by: Joe Bao \u003czheng.bao@amd.com\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n"
    },
    {
      "commit": "14e50ac12310eac97f64ee8d6cb17dfb6407259b",
      "tree": "db1512123838cee8ce82f11fb61def54898b073f",
      "parents": [
        "92a54ca0300dd6e0f9773a4313ab489df79020c7"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Fri Nov 28 01:25:00 2008 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Fri Nov 28 01:25:00 2008 +0000"
      },
      "message": "Flashrom already has the following probe functions\n\n- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID\n- probe_spi_res with opcode 0xab, usually 1 byte ID\nWe are missing the following probe function:\n- probe_spi_rems with opcode 0x90, usually 2 bytes ID\n\nRDID provides best specifity (manufacturer, device class and device) and\nRES is supported by quite a few old chips. However, RES only returns one\nbyte and there are multiple flash chips with different sizes on the\nmarket and all of them have the same RES ID.\nREMS is from the same age as RES, but it provides a manufacturer and a\ndevice ID. It is therefore on par with the probing for parallel flash\nchips and specific enough.\n\nThe order in which chips should be detected is as follows:\n1. RDID\n2. REMS\n3. RES\n\nCorresponding to flashrom svn r349 and coreboot v2 svn r3775.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Peter Stuge \u003cpeter@stuge.se\u003e\n"
    },
    {
      "commit": "d54ef6e789712b41cb4190021448f4fcaa729c56",
      "tree": "0fe9eee0b40661b65917d220454c932166d38cfd",
      "parents": [
        "fc4a369669d9a113ae312b0a74874660f8eb5107"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Sat Nov 15 13:55:43 2008 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Sat Nov 15 13:55:43 2008 +0000"
      },
      "message": "The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs\n\nThe AT45 series SPI chips are DataFlash EEPROMs which means they have\nodd (non-power-of-two) sector sizes, but some of the DataFlash chips can\nbe configured or ordered with power-of-two sector sizes.\n\nAdd probe support for the following Atmel SPI chips:\nAT25DF021\nAT25DF041A\nAT25DF081\nAT25DF161\nAT25DF321A\nAT25DF641\nAT25F512B\nAT25FS010\nAT25FS040\nAT26DF041\nAT26DF081A\nAT26DF161\nAT26DF161A\nAT26DF321\nAT26F004\nAT45CS1282\nAT45DB011D\nAT45DB021D\nAT45DB041D\nAT45DB081D\nAT45DB161D\nAT45DB321C\nAT45DB321D\nAT45DB642D\n\nAdd an explanation why the following chips can\u0027t be probed:\nAT45BR3214B\nAT45D011\nAT45D021A\nAT45D041A\nAT45D081A\nAT45D161\nAT45DB011\nAT45DB011B\nAT45DB021A\nAT45DB021B\nAT45DB041A\nAT45DB081A\nAT45DB161\nAT45DB161B\nAT45DB321\nAT45DB321B\nAT45DB642\n\nAdd the ID, but no probing function for this chip:\nAT25F512A\n\nCorresponding to flashrom svn r342 and coreboot v2 svn r3754.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Jesse Brandeburg \u003cjesse.brandeburg@intel.com\u003e\nTested-by: Andriy Gapon \u003cavg@icyb.net.ua\u003e\nAcked-by: Myles Watson \u003cmylesgw@gmail.com\u003e\n"
    },
    {
      "commit": "f83221b6db1a35b559830c01fe40cdb4fa3f5fb2",
      "tree": "83dc53759cd8cca1419c8e1e43dc3e83d15995f2",
      "parents": [
        "6a214163c098f63a2fc3595d69f41b1cab0e64c9"
      ],
      "author": {
        "name": "Peter Stuge",
        "email": "peter@stuge.se",
        "time": "Mon Jul 07 06:38:51 2008 +0000"
      },
      "committer": {
        "name": "Peter Stuge",
        "email": "peter@stuge.se",
        "time": "Mon Jul 07 06:38:51 2008 +0000"
      },
      "message": "Trivial SPI cleanups\n\nWhile writing a new SPI driver I fixed some things in the SPI code:\nAll calls to spi_command() had unneccessary #define duplications, and in some\ncases the read count define could theoretically become harmful because NULL was\npassed for the read buffer. Avoid a crash, should someone change the #defines.\n\nI also noticed that the only caller of spi_page_program() was the it87 driver,\nand spi_page_program() could only call back into the it87 driver. Removed the\nfunction for easier-to-follow code and made it8716f_spi_page_program() static.\nThe ichspi driver\u0027s static page functions are already static.\n\nCorresponding to flashrom svn r302 and coreboot v2 svn r3418.\n\nSigned-off-by: Peter Stuge \u003cpeter@stuge.se\u003e\nAcked-by: Peter Stuge \u003cpeter@stuge.se\u003e\n"
    },
    {
      "commit": "42c54971801dc1cec7c5724b5619e7731126222d",
      "tree": "68c1d560242821885e66578bca46a1e6c68eb36c",
      "parents": [
        "6dc1d3b8dc6bd226bb2530c7af8d109407faa056"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Thu May 15 03:19:49 2008 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Thu May 15 03:19:49 2008 +0000"
      },
      "message": "Add support for the JEDEC RES\n\nAdd support for the JEDEC RES (Read Electronic Signature and Resume from\nPowerdown) SPI command to identify older SPI chips which can\u0027t handle\nJEDEC RDID.\n\nSince RES gives a one-byte identifier which is shared among many\ndifferent vendors and even different sizes, we want to match RES as a\nlast resort if RDID returns 0xff 0xff 0xff.\n\nCorresponding to flashrom svn r235 and coreboot v2 svn r3320.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Peter Stuge \u003cpeter@stuge.se\u003e\n\nThis is a heavily reworked version of a patch by Fredrik Tolf, which was\nSigned-off-by: Fredrik Tolf \u003cfredrik@dolda2000.com\u003e\n"
    },
    {
      "commit": "d6cbf76ee527da983b0405ca41ccd60a14d3d7be",
      "tree": "3a5c3a6dcbfa80443fcec823826f2ac73b021c4d",
      "parents": [
        "228231ff2c43fbdaaae9e83b658dfeb0f2fe84e9"
      ],
      "author": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Tue May 13 14:58:23 2008 +0000"
      },
      "committer": {
        "name": "Carl-Daniel Hailfinger",
        "email": "c-d.hailfinger.devel.2006@gmx.net",
        "time": "Tue May 13 14:58:23 2008 +0000"
      },
      "message": "Move the SPI #defines from spi.c to spi.h\n\nThis patch has no code changes.\n\nCorresponding to flashrom svn r228 and coreboot v2 svn r3302.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Peter Stuge \u003cpeter@stuge.se\u003e\n"
    }
  ]
}