)]}' { "log": [ { "commit": "05790290bfb9999fcde9fc7833882b95c828a40e", "tree": "17a5ae722ca47b10d936568023d88023e1f8d884", "parents": [ "f1411ba8b9a7b7961c59c293e79be1a2feeede95" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 09 17:24:08 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "opaque: Move last bits from chipdrivers.h into chipdrivers/opaque.h\n\nThere are only things related to opaque programmers left.\n\nChange-Id: Iffb702336ccbf9e8b67a2f57e25a5a06ba91b6a9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/448\n" }, { "commit": "3a3533716c10bd9aa5fd7960a916292503bcf3fa", "tree": "2a13a6b1657ae1f703f76d5c5e1b93acfb922a9a", "parents": [ "b72fa1aec4e8729a43302c9057705894740b6eaa" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 08 15:06:51 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "jedec: Use common probing for EN29LV640B\n\nTurns out this is just common probing with respective feature bits\nand `.probe_timing`.\n\nChange-Id: I5bbf23198966c4520e2c344d198cba4e4dcbc49b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/446\n" }, { "commit": "2e94746997b3c46df3b925a4511f34c5f5b81437", "tree": "86f865121240490c8de65884016592be38b6d312", "parents": [ "2cadbe3481ec133b91b33f985f54ed0828559e15" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 07 17:04:59 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "Use bus probing for standard JEDEC and JEDEC_29GL\n\nTo keep things close to as they were, we still run the probing many\ntimes, with a huge amount of different chip parameters and sizes.\n\nThis brings us down to 35 probing runs for 159 chips. And there is\nstill room for improvement: It\u0027s likely that chips respond already\nwhen longer delays are used. Also, many chips actually ignore addi-\ntional address bits when decoding commands (i.e. bits above a 0x555\npattern are simply ignored and we actually don\u0027t need the masking).\nMany (if not all) parallel flash chips also don\u0027t care about higher\naddress bits when reading the identification, so we might only have\nto probe for them with a single chip size.\n\nFor now, we keep the set of probing parameters close to what we did\nbefore. For power-of-two chip sizes from 64KiB to 1MiB, we run with\nthe most common parameters. 7 more parameter sets are used for more\nunusual cases. And the 29GL parts are probed for the three sizes we\nhave in our database: 4MiB, 8MiB, 16MiB.\n\nA note on the 29GL probing: All the chips have status UNTESTED, and\nmost if not all are x16 parts that need the addresses shifted (what\nwe don\u0027t do ATM). Overall it looks like standard jedec probing with\na short reset sequence. However, continuations of the device ID are\nalways 2 bytes long, at a different offset (0x0E) and prefixed with\n0x7E.\n\nChange-Id: If6ece7edc2291cae4824e5bcc2f83fd8aaef296e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/444\n" }, { "commit": "2cadbe3481ec133b91b33f985f54ed0828559e15", "tree": "e8b65ba8ebbb69732c24658d580621d6fb5550f4", "parents": [ "3a2a4d5af905b0cc0fae1010cc7bae51e324c96f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 05 18:34:57 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "Use bus probing for W29EE011\n\nThis peculiar probing function is only used for a single chip in our\ndatabase. Hence, we run it only for its 128KiB chip size. Because it\ncan cause trouble with other chips, it gets a lower priority, and is\nonly called if no higher-priority probing function returned any data.\n\nChange-Id: I90fb5aaea73e610a53b183383ebfe76a748ddffd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/443\n" }, { "commit": "3a2a4d5af905b0cc0fae1010cc7bae51e324c96f", "tree": "28578c9a46d361e4eedc3cf69c9d92c416445daf", "parents": [ "dae9022046be147c87c32d56678053b2f85cdb1a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 01 12:15:23 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "Use bus probing for 82802AB\n\nWe probe for chip sizes from 256KiB to 2MiB, with and without shifted\naddresses (for x16 chips). That makes 8 probing calls that currently\ncover 28 chips in our database.\n\nChange-Id: I3dd753efb3152a8a103ca88b941802b815a8180a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/442\n" }, { "commit": "10337f785ebd621b544d7f5929bb1050eb975431", "tree": "2efbd04d3f00fa7a71a46cd68e61ee5a142a4d1c", "parents": [ "dd6e07ab3ab12346ab68f9e93f725d651a90964d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 04 19:57:27 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "memory_bus: Move related declarations into new `chipdrivers/memory_bus.h`\n\nChange-Id: I2bef65de77860d049ec3d9938ae777c5f929c258\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/438\n" }, { "commit": "4374ba1e696c9f0d18ee86188f0a389634fd2c94", "tree": "8e6160077021cc48ef230aceba101873fc3eadcd", "parents": [ "899d36af94fca6650964d88ae40ddc5c8734503c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 06 22:25:27 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "flashchips: Set 1us (150ns) probe timining for SST49LF080A\n\nAccording to its datasheet it\u0027s the same 150ns that its siblings have.\n\nChange-Id: Ica9b2afaad4438885ab6537a1642bac48a4933e1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/434\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "899d36af94fca6650964d88ae40ddc5c8734503c", "tree": "86d36bfd89e8abd8a958c942659f8bb698cd0473", "parents": [ "0c39ddbd42d86e1b4672d8ffc9d1f961ed1a53d9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 06 22:22:22 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "flashchips: Allow long reset/exit sequence for MBM29LV160[BT]E\n\nChange-Id: Ibaa8edec2414a21fe5e3a92389480aa3bbec46c1\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/433\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "0c39ddbd42d86e1b4672d8ffc9d1f961ed1a53d9", "tree": "0451059810d70eeefc00b14ff70e8ccb7132012d", "parents": [ "be42cf24728907ace7db5c572b097288485dca5c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Mar 06 22:17:33 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 28 09:29:37 2026 +0000" }, "message": "flashchips: Drop spurious address masks from parallel chips\n\nThese chip entries are all untested. According to their datasheets,\nthey all ignore additional address bits when receiving commands. In\ncase of x16 chips (w/ address shift), the 2AA masks were wrong any-\nway, as we mask after the shifting.\n\nChange-Id: Ie7ae3c78353cc9d01bc627209481cb5d8f7afffb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/432\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\n" }, { "commit": "f3113acc7b51a1707764f90c0d423e79b59b7543", "tree": "4905c73004745c1c76d31f1b68db49b53b5d4ef0", "parents": [ "4af02fe6355beb2ca7eac59a5c35856e1b4084d5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 21 12:50:19 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "edi: Turn edi_chip_probe() into a bus probing function\n\nLet our common bus-probing infrastructure handle the ID comparison.\nThis also makes the `flashchips\u0027 entry (KB9012) an actual chip entry\nthat carries its identification.\n\nChange-Id: I9533ece2b1337281ea70cb2e3be7a74353a4a758\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/424\n" }, { "commit": "4af02fe6355beb2ca7eac59a5c35856e1b4084d5", "tree": "74632469db4c140b3a60a8b87a487a15607d5b19", "parents": [ "a94ce1cf4713266d4d6f9e21c5048d70c3c21d51" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 21 12:29:26 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "edi: Split preparation/finalization out of edi_probe_kb9012()\n\nThis turns edi_probe_kb9012() into a pure probing function. To avoid\nturning EDI off after probing, register edi_finish() only after full\npreparation.\n\nChange-Id: Icc342b8ab109d5621d8b65c79cecf71a44bea4bd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/423\n" }, { "commit": "6bd4f10ed9f24c1ac60f18598edef0b45b4885c3", "tree": "4e97539643c3599f8ff5577a462387f406dd9d99", "parents": [ "2e0a0031139fe9aa4e7ad3259c6a864112b06f11" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 22 23:28:13 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "edi: Move EDI related things into new chipdrivers/edi.h\n\nChange-Id: I592449693647587b5817614b6c6cac07e8009a89\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/421\n" }, { "commit": "2e0a0031139fe9aa4e7ad3259c6a864112b06f11", "tree": "453b9a47b06c404e7572945e6c23dc0aaa6c1c1c", "parents": [ "b9e47cc321b4924e19d1a556462a8cd94361d1ea" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 07 22:32:27 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Use bus probing for SFDP\n\nOnly probe for the SFDP signature and split the actual SFDP parsing\ninto a chip preparation function.\n\nChange-Id: I182d0a386bb2fd11951a1c9f2f965ce68ff57cf0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/427\n" }, { "commit": "b9e47cc321b4924e19d1a556462a8cd94361d1ea", "tree": "22676291abc0c0530863684f4f002f04038b4522", "parents": [ "ac13873e102208d4a78d9c9e541a3eab29fbb1c6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 21 13:25:17 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Use bus probing for ST95 RDID\n\nAs the SPI instruction used for probing conflicts with AT45DB chips,\nlet it only run at priority `1\u0027, when no flash chip was detected.\n\nChange-Id: I61db0d6fa7be81d120bc84213c358498019dc52d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/420\n" }, { "commit": "64f53a1c9f5bd11b8b35cff757ac6d4aa37b0c59", "tree": "d64e96af9998a13ba3e22eb1cce5a65d434b7be2", "parents": [ "4312576b49dc77b53d5ebfa6686e3072c9368ea0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 15 16:04:29 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Use bus probing for REMS, RES and AT25F\n\nChange-Id: Ic5d2a5283c5fb5e52c58c0b5937922371f56249f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/417\n" }, { "commit": "4312576b49dc77b53d5ebfa6686e3072c9368ea0", "tree": "5802bfef2623095f5fdccd98df15bdabac35f785", "parents": [ "fbc41d2a932ede9c02aa7803472c31f39ec200f2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 15:56:16 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Use bus probing for RDID\n\nWe put 3 and 4 byte RDID into a single function. Only if we can\u0027t\nread 4 bytes, we try again with 3. There are no conflicts because\nthe only RDID4 manufacturer ID contains the 0x7f prefix, hence it\ncan\u0027t match any 3-byte ID.\n\nChange-Id: I5d35bc30255aae66da35d58431628512e50b39f0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74900\n" }, { "commit": "fbc41d2a932ede9c02aa7803472c31f39ec200f2", "tree": "8b72b78abfd99bf8737b90cc2fece11f2dbe93d3", "parents": [ "966dc9b776c2897d1245937639ab41fc834d7cb9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 22 23:04:01 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "spi: Move SPI related things into new chipdrivers/spi.h\n\nA few things that rely heavily on `flash.h` are moved there instead:\n* function signatures containing `erasefunc_t`,\n* the inline default_wrsr_target() that needs to know struct flashctx.\n\nThis allows to keep the new header file free of a transitive `flash.h`\ninclude.\n\nChange-Id: Ib215821feeb822ea3fc11bf9f48c0328f9a394d4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/416\n" }, { "commit": "966dc9b776c2897d1245937639ab41fc834d7cb9", "tree": "517dabeaf5bf7e79fbbdbf988cd2ef7734b7b0d9", "parents": [ "af9d738a66a885f19fdb0659455834f114d9d1e0" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 07 21:59:15 2026 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 22 09:47:02 2026 +0000" }, "message": "Use new probing path for chips w/o IDs\n\nWe used to have a probe_noop() that simply assumed a chip is there\nbut wasn\u0027t called by default. Instead we can handle this case spe-\ncifically in the new probing path.\n\nChange-Id: I633c55f8de3a36c4de96f79fd938f58aa39b5bf9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/426\n" }, { "commit": "11136c210e382258a72df44ffe625260a6394a45", "tree": "376f66e9e7a826dcf13f833e90291db7663205a4", "parents": [ "610c1aad71bfa118c4f49ac01761f586b8dede69" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 12:00:09 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 15 14:27:20 2026 +0000" }, "message": "flashchips: Add a type enum to the chip identification\n\nWe used to imply what kind of ID (e.g. RES, REMS, RDID) a chip entry\nprovides, based on the given probing function. This works well as long\nas we call the respective probing function for every single chip entry.\nWith our ever growing chip database, however, this slows probing signi-\nficantly down. Especially with external programmers with a long command\nround-trip.\n\nWith the type of identification information stored in the chip entries\nexplicitly, we\u0027ll be able to implement bus-specific probing functions.\nThese would be called only once and their results would be used to look\na matching chip up in the chip database. Instead of looking for every\npossible chip on the buses, we can turn it around and search for the\nactually present chips in the database.\n\nChange-Id: Ie658ebf58f21c8994b9b66f7683f9490e8d12267\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74898\n" }, { "commit": "32f1ea8df501b41362058bb699a7ea96482e4db3", "tree": "294501d43632515901c1262e6e2b294d75ba3d1a", "parents": [ "b89c4524d978d3104ce3346894503e8d7b3fce51" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 01 15:11:48 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Feb 14 22:42:55 2026 +0000" }, "message": "at45db: Use .prepare_access hook for non-power-of-2 preparations\n\nWe performed some additional preparations in probe_spi_at45db(). Turn\nit into a .prepare_access hook, spi_prepare_at45db(), so we can use\na pure probing function.\n\nChange-Id: I75570078301b9a06a229543f44714a0941457a5a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74895\n" }, { "commit": "e060018655f802896dc226832d25e223102889c8", "tree": "ffb01d5b4cabd734e6676fb48b4e7b87f35a7828", "parents": [ "ff9526b8039e69310d4af13d5d7665b4002d8450" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 01 12:29:28 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 03 16:16:09 2025 +0000" }, "message": "flashchips: Explicitly zero-initialize in .qpi_read_params\n\nThe last number was left out on purpose for GD25LE255E, because the\nsetting is reserved. Clang is picky about this case, though, due to\n`-Wmissing-field-initializers\u0027.\n\nChange-Id: I0a6915d37a4413eecc33ac88d2e20ad6a327cd38\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/332\n" }, { "commit": "5a72cfb13afacb69a991199d568a5b7e253c6d2a", "tree": "8a70766a62e2181fdaabadc15ae9011e72c5592e", "parents": [ "284d55b9554f14086fdfa94fedac1313a7da3457" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 26 23:47:14 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 03 16:16:09 2025 +0000" }, "message": "flashchips: Fix block-protection bits for 4BA Puya chips\n\nLike many other 4BA chips with \u003e\u003d 32MiB flash space, these chips use\na fourth BP bit to encode the size of the protected area. The TB bit\ntakes the SEC bit\u0027s place, which is sacrificed.\n\nChange-Id: Iac2c817e8650d4d57ff94d41eba49f84cbb66d7d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/329\n" }, { "commit": "284d55b9554f14086fdfa94fedac1313a7da3457", "tree": "108290ef32568b61cc112e5c9dd6f08926a01e6f", "parents": [ "37e07a86a652467c14afaaff08af17da019f2166" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 26 23:37:49 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 03 16:16:09 2025 +0000" }, "message": "flashchips: Add WPS bit description for GD25Q128C\n\nThis seems to be the only GigaDevice chip in our database with\na WPS bit in a regular status register.\n\nChange-Id: If08aa4c4f90291e9b8b975565b5fa808773442bb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/328\n" }, { "commit": "37e07a86a652467c14afaaff08af17da019f2166", "tree": "8520d91487990da1223ffba9eb1f4714aee0dabb", "parents": [ "3646b18f69a3461bf9353b0dd909fadfdc32f147" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 26 23:26:59 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 03 16:16:09 2025 +0000" }, "message": "flashchips: Add missing QE bit descriptions\n\nWinbond and XTX chips have QE bits. These were missed when adding\nquad-i/o support initially. Found by checking for irregularities\nin chips with quad-i/o support but no `.qe` entry.\n\nChange-Id: Id47e9ac9eb487140340349895f771adbe42c87fd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/327\n" }, { "commit": "3646b18f69a3461bf9353b0dd909fadfdc32f147", "tree": "6ad6b9cf08961d0b5690e2791f2a16f7b4e3643c", "parents": [ "d4eb532cf1f6370f06761bb89786831587bec117" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 23:44:37 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 27 20:58:30 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25LF128E 166MHz, 1.8V part\n\nThis one has dummy-cycles configuration bits that control the\nquad-i/o fast read command. Otherwise it supports the standard\nset of QPI commands and all usual block-protection bits except\nWPS.\n\nDatasheet used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00632-GD25LF128E-Rev1.3.pdf\n\nChange-Id: Id43ca44f66002f3038460be2bbf595de31956a51\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/308\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d4eb532cf1f6370f06761bb89786831587bec117", "tree": "6ed282807c1d1488963ddda99a4cc509e512ebc8", "parents": [ "38d037fc5bf75068c608ef24af5dc9bd26456263" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 23:26:04 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 27 20:58:30 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25LF80E..GD25LF64E 166MHz, 1.8V parts\n\nThese chips are supposed to have full QPI support and all known block-\nprotection features except WPS. Only one quirk was found in the data-\nsheets: the fast-read quad-i/o command uses 10 dummy cycles instead of\nthe usual 6.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240914/DS-00678-GD25LF80E-Rev1.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00677-GD25LF16E-Rev1.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00676-GD25LF32E-Rev1.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-00636-GD25LF64E-Rev1.4.pdf\n\nChange-Id: I2b57bfdd38f354867aa242d040b17e860c8734f4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/307\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "38d037fc5bf75068c608ef24af5dc9bd26456263", "tree": "dd8ed6fb6169d4a79e7a9674d58010916497b8b1", "parents": [ "1da029331d6dade08ed181f8b2c87d3cf02a0489" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 18:25:55 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 27 20:58:30 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25LB512MF..GD55LB02GF 1.8V parts\n\nAgain, very similar to their 256Mbit counter parts. There are non-\nvolatile dummy-cycle bits that control DIO and QIO commands in the\nSPI mode, hence disable those. QPI works with a set-read-parameters\ncommand, so shouldn\u0027t be affected.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-01012-GD25LB512MF-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-01017-GD25LR512MF-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-01013-GD55LB01GF-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-01015-GD55LB02GF-Rev1.1-773.pdf\n\nChange-Id: I5d81bcec3e7c5e4419dceb0fbf2ff60c484decf6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/306\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1da029331d6dade08ed181f8b2c87d3cf02a0489", "tree": "7a28ee6f88faf70544015d991e1153e58822aa2b", "parents": [ "6d728e6e148d8e34fccf413849f3eebf79a9965f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 17:56:39 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 27 20:58:30 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25LB512ME..GD55LB02GE 1.8V parts\n\nThe GD25LB512ME shares the ID with GD25LR512ME. All those E versions\nlook much like the 256Mbit GD25LB256E. Copy this and update the sizes.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00580-GD25LB512ME-Rev1.5.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00621-GD25LR512ME-Rev1.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-00572-GD55LB01GE-Rev1.4.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-00637-GD55LB02GE-Rev1.4.pdf\n\nChange-Id: Ic3ba2a1a7507804f6de611e24606834eb26f19ec\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/305\n" }, { "commit": "6d728e6e148d8e34fccf413849f3eebf79a9965f", "tree": "9479940aa2fe9c9fbdb92c4398b44f6eaaf26b20", "parents": [ "493a4e05a9feae8ace45e25733d25094b024a217" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 13:07:52 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 27 20:58:30 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25B512MF..GD55B02GF 3.3V parts\n\nThese F versions seem more regular. Except for a SEC bit, complete\nblock-protection support, and a complete 4BA/QPI command set. How-\never, they also have non-volatile dummy-cycle bits that affect DIO\nand QIO commands in SPI mode.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-00975-GD25B512MF-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-01005-GD25R512MF-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-00979-GD55B01GF-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-00980-GD55B02GF-Rev1.2.pdf\n\nChange-Id: Ia31d3969d5db5ae39dad2d6463456dc7d381ed73\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/300\n" }, { "commit": "493a4e05a9feae8ace45e25733d25094b024a217", "tree": "d7ba157867be69488c212dcc7549ed1271272bf4", "parents": [ "648dfdc9272f02aaca0217fcdab542a10f45476e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 27 15:15:26 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Feb 27 20:58:30 2025 +0000" }, "message": "flashchips: Update and split GD25Q256D entry\n\nAll these chips support volatile status-register writes. While the\ncommands used by flashprog all seem the same, newer versions with\nthe same ID differ in their status-register layout / features. So\nwe add redundant entries.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00285-GD25Q256D-Rev2.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00406-GD25R256D-Rev1.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00327-GD25B256D-Rev1.7.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00398-GD25Q257D-Rev2.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00446-GD25B257D-Rev1.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00526-GD25Q256E-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00750-GD25R256E-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00658-GD25B256E-Rev1.1.pdf\n\nChange-Id: Iee905ab0d72324a0059505713428555308f90207\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/298\n" }, { "commit": "c90d6c425094d39c1bc1114c64e2560acf073412", "tree": "b66c1e54ebd36007afebb90db1b7a8e0d406ff8a", "parents": [ "ee8cf1c9c6218681f78193ba29c890bf9b7ba30a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 02 23:37:59 2025 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 17:23:14 2025 +0000" }, "message": "flashchips: Add some 25LC series EEPROMs\n\nChange-Id: Iff02282cc1b9e76ce681467fb4b228a7f078b06f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/316\nReviewed-by: ftr4 ftr4 \u003cftr4@sharklasers.com\u003e\n" }, { "commit": "06fbccc61ea5cc8410cb795554dffcfdda111139", "tree": "18bea04deb690c8cad0ff1a77ddadbe1147c5bae", "parents": [ "bc001daac6232df01eb4c20e5b701553bcd22ca5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 17:36:28 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25LB256E 1.8V part\n\nThis chip has WPS and DC bits in unsupported configuration registers.\nHence we can\u0027t support QPI and block protection for now.\n\nDatasheet used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00513-GD25LB256E-Rev2.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00573-GD25LR256E-Rev1.6.pdf\n\nChange-Id: I0dab32efab33d34a4c29ca84a5e1e1fe0b408e07\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/304\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "bc001daac6232df01eb4c20e5b701553bcd22ca5", "tree": "d855b3746bce72cb0ff6de98506c687c660ec46b", "parents": [ "7d0f556db8e793df25f54504c6ebfccbcf62f292" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 17:11:56 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add some GigaDevice GD25L*256 1.8V parts\n\nHere\u0027s a bunch of chips that all share the same ID. They differ however\nin their block-protection support (which is where we split them), their\nsupport for native 4BA commands, and their logic to configure dummy cy-\ncles in SPI mode.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00301-GD25LQ256D-Rev2.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00282-GD25LE256D-Rev1.7.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00314-GD25LB256D-Rev1.4.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-00562-GD25LQ255E-Rev1.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-01085-GD25LQ256H-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-01113-GD25LE256H-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-00978-GD25LB256F-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00619-GD25LE255E-Rev1.2.pdf\n\nChange-Id: Id995c53f371c9b83dabe5fb6f881954a7e7f4f59\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/303\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "7d0f556db8e793df25f54504c6ebfccbcf62f292", "tree": "424f9ca6daba9a658f4a721139221f016a423e3f", "parents": [ "7f8c12d63d214bfd2b3ba841a3e3633ab82d825d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 15:06:22 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Update GigaDevice 1.8V family up to GD25LQ128\n\nThese chips all are supposed to support volatile status-register writes\nand feature the most usual block-protection bits. The 1.695V limit looks\ncertainly like a typo. All datasheets found start at 1.65V.\n\nDatasheets used:\nhttps://treetoptech.com/Resources/Datasheets/GD25LQ32C_Rev1.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00230-GD25LQ32D-Rev2.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240902/DS-00543-GD25LQ32E-Rev1.6.pdf\nhttps://www.mouser.com/datasheet/2/870/gd25lq64c_rev3_4_20190615-2486443.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-00593-GD25LQ64E-Rev1.4.pdf\nhttps://www.tme.com/Document/3677f0b602f733a6800806f5bd7a79f9/gd25lq128c.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00291-GD25LQ128D-Rev1.9.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240729/DS-00533-GD25LQ128E-Rev1.2.pdf\n\nChange-Id: I581c3936fbae43f13b01ebf01bf94e68c3150efd\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/302\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "7f8c12d63d214bfd2b3ba841a3e3633ab82d825d", "tree": "3b0580d5fe3e86efd8381a99d638022aea639990", "parents": [ "565471ce44b21aa39698b0cd876020b9dbacd690" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 14:24:14 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25LQ20, update family up to GD25LQ16\n\nThey all are supposed to support volatile status-register writes and\nfeature the most usual block-protection bits. The 1.695V limit looks\ncertainly like a typo. All datasheets found start at 1.65V.\n\nDatasheets used:\nhttps://device.report/m/0dd9581d418568153f88153cd3bd298f85f83fba817fc6b242405e98002f7c44.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00347-GD25LQ20C-Rev1.5.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00785-GD25LQ20E-Rev1.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00663-GD25LQ40E-Rev1.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00405-GD25LQ80C-Rev1.9.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00583-GD25LQ80E-Rev1.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00289-GD25LQ16C-Rev2.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240902/DS-00576-GD25LQ16E-Rev1.4.pdf\n\nChange-Id: I23b3b199d9c6fd7b42de468cbe8b3945774f15e8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/301\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "565471ce44b21aa39698b0cd876020b9dbacd690", "tree": "aee9b5c6f67060e8b580fe44d231287794142ae6", "parents": [ "6ee2f8958e20c30d52758d37a41f8f043345d5ff" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Nov 08 13:07:52 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add GigaDevice GD25B512ME..GD55B02GE 3.3V parts\n\nThese E versions have different, peculiar IDs (0x47 prefix) and\ndon\u0027t support dual-output/-io commands. They have special non-\nvolatile dummy-cycle registers, hence we don\u0027t support QPI and\nblock-protection for now.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230321/DS-00649-GD25B512ME-Rev1.6.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00742-GD25R512ME-Rev1.2.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230321/DS-00650-GD55B01GE-Rev1.4.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230321/DS-00651-GD55B02GE-Rev1.4.pdf\n\nChange-Id: Iffbb5b53383373a5bf677742e2730deaf486883d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/299\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "6ee2f8958e20c30d52758d37a41f8f043345d5ff", "tree": "4564611b4980dbfea1d0bfde6e439e66a6e07cbe", "parents": [ "c230c69c7d4c8403859c4735241158624eade964" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 27 12:15:50 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Update GigaDevice GD25Q/B/R 128Mbit, 3.3V parts\n\nRename and move the GD25B128B/GD25Q128B entry so that it lives closer to\nthe other similar chips (the B version is just a Q with fixed QE\u003d1, thus\nsort it by Q). All the other, newer chips support volatile status regis-\nter writes, however differ in QIO/QPI support. In particular, the newest\nchips have a non-volatile dummy-cycle configuration bit, which we do not\nsupport at the moment.\n\nDatasheets used:\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00319-GD25R127D-Rev1.4.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00277-GD25B127D-Rev1.5.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00480-GD25Q128E-Rev1.4.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-01121-GD25Q128H-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20241211/DS-00751-GD25R128E-Rev1.0.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240902/DS-00594-GD25B128E-Rev1.1.pdf\nhttps://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240902/DS-01137-GD25B128H-Rev1.1.pdf\n\nChange-Id: If2893e59e73d06ecc542c9eb2bb429f2c4e469b9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/297\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c230c69c7d4c8403859c4735241158624eade964", "tree": "59154a1fc4d6d3a1295bf176d43ed4a425c43c96", "parents": [ "06e0264aa076bb9359274692850bf9010a1fe5c7" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 26 01:16:23 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add remaining Puya PY25Q..H 3.3V parts\n\nThe remaining chips use 32-bit addresses (4BA). They seem to support\nthe maximum of fast-read commands, also in QPI/4BA mode.\n\nDatasheets used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q256HB_Datasheet_V1.3.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25R256HB_Datasheet_V1.0.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25F256HB_Datasheet_V1.2.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q512HB_Datasheet_V1.2.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25F512HB_Datasheet_V1.2.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q01GHB_Datasheet_V1.2.pdf\n\nChange-Id: I2ace2734d9dcf0920fb12f607d57fc419db8563e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/296\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "06e0264aa076bb9359274692850bf9010a1fe5c7", "tree": "c72b5d6086fe5de5c64730bdcc144521c7099d58", "parents": [ "fe21b43203c08f597c1295dba556323e63b3f209" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Oct 26 00:46:11 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Puya PY25Q..H family up to PY25Q128H\n\nThese are all the 3.3V parts of the family with only 24-bit\naddresses (3BA). First two (PY25Q40HB, PY25Q80HB) don\u0027t have\na configuration register and no WPS bit. From PY25Q64HA on,\nthe voltage range starts from 2.7V (instead of the 2.3V they\nhad before). There are versions with fixed quad-enable bits.\nAlas, they use different IDs, so we need duplicate database\nentries again.\n\nDatasheets used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q80HB_Datasheet_V1.7.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q16HB_Datasheet_V1.6.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q32HB_Datasheet_V1.7.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q64HA_Datasheet_V1.9.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25F64HA_Datasheet_V1.1.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25Q128HA_Datasheet_V2.0.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25R128HA_Datasheet_V1.0.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25F128HA_Datasheet_V1.2.pdf\n\nChange-Id: I9f97e686604cf722af36c799dc0c5c1e7e942a26\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/295\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "fe21b43203c08f597c1295dba556323e63b3f209", "tree": "05161bf0efd4ca85f8483a92d8d014e457332c67", "parents": [ "1c5d8296f9997e6b773352688fce59c24c1aafd5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 25 23:51:05 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add remaining P25Q..H family 3.3V chips\n\nThey all support QPI, and WPS for individual sector protection.\nHowever, the original P25Q32H and P25Q64H have a different de-\nfault setting for the dummy cycles in QPI mode. Hence, we need\nduplicate database entries once more.\n\nDatasheets used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q32H_Datasheet_V1.4.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q32SH_Datasheet_V1.9.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q64H_Datasheet_V1.4.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q64SH_Datasheet_V1.5.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q128H_Datasheet_V1.6.pdf\n\nChange-Id: I700747a6bc1762f113846aa62f55681fa2c8cfbb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/294\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1c5d8296f9997e6b773352688fce59c24c1aafd5", "tree": "f1ac20fa75e0d2198f7ef0f132d136b89201d751", "parents": [ "b0cae5e30ef780f73b89b8c4ff43c651a3612698" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 25 23:21:02 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Puya P25Q40SH, P25Q80SH, P25Q16SH 3.3V parts\n\nThese are updated versions of the original `H\u0027 chips. They have\na configuration register that is read/written like a third sta-\ntus register, also support QPI, and have a WPS bit for indivi-\ndual sector protection. Because of the WPS bit, they need their\nown database entries, even though they share the old IDs.\n\nDatasheets used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q40SH_Datasheet_V1.9.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q80SH_Datasheet_V1.5.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q16SH_Datasheet_V1.8.pdf\n\nChange-Id: I203bec24b8f4028f50388fb79350d0bf388f404d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/293\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "b0cae5e30ef780f73b89b8c4ff43c651a3612698", "tree": "6321ef6d3dbe4140a4094bb63f26fe66dd26d6b3", "parents": [ "b09136b0971913cf7f984355c1005f65575aba44" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 25 23:03:40 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Puya P25Q06H, P25Q11H, P25Q21H 3.3V parts\n\nThese look like an update to the original quad-i/o chips. They\nhave a configuration register that is read/written like a third\nstatus register. Otherwise, they seem very much compatible, but\nhave different IDs.\n\nDatasheet used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q21H_11H_06H_Datasheet_V2.1.pdf\n\nChange-Id: I984c574bcfd7275a2234c1db13935c01d12fab72\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/292\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "b09136b0971913cf7f984355c1005f65575aba44", "tree": "c11416105bf9ff3bb8a8a8b2a1ade79f9e63278c", "parents": [ "ed8b82c17e285de43437325fe7c402186719da8c" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 25 22:52:30 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Puya P25Q05..16H 3.3V parts\n\nAll quad-i/o chips with block-protection similar to Winbond. One\nspecialty is a page-erase operation. At the upper end (P25Q08H,\nP25Q16H), they have a configuration register that is read like a\nthird status register however written like a second (31h, accor-\nding to the datasheets).\n\nDatasheets used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q40H_20H_10H_05H_Datasheet_V2.0.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q80H_Datasheet_V1.7.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q16H_Datasheet_V2.1.pdf\n\nChange-Id: I8ca43d19603cd11fd9cf06d2afc930b1096548d3\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/291\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "ed8b82c17e285de43437325fe7c402186719da8c", "tree": "e252a99cb8978e5fc27eda846dc8c92de9058024", "parents": [ "4a351349eb0e2156adc06cb628f4db64d7857d40" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 22 00:12:03 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Fudan FM25Q128 3.3V part\n\nThis chip has non-volatile DC bits that control the number of dummy\ncycles for all fast-read commands in all modes. As we don\u0027t check\nsuch bits, we don\u0027t enable any fast reads for now. Otherwise it\nlooks well featured. Block protection seems to follow Winbonds\nscheme, however without SEC and SRL bits.\n\nDatasheet used:\nhttp://eng.fmsh.com/nvm/FM25Q128_ds_eng.pdf\n\nChange-Id: I9cda2fdbc13c20eda999555d09c9a847d0192536\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/290\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4a351349eb0e2156adc06cb628f4db64d7857d40", "tree": "9a58cfe7e2eb88a4417b96c0194e042a99e782aa", "parents": [ "7f7bffa8b4c71d0cf652d94c1386284cdd5a012a" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue Oct 22 00:03:52 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Fudan FM25Q08A 3.3V part\n\nThis chip is almost identical to the older FM25Q08, however\nthe CMP bit is at a different offset. /o\\\n\nDatasheet used:\nhttp://eng.fmsh.com/nvm/FM25Q08A_ds_eng.pdf\n\nChange-Id: I703487c24491d0be1c90579af798bd5c7457148a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/289\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "7f7bffa8b4c71d0cf652d94c1386284cdd5a012a", "tree": "01c190da882dd96fd5563396a8dba41039ae8ba8", "parents": [ "c591518dca2c097d907787858d177707158bc10e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 21 23:57:11 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Fudan FM25Q64, update FM25Q08..Q32\n\nFor all bits that matter to us, these chips seem to have the same\nstatus-register layout. The FM25Q64 differs in a few bits that are\nout-of-scope, and additionally supports a WRSR2.\n\nDatasheets used:\nhttp://eng.fmsh.com/nvm/FM25Q08_ds_eng.pdf\nhttp://eng.fmsh.com/nvm/FM25Q16_ds_eng.pdf\nhttp://eng.fmsh.com/nvm/FM25Q32_ds_eng.pdf\nhttp://eng.fmsh.com/nvm/FM25Q64_ds_eng.pdf\n\nChange-Id: I820ed60366d19ab4d87f8c02b4018ffb5591ca5f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/288\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c591518dca2c097d907787858d177707158bc10e", "tree": "0bdc1e5ece5d1fc5935c50f845a82a928723ea71", "parents": [ "fea6e16e177fc7a9fd5acd75f812272bcadab163" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 21 23:40:10 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Fudan FM25Q02/Q04 3.3V parts\n\nThese smallest two in the series seem to have the same status-\nregister layout. They look almost feature-complete, with only\na SEC-bit missing.\n\nDatasheets used:\nhttp://eng.fmsh.com/nvm/FM25Q02_ds_eng.pdf\nhttp://eng.fmsh.com/nvm/FM25Q04_ds_eng.pdf\n\nChange-Id: Ic267ddd2b33b63e72ad923f2bbe0af29aaa6bf93\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/287\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "fea6e16e177fc7a9fd5acd75f812272bcadab163", "tree": "1a00a179b4076d6b6e885f47547b439c5c87b64d", "parents": [ "56d727e3829923c01b21d4f8d2a281acbb2c83bf" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 23:11:57 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Winbond W25Q16JV_M (DTR version)\n\nFully featured 3.3V version of Winbond\u0027s 16Mbit chip.\n\nDatasheet used:\nhttps://www.winbond.com/resource-files/w25q16jv_dtr%20reve%2002092018%20plus.pdf\n\nChange-Id: I3150b4690c73c1118b6819b83b9dfab55ddf3c8f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/286\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "56d727e3829923c01b21d4f8d2a281acbb2c83bf", "tree": "3200a071d02f9f5726da294a9577d70d5c2a8570", "parents": [ "c64a80362eabce9bbdc44c79b9d2fbd1e77389c2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 22:46:12 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add newer gen. XTX Tech. XT25F..F 3.3V parts\n\nThese F versions don\u0027t support QPI but have a 3rd status register.\nThere are non-volatile DC bits, that control the number of dummy\ncycles for dual- and quad-i/o reads. As we don\u0027t check such bits,\nwe only enable dual- and quad-output commands for now.\n\nDatasheets used:\nhttps://en.xtxtech.com/download/?AId\u003d516\nhttps://en.xtxtech.com/download/?AId\u003d257\nhttps://en.xtxtech.com/download/?AId\u003d450\nhttps://en.xtxtech.com/download/?AId\u003d454\nhttps://en.xtxtech.com/download/?AId\u003d531\n\nChange-Id: Icc187d835a65357a72854d0a04c17e9f54beaee9\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/285\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c64a80362eabce9bbdc44c79b9d2fbd1e77389c2", "tree": "14a32474129ea9057efa2c3c471b6267edad21ca", "parents": [ "46e42096032e85265b0740b47c86f4975cf365ef" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 19:14:19 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add XTX Tech. XT25F..B 3.3V family\n\nThese are old versions of the 3.3V family, that don\u0027t seem to be\nmanufactured anymore. Except for the smallest 16Mbit chip, they\nhave QPI support which newer versions lack. The block-protection\nseems to follow Winbond\u0027s model.\n\nDatasheets used:\nhttps://xonstorage.blob.core.windows.net/pdf/xtx_xt25f16bsoigu_xonjuly20_20_link.pdf\nhttps://www.lcsc.com/datasheet/lcsc_datasheet_2410121518_XTX-XT25F32BSOIGU-S_C558851.pdf\nhttps://www.lcsc.com/datasheet/lcsc_datasheet_2411220126_XTX-XT25F64BSSIGU_C3202692.pdf\nhttps://www.lcsc.com/datasheet/lcsc_datasheet_2410121527_XTX-XT25F128BSSIGU_C558845.pdf\n\nChange-Id: Ifc5607674fabf1466155d821e7d5e88886d3b21b\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/284\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "46e42096032e85265b0740b47c86f4975cf365ef", "tree": "c4d77e4da37ec5b45fc3aafdff84c5c5a76c8095", "parents": [ "6bc88e72d97a140cf657571a2f4a4f3e1c643954" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 18:21:43 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add XTX Tech. XT25F02E/04D/08B 3.3V parts\n\nThese are old chips with rather limited capabilities. Their\nblock-protection ranges are rather special, hence not added\nat the moment.\n\nDatasheets used:\nhttps://en.xtxtech.com/download/?AId\u003d118\nhttps://en.xtxtech.com/download/?AId\u003d136\nhttps://en.xtxtech.com/download/?AId\u003d51\n\nChange-Id: I28ec5087be63b394b0f387ca01e2391823680272\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/283\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "6bc88e72d97a140cf657571a2f4a4f3e1c643954", "tree": "58bb0483d5951b1648707ff651a318ffe27b7623", "parents": [ "3cddff471a7c5ada2770bd5c3e928e85fe2d037d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 16:32:08 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Boya/BoHong BY25Q32/64/128 3.3V variants\n\nAdd all remaining 3BA, 3.3V parts of the BY25Q family. Once more,\ndatasheets look very similar. The whole family supports volatile\nstatus-register writes, three status registers, and all the usual\ndual- and quad-i/o instructions. Also, they use the common, Win-\nbond-like block protection bits.\n\nDatasheets used:\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q32BS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q32CS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q32ES.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q64AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q64ES.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q128AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q128ES.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q128FS.pdf\n\nChange-Id: Iff9c0459d215669025bc2af8b619fcf17c56f528\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/282\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "3cddff471a7c5ada2770bd5c3e928e85fe2d037d", "tree": "2a2b5b44965fbbf695ee172d9bd0ac032b841fb5", "parents": [ "34e3de6f9e89801eb34927bc372a084e934042f2" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 15:18:53 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Complete Boya/BoHong BY25D family\n\nExcept for the sizes, the datasheets look the same. All chips support\ndual-output fast reads. There is some overlap with the BY25Q family,\nbut given the small sizes (2MiB max.), it doesn\u0027t seem worthwhile to\nadd additional entries for these chips.\n\nThe block protection of the BY25Ds is rather peculiar, hence not con-\nfigured: It looks like hardcoded CMP\u003d1, SEC\u003d1 with 8KiB sectors and\nno 32KiB limit.\n\nDatasheets used:\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D05AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D10AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D20AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D40AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D40ES.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D80AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25D16AS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q80BS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q80ES.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q16BS.pdf\nhttp://en.boyamicro.com/download/SPI_NOR_Flash/BY25Q16ES.pdf\n\nChange-Id: Ie3f8578c152fcedd3ccb60873018d92e1dc80876\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/281\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "34e3de6f9e89801eb34927bc372a084e934042f2", "tree": "11a9b565564d0290c0cacd20f18e89313ceceaf9", "parents": [ "f050370395afb0f4658458697984075dce551123" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 13:00:12 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add Zetta Device ZD25LQ64/128 1.8V parts\n\nDatasheets for both look very much the same. Block protection and\nQPI implementations seem to follow Winbond.\n\nDatasheets used:\nhttp://www.zettadevice.com/upload/file/pdf/DS_Zetta_25LQ64_RevA_20180801.pdf\nhttp://www.zettadevice.com/upload/file/20150821/DS_Zetta_25LQ128_RevA_20180815.pdf\n\nChange-Id: Iea8c4076105910b4e0975b02a92f287ded745eae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/280\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "2a1036b98c44529c64db645c481c0b35c81b21b0", "tree": "c72d463a2c50ce6f3145a38637094bedbb9b56a7", "parents": [ "d4e41d353604cb19938305590efbc81642152422" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Oct 20 23:19:49 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Fix up GD25Q128C write-protect support\n\nThe SPI write-protection functions were missing in the GD25Q128C\nentry. Fix that.\n\nDatasheet used:\nhttps://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf\n\nChange-Id: Ibda9f224fb5f57a0878246c324bceb2089dd70ae\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/277\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "d4e41d353604cb19938305590efbc81642152422", "tree": "50d1ec87c227b58de5c56723bfb86b6c09b1e305", "parents": [ "04c1cf789b0468de5fd1368469d90b6fc75b3c46" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Oct 18 14:59:54 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Feb 23 12:05:52 2025 +0000" }, "message": "flashchips: Add SST26VF080A\n\nSimple 8Mbit SPI flash, with one caveat though: SFDP reports 0xd8 as\nboth 32KiB and 64KiB eraser. The datasheet[1] lists this too in the\nSFDP table, however otherwise consistently states that erase blocks\nare uniform, and lists 0x52 as the 32KiB eraser. For now, we\u0027ll try\nthe latter.\n\n[1] https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/SST26VF080A-2.5V-3.0V-8-Mbit-Serial-Quad-IO-%28SQI%29-Flash-Memory-20006203C.pdf\n\nChange-Id: I7d66ff23ef9ded7365e9c75a1aff0a68678a4ba0\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/263\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "6ce26a72f721461d3de48c12cd1dc09a96b5519c", "tree": "7ca4f4b528dd04b73af42d05b721d4c30c00ca7a", "parents": [ "612519b2c54a008744891540407f2c8ff251083d" ], "author": { "name": "Alexandru M Stan", "email": "ams@frame.work", "time": "Fri Oct 11 22:47:24 2024 -0700" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 10 14:00:40 2024 +0000" }, "message": "flashchips: add Winbond W25R512NW / W74M51NW\n\nI used W25Q256JW as a template and just increased every erase size\ncalculation.\n\nDatasheet can be found by form contact only via\nhttps://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale\u003den_TW\u0026partNo\u003dW25R512NW\n\nI tested it by running:\ndd if\u003d/dev/urandom of\u003d/tmp/random.bin bs\u003d1M count\u003d64\nsudo /tmp/flashrom/build/flashrom -p ft2232_spi:type\u003d2232H -w /tmp/random.bin --progress\nsudo /tmp/flashrom/build/flashrom -p ft2232_spi:type\u003d2232H -v /tmp/random.bin\nAnd I saw \"Verifying flash... VERIFIED.\"\n\nChange-Id: Ibf670e4014a22e4636789768b759cb51f75cd046\nSigned-off-by: Alexandru M Stan \u003cams@frame.work\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/84752\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/272\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "9897063f72c2290d312954d34e305f472101a73b", "tree": "008e9415c6df6d4a528f16184c9f342c3d068712", "parents": [ "c972aedf9bbbcb5993135514095ab445cd6375e1" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 30 02:14:05 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 03 17:54:48 2024 +0000" }, "message": "flashchips: Allow volatile register writes for W25Q128.V\n\nMost status register bits can be written either volatile (with an\nEWSR prefix) or non-volatile (WREN prefix).\n\nTested setting a volatile QE and also volatile WP settings.\n\nChange-Id: I8fcd4d33027325150f9bb1a39865368a4b8995b5\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/255\n" }, { "commit": "c972aedf9bbbcb5993135514095ab445cd6375e1", "tree": "583f09e7278e25f2cbc7898276bdcb48625ef255", "parents": [ "8f7122cd1183a4224b14131483d549df497b22a6" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Aug 30 02:06:41 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Nov 03 17:54:48 2024 +0000" }, "message": "flashchips: Configure WP for MX25L25635F/45G\n\nTested with an RPi and `linux_spi\u0027.\n\nChange-Id: I76134fdbc73faaba3f9b78a5c5798da4d8940e28\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/254\n" }, { "commit": "768cfc461105e11852706154c85a312831821f4d", "tree": "1a77bf477fca555ea53b38e4fc9e9b7c5fbf8a7e", "parents": [ "d128a0ae87086b37c0e5d7a8d934bcdee173402f" ], "author": { "name": "Naresh Solanki", "email": "naresh.solanki@9elements.com", "time": "Fri Oct 04 20:17:34 2024 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Oct 14 18:42:03 2024 +0000" }, "message": "flashchips: Add GigaDevice GD25LR512ME\n\nTested on Birman+ board.\n\nChange-Id: I056d9245809c6fddae0123b8ed667deb5d00d6f6\nSigned-off-by: Naresh Solanki \u003cnaresh.solanki@9elements.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/262\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d128a0ae87086b37c0e5d7a8d934bcdee173402f", "tree": "e28ec82c6450d6abc520b9fd7f70d2d776f61dac", "parents": [ "c6a924aa66d7bbd56f28754c44668cc4f054c13d" ], "author": { "name": "Nicholas Chin", "email": "nic.c3.14@gmail.com", "time": "Fri Sep 27 22:57:22 2024 -0600" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Sep 29 23:37:04 2024 +0000" }, "message": "flashchips: Remove unsupported erase blocks for Winbond W25X{16,32,64}\n\nThis family of chips does not support the 0x52 (32 KiB block erase) and\n0x60 (chip erase) opcodes according to their datasheet.\n\nChange-Id: I35ecc4265fdee208855a4ce8f74880fdc8dfa326\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/260\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "930d421385aae5ca93d5963fba7926970d7702e8", "tree": "199e15c17260fabb8e422075230621a21e064531", "parents": [ "8d0f4650c73eb7bcda0b71e514c0effdf37d90b5" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat May 04 18:59:15 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi25: Introduce generic spi_prepare_io()/spi_finish_io()\n\nIntroduce two new functions to be hooked up in the chip database:\n* spi_prepare_io(), and\n* spi_finish_io().\n\nThese will be used to prepare multi-i/o and QPI operations. Hence,\nhook them up to all the chips that support those. spi_prepare_4ba()\nis wrapped to account for overlaps with 4BA support.\n\nChange-Id: I444f6322b6d6a26a040cb0ca972b2c411838d702\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/163\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "226bb87b96c21fbd54061d043aca67e9a02f0aca", "tree": "69907cf91ed509fd4dbd23a888e25605faf4475d", "parents": [ "4fa39c5e016698a5241269dac13d3ad3edb8d7ed" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Tue Apr 09 23:30:34 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Add missing QE-bit definitions\n\nFor all remaining chips that are already tagged as supporting quad-i/o,\nadd missing QE-bit definitions.\n\nChange-Id: I24fa7187c528882b78ac4ba376c410e06bf44f2b\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/124\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4fa39c5e016698a5241269dac13d3ad3edb8d7ed", "tree": "8a8023031d7bc085f2bc9496bd438e1258bf1d28", "parents": [ "5f50999184634a2d197495596dee9cbe3284be34" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 01:18:12 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill multi-i/o gaps in MX25U family\n\nChange-Id: I488ad3c2d2d2336cd8309514f699db797873963d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/123\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "5f50999184634a2d197495596dee9cbe3284be34", "tree": "437c97035908922d7b63b1c4e6ec7d4d10088caf", "parents": [ "46552c810b7501c3bbab940162fea891b42d9d14" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 01:18:12 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill multi-i/o gaps in MX25R family\n\nChange-Id: I358a0b3eb6ebad67c1e37cd61fcfee4087ede0e8\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/122\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "46552c810b7501c3bbab940162fea891b42d9d14", "tree": "9b703c38e183e54ac3390f1be62ff24de5b88b05", "parents": [ "96786d04a9675c786c8e5ca218f58276fdaefd28" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 01:18:12 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill multi-i/o gaps in MX25L family\n\nChange-Id: I8f1f7add3847f65b058e1a6e721a356bb728cb53\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/117\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "96786d04a9675c786c8e5ca218f58276fdaefd28", "tree": "86b9a5e061a4eb43a4eb0798679d3ef66b2ae1a5", "parents": [ "a26a3c6b6877e416681fe103478aa81121ef5f88" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 18:30:15 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill quad-i/o gaps in XM25Q family\n\nChange-Id: Icbbc6732651696c52e236e3828820db286f5ff81\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/48\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "a26a3c6b6877e416681fe103478aa81121ef5f88", "tree": "f4934754df61060441e7380ce77a6142b9e95639", "parents": [ "2133f596b1eb9597359b27c4dc996501dca910e1" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Fri Apr 12 19:28:28 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill dual-i/o gaps in W25X family\n\nChange-Id: I4536df38684258c780c74fc2b12830a4178f955d\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/121\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "2133f596b1eb9597359b27c4dc996501dca910e1", "tree": "ed16523bfd6f8730c31f9687e708b96e22e08b9c", "parents": [ "68573afd26ab16e02b7678663ee562384e552bc9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 18:30:01 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill quad-i/o gaps in W25Q family\n\nChange-Id: I8c53e9976b769327893838701eb0be9cff1443d7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/47\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "68573afd26ab16e02b7678663ee562384e552bc9", "tree": "0a3200774a473adfe45d03cb772fba85ac8925bd", "parents": [ "4da971fa6985ae7e2b0ca8031b156918c73293f8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 18:28:22 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Split GD25Q127C and GD25Q128C\n\nOnly GD25Q128C supports QPI.\n\nChange-Id: Iecaa15881a574426eb6889335ef6fbdfe017c617\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/46\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "4da971fa6985ae7e2b0ca8031b156918c73293f8", "tree": "f6511f3f2915b1ac7f8cc1985b2477161b3231d4", "parents": [ "f7e2d9739b8ccbc841081337c1d7c46407b5f0cf" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Mar 27 01:18:12 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Fill quad-i/o gaps in GD25*Q families\n\nChange-Id: Ice4596203384fd81244ed65e1f20e96da95b7af4\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/120\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "1412d9f435ead84d612086bf0051a4c3464bd079", "tree": "7d1e2050d97f8e12b280d267fac9a49dbab7939e", "parents": [ "d518563f197241cc72f5da4b2108b2df10f00372" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Jan 06 18:25:49 2024 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "spi: Rework FEATURE_QPI\n\nAlas, a single feature flag is not enough. QPI requires enter/exit\ncommands and there are at least two competing sets of opcodes. More-\nover, the current flag was sometimes accidentally used for chips\nthat can only do quad-i/o for address/data phases but not full QPI.\n\nSo, add a lot of new flags and go through all the entries that have\ncurrently FEATURE_QPI set. Additionally, note the amount of dummy\ncycles required by read commands in QPI mode, and whether and how\nthese can be configured.\n\nChange-Id: Id7310af07b2fdbedb7b051e9395ea967cb345d16\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/45\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "a358b14d2e7e93e317499a687223ada2d221a36a", "tree": "5f46662a287ab6a85d9c98ba220b76f05afa40b4", "parents": [ "3127db11dfecb54ea2432a6ca81ef7e7a1a383e9" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Apr 14 18:29:06 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Jul 22 10:08:47 2024 +0000" }, "message": "flashchips: Split W25Q64.W -\u003e W25Q64DW | W25Q64FW/W25Q64JW...Q\n\nThe older D versions used an extended write status register instruction\nto write both status registers at once. The newer ones have individual\nwrite status register 2 \u0026 3 instructions.\n\nIn theory, this fixes WP support for the W25Q64DW.\n\nChange-Id: I63605d4ac640c9e299afccb3b79ebd1a8f972d4c\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/119\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "0d4354eee32c834a602f5bec05803bd36977cfaa", "tree": "b21a5e04456629a1da344c0965ed90e1a31f09e8", "parents": [ "5b4fdd11dd74c7f018cb04f7a27a2badc02fe182" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Sun May 26 16:33:51 2024 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Jun 02 10:01:10 2024 +0000" }, "message": "flashchips: Add W25Q32JV-.M\n\nTested by `cobra` on IRC, on a ThinkPad R500.\n\nChange-Id: If1bffe0f09802f136636035f0f4ed31c3e33a7c4\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/150\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "aabb3e0ff54e87c0136c91f105e506ed19184cc6", "tree": "d53c2df274e9550b1f251a94b80add2d7285c5c4", "parents": [ "89569d60e3aeeec651496b2e7a2e6064d782ab3b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Jan 13 00:22:30 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "writeprotect: Hook wp functions into the chip driver\n\nChange-Id: I17a06210ec329aba337cf459d581463827182108\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72532\n" }, { "commit": "b197402042a065554234700b69057e9b6eedc39a", "tree": "62e4b15dff887d157ad18dd09b3d47dd2d7f8c1a", "parents": [ "0e76d99a7c0eda11515923c5457f0b5a4af9893f" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 13:13:12 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "memory_bus: Split register mapping into own function\n\nNow that we have a hook for the memory mapping, we don\u0027t need\nFEATURE_REGISTERMAP anymore and can clean up around it.\n\nChange-Id: If11ece9ce81ddf214b75764007a1006d271dc8af\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72523\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "9eec40780207a110f3ba7ea70d11c042c6d86abf", "tree": "f48e0860e967bd720901e9cf12faaa82363bf2c8", "parents": [ "56b53dd4c892c6f400f6b05797eb6ed4b96179db" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 12 01:17:30 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "Perform default mapping only for respective chips\n\nThe default memory mapping for the whole flash chip only makes sense\nfor chips that are directly connected to a bus serving memory cycles,\ni.e. parallel, LPC and FWH chips. Use the new `.prepare_access` and\n`.finish_access` hooks to map/unmap respective chips.\n\nGoing through the chip driver for this allows us to free the core\nflashprog code from this peculiarity.\n\nChange-Id: I54d1554b44b7e21fc18ef066103a9a26a2783b36\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72521\n" }, { "commit": "ab6b18f0e0d4f4b2b8348306576b701b63372bd2", "tree": "f9adeb7ab53e6fed6d940f852979b5da86dd7de1", "parents": [ "901fb957742edef9307948c397bdd28c8b5ebfac" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Jan 11 23:38:20 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Mar 09 10:30:24 2024 +0000" }, "message": "spi25: Move 4BA preparations into spi_prepare_4ba() hook\n\nThese preparations are specific to 4BA SPI chips and don\u0027t have to\nclutter `flashprog.c`.\n\nChange-Id: I842244c57e575f93b9c505e16f1f20c7afd23733\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72517\n" }, { "commit": "ddfbbe84b41d6a2fa3e2e7d031f55a82e05e6c76", "tree": "47ee340dd67aa6a1b59d0e4f883f88520b8ee9f1", "parents": [ "f9b777dde3a5f35cbd6d1d910d29bf70a4af5a98" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Dec 21 16:31:27 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Jan 25 09:24:39 2024 +0000" }, "message": "flashchips: Mark W25Q256JV_Q as tested\n\nMark probe, read, erase and write tested for W25Q256JV_Q. As reported in\nhttps://mail.sourcearcade.org/hyperkitty/list/flashprog@flashprog.org/thread/3HRWA76VCCW5S54KLUBJW3HGFFHPQLK6/\n\nChange-Id: Ia7526263dea5ddd692eb5d485c5919af1784c7d2\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReported-by: Mathieu Pilato \u003cpilatomic@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/41\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "5455786bfb4b09af11f4354a6bb4842d37d78419", "tree": "4444295adb9d0e6f9e13e08a16bc5c88a0b14352", "parents": [ "c3b02dce51aad2766512d1939a1b7447c2d526b8" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon May 15 12:01:04 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 08 19:56:50 2023 +0000" }, "message": "spi95: Avoid automatic probing\n\nIt turned out that the read ID command for the ST/M95 family (0x83)\nis a write command for AT45DB chips. We\u0027ll tag respective chips as\nusing a SPI95 command set, like we did for EDI, to avoid automatic\nprobing.\n\nChange-Id: Ibdf364424ac9cd8a734507a05fe769f008f8178e\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/75218\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n" }, { "commit": "c3b02dce51aad2766512d1939a1b7447c2d526b8", "tree": "58069f464bb8a777ef06e93767813a4c5a042cb0", "parents": [ "a02df33fbf1c196395a61049e60895d4ae0e0a5b" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sat Aug 12 01:13:45 2023 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Sep 18 19:24:39 2023 +0000" }, "message": "Rebrand to flashprog and update URLs\n\nMostly automated `sed` work. As of now, URLs to the old wiki are broken\neither way, so changing them shouldn\u0027t hurt. Other URLs (e.g. to mailing\nlist archives) were hopefully filtered correctly.\n\nChange-Id: I9d43bfd0e675eff2fcbad05f304b9ce9f5006b08\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashrom-stable/+/21\n" }, { "commit": "a2eaf4aa0166e107b3a3f9c50040d1b983cf4622", "tree": "0b0d4dc14d8898f4456705ab968d66e9a85cdc29", "parents": [ "07dd1219ff158a63dc9fa2d0f32f91bb03d8722e" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Wed Feb 15 22:56:53 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Thu Mar 16 21:49:40 2023 +0000" }, "message": "flashchips: Add entries for SST26VF016/032\n\nThey share a datasheet and look similar to the A/B variants that\nalready had entries but different IDs.\n\nChange-Id: I62ca123de917dc5c4766f3cf00a11d05b3befd4f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73043\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "111c380b2502df035057806fb727a724b18c815f", "tree": "c552fa6497313652798c34a16f41c2d3e56c6cd3", "parents": [ "b8ee2d63ae9f67bee7d6a2cab11de88128021e51" ], "author": { "name": "Kapil Porwal", "email": "kapilporwal@google.com", "time": "Fri Dec 09 19:41:27 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 06 23:36:26 2023 +0000" }, "message": "flashchips.c: Add reg_bits for W25Q256JW_DTR\n\nAdd reg_bits for W25Q256JW_DTR as per the datasheet.\n\nw/o this patch:\nFailed to get WP status: WP operations are not implemented for this chip\n\nw/ this patch:\nflashrom -p internal --wp-range 0x0,0x2000000\nflashrom -p internal --wp-enable\nflashrom -p internal --wp-status\nflashrom -p internal -E \u003c---- failed to erase the flash as WP (which is\nexpected)\n\nSigned-off-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nChange-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549\nOriginal-Reviewed-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73481\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "48dc090ae357bae82cdac2449fce8e7aad545922", "tree": "4fce1e7327fa5bd620213fdcc53fa62f39b427c6", "parents": [ "1e56360b267056e347b786349e6ec72e8f7216bc" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Sun Mar 05 17:20:55 2023 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 06 23:36:26 2023 +0000" }, "message": "flashchips: Drop FEATURE_4BA_WREN from MT25QU128\n\nThe chip is too small for that.\n\nChange-Id: I4672d6d0d1802490b200db475d6fa464772018d7\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73475\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "1e56360b267056e347b786349e6ec72e8f7216bc", "tree": "dfeb62f02b184503719463de61396a95b88bd191", "parents": [ "5d5b12201bfc7a56d7ece9a90632a960aa8393d3" ], "author": { "name": "Rick Altherr", "email": "kc8apf@kc8apf.net", "time": "Thu Dec 22 10:25:34 2022 -0800" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Mon Mar 06 23:36:26 2023 +0000" }, "message": "flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as tested\n\nUsing both a Dediprog SF100 and a Bus Pirate, read and erase works\ncorrectly on a MT25QL128 but writes were failing to take effect.\nCurrently, the entry in flashchips.c indicates that this device supports\n4-byte addressing. Micron\u0027s datasheet indicates that it does not.\nAfter removing FEATURE_4BA_WREN from feature_bits, both SF100 and\nBus Pirate were able to successfully read, erase, and write a\nMT25QL128 so also marking as tested.\n\nChange-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab\nSigned-off-by: Rick Altherr \u003ckc8apf@kc8apf.net\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73474\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "a97e353df0b3bb514502b7684b0171af75ff351e", "tree": "15fb98340333226c91a5a08780465672f7cb3195", "parents": [ "f5bffd99bd7737b77e51b3e1bdb3392355b10ff6" ], "author": { "name": "Edward O\u0027Callaghan", "email": "quasisec@google.com", "time": "Fri Dec 16 15:41:05 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:58 2022 +0100" }, "message": "flashchips.c: Mark W25Q128.V WP as tested\n\nTested: `-p internal --wp-status`.\n\nChange-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d\nSigned-off-by: Edward O\u0027Callaghan \u003cquasisec@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71240\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "f5bffd99bd7737b77e51b3e1bdb3392355b10ff6", "tree": "294477f73e4d021f19df9c55ce3758563640e2c5", "parents": [ "3c9bdb97190cbeaf383633d52a57810a2361dccc" ], "author": { "name": "Subrata Banik", "email": "subratabanik@google.com", "time": "Wed Dec 14 12:30:43 2022 +0530" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:58 2022 +0100" }, "message": "flashchips: Add WP settings for Flash Chip `W25Q512NW`\n\nThis patch adds WP register bits and decode range for Flash\nChip `W25Q512NW`.\n\nTested: Able to flash AP FW, wp-enable/disable on Google/rex device\nwhich has flash chip `W25Q512NW`.\n\nSigned-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nChange-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827\nOriginal-Reviewed-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nOriginal-Reviewed-by: Eric Lai \u003ceric_lai@quanta.corp-partner.google.com\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71239\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "3c9bdb97190cbeaf383633d52a57810a2361dccc", "tree": "daf19e4813959ffc7c8ac9d8ca19ae34bde731ea", "parents": [ "b931e7a81314d0a9e44312ada2996719da19154e" ], "author": { "name": "Felix Singer", "email": "felixsinger@posteo.net", "time": "Thu Dec 15 23:30:16 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "flashchips.c: Indent definition of W25Q512NW-IM properly\n\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nChange-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151\nOriginal-Reviewed-by: Eric Lai \u003ceric_lai@quanta.corp-partner.google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71238\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b931e7a81314d0a9e44312ada2996719da19154e", "tree": "06a427c3a3410a48e05e9c1c2da4fc571cd038ab", "parents": [ "09dd6ba4b16fd8d80e09de55702e0ba0a111ac89" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Mon Dec 05 13:06:14 2022 +1100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:57 2022 +0100" }, "message": "flashchips.c: remove WREN from GD25Q256D enter 4BA sequence\n\nAs noted in a comment on\n`commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D\ndatasheet indicates that the chip does not require a WREN command to\nenter 4BA mode.\n\nTesting has confirmed that a WREN command is not required, so change the\nflashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA.\n\nTicket: https://ticket.coreboot.org/issues/356\n\nTested: read/write/erase/verify GD25Q256D flash with FT2232H programmer\nTested: called spi_enter_exit_4ba(true), dumped registers, checked ADS\u003d1.\n\nChange-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71015\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "d5ba24c1a0870c9b1e3142ffa122851b22acf0da", "tree": "8208daddbf73ed9733b183524519d1c8b5206601", "parents": [ "b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:28:35 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E\n\nChange-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71011\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86", "tree": "159be3b6cf099734c86474a71131660f903399ab", "parents": [ "c6e8b1ad88ed1c65bba9c6002a36b16181c1ffec" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Mon Jul 25 00:27:37 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M\n\nSplit chips:\n * W25Q32.V -\u003e W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV\n * W25Q32.W -\u003e W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q\n\nChange-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71010\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "c6e8b1ad88ed1c65bba9c6002a36b16181c1ffec", "tree": "a96474c1ccdee8b8fcb54bf36894f639016979c2", "parents": [ "39687acc6bf41b955a11e8a8fa3f0029342cbb3e" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Sun Aug 14 20:57:48 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:56 2022 +0100" }, "message": "flashchips.c: enable WP for EN25QH32 and EN25QH64\n\nSplit chips:\n * EN25QH32 -\u003e EN25QH32 and EN25QH32B\n * EN25QH64 -\u003e EN25QH64 and EN25QH64A\n\nUnlike older revisions both newly added EN25QH32B and EN25QH64A support\nhalf block (32KiB) erase operation via 0x52 opcode.\n\nChange-Id: I759f0119346235ce0bddc78cde9c461495990c25\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71009\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n" }, { "commit": "29c8b5db5da5c0506aaac26fdfd3c8312638a51b", "tree": "4977598e6bfbbfe95ec1be529dd5b5d2b454c327", "parents": [ "d81997cdb76a721e46cfd98a7e65410d4e9790a5" ], "author": { "name": "Evan Benn", "email": "evanbenn@chromium.org", "time": "Tue Sep 13 16:01:10 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:55 2022 +0100" }, "message": "flashchips: Add write protect bits to W25Q64JW...M\n\nhttps://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale\u003den\u0026DocNo\u003dDA00-W25Q64JW\n\nTested: None\n\nChange-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62\nSigned-off-by: Evan Benn \u003cevanbenn@chromium.org\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71003\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "c74eac2fa3349c41f43eb9bd73809a1f051a9346", "tree": "330e6692197e48a9ad63b1b7db3fbf1eb201efde", "parents": [ "c720b6e8fbe9245e670f1424c5d24143b22a4c72" ], "author": { "name": "Sergii Dmytruk", "email": "sergii.dmytruk@3mdeb.com", "time": "Thu Oct 06 18:17:58 2022 +0300" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:54 2022 +0100" }, "message": "flashchips.c: mark WP of 9 entries as tested\n\nThis is based on information from:\n * commit a850fd0aa8054a1125a9231fa3317428f15900f4\n - GD25LQ128C/GD25LQ128D/GD25LQ128E\n - GD25LQ64(B)\n - GD25Q127C/GD25Q128C\n - GD25Q256D/GD25Q256E\n - GD25Q64(B)\n * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba\n - GD25Q32(B)\n * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8\n - W25Q64BV/W25Q64CV/W25Q64FV\n * https://github.com/Dasharo/dasharo-issues/issues/67\n - W25Q128.V..M\n * https://github.com/Dasharo/flashrom/pull/8\n - W25Q64.W\n\nChange-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Tested-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Tested-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Tested-by: Kamil Pokornicki \u003ckamil.pokornicki@3mdeb.com\u003e\nOriginal-Tested-by: Przemyslaw Banasiak \u003cprzemyslaw.banasiak@3mdeb.com\u003e\nOriginal-Tested-by: Maciej Pijanowski \u003cmaciej.pijanowski@3mdeb.com\u003e\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71001\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "590525835ab9f8b9471c17f859e0e18245008c08", "tree": "16fb4a4b18661a8692fd3f10e14ea8b25c29a3da", "parents": [ "3ca0af0c8baadb8a25056f0d6d7c2299822ae55b" ], "author": { "name": "Angel Pons", "email": "th3fanbus@gmail.com", "time": "Tue Mar 08 15:23:58 2022 +0100" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips.c: Mark MT25QU256 as tested\n\nAs reported by Charles Parent on the mailing list.\n\nChange-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62664\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70998\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "3ca0af0c8baadb8a25056f0d6d7c2299822ae55b", "tree": "d47899d5e121026e9dcc7655c0e1ed455030bf24", "parents": [ "bb608ff1900eee52c4bb3eb624421a8c0fe1b694" ], "author": { "name": "Nikolai Artemiev", "email": "nartemiev@google.com", "time": "Fri Jun 17 15:10:18 2022 +1000" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips.c: change GD25Q256D to \"GD25Q256D/GD25Q256E\"\n\nExtend \"D\" chip entry to include newer \"E\" parts.\n\nChange-Id: I6b398d417da9289cc1d6a191fb20e3f937addb21\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65191\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70997\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "bb608ff1900eee52c4bb3eb624421a8c0fe1b694", "tree": "3b020028e30f3c6888a26cccad0f99040d32e5dd", "parents": [ "26237922269390f11788ae573c4af39eb17d5e30" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:33:26 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:53 2022 +0100" }, "message": "flashchips: Add missing block eraser for S25FL512S\n\nNow that we can make use of the extended-address register, we can also\nadvertise the `d8` eraser that can take 3- or 4-byte addresses.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTicket: https://ticket.coreboot.org/issues/357\nChange-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64637\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70996\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "26237922269390f11788ae573c4af39eb17d5e30", "tree": "a91ae80f27628b92bc2401c6c3e871c0473473e5", "parents": [ "ad55d5a4ea4bc82450b076fbf9faffc130a698bb" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:37:37 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512S\n\nAccording to its datasheet, Spansion S25FL512S supports writing/\nreading its extended address register via 0x17/0x16 opcodes. With\nthat enabled, we can also enable the EAR7 feature, i.e. toggling\n4BA mode via bit 7 of that register.\n\nS25FL512S did not advertise EAR support at all, so we set it to\nTEST_UNTESTED again.\n\nChange-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70995\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "ad55d5a4ea4bc82450b076fbf9faffc130a698bb", "tree": "6beb87c779785e2e3a823b171231c51c5c6f2602", "parents": [ "9bb8a322e991b899a6faff4ec14d2f4c6dba447d" ], "author": { "name": "Nico Huber", "email": "nico.huber@secunet.com", "time": "Mon Jun 20 19:32:16 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips\n\nAccording to their datasheets, ISSI IS25LP256 and IS25WP256 support\nboth 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended\naddress register. Flashrom will use 0xc5 by default if available,\nso adding the FEATURE_4BA_EAR_1716 flag makes no difference for now\n(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA\nset). It\u0027s better to have a comprehensive description of the chips,\nthough, in case somebody wants to use them in the future with a\nmaster that restricts available opcodes.\n\nChange-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70994\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" }, { "commit": "9bb8a322e991b899a6faff4ec14d2f4c6dba447d", "tree": "466f98faf8e1f425b5c3144e399008bf14ac8b35", "parents": [ "542b1f04869e7ac42b84800675f08f617ddf3f2d" ], "author": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Tue May 24 15:07:34 2022 +0200" }, "committer": { "name": "Nico Huber", "email": "nico.h@gmx.de", "time": "Fri Dec 30 01:16:52 2022 +0100" }, "message": "flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716\n\nThere are two competing sets of instructions to access the extended\naddress register of 4BA SPI chips. Some chips even support both sets.\n\nSo far, we assumed the 0xc5/0xc8 instructions by default and allowed\nto override the write instructions with the `.wrea_override` field.\nThis has some disadvantages:\n\n* The additional field is easily overlooked. So when adding a new\n flash chip, one might assume only 0xc5/0xc8 are supported.\n\n* We cannot describe flash chips completely that allow both\n instructions (and some programmers may be picky about which\n instructions can be used).\n\nTherefore, replace the `.wrea_override` field with a feature flag.\n\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nChange-Id: I6d82f24898acd0789203516a7456fd785907bc10\nTicket: https://ticket.coreboot.org/issues/357\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70993\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n" } ], "next": "542b1f04869e7ac42b84800675f08f617ddf3f2d" }