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Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S
5 * Copyright (C) 2011, 2014 Stefan Tauner
6 *
7 * Based on nicinctel_spi.c and ichspi.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see http://www.gnu.org/licenses/.
20 */
21
22/*
23 * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet
24 * 3.3.1.4: General EEPROM Software Access
25 * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface)
26 * 7.4: Register Descriptions
27 */
28
29#include <stdlib.h>
30#include <unistd.h>
31#include "flash.h"
32#include "spi.h"
33#include "programmer.h"
34#include "hwaccess.h"
35
36#define PCI_VENDOR_ID_INTEL 0x8086
37#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */
38
39#define EEC 0x10 /* EEPROM/Flash Control Register */
40#define EERD 0x14 /* EEPROM Read Register */
41
42/* EPROM/Flash Control Register bits */
43#define EE_SCK 0
44#define EE_CS 1
45#define EE_SI 2
46#define EE_SO 3
47#define EE_REQ 6
48#define EE_GNT 7
49#define EE_PRES 8
50#define EE_SIZE 11
51#define EE_SIZE_MASK 0xf
52
53/* EEPROM Read Register bits */
54#define EERD_START 0
55#define EERD_DONE 1
56#define EERD_ADDR 2
57#define EERD_DATA 16
58
59#define BIT(x) (1<<x)
Stefan Tauner8d21ff12015-01-10 09:33:06 +000060#define EE_PAGE_MASK 0x3f
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000061
62static uint8_t *nicintel_eebar;
63static struct pci_dev *nicintel_pci;
64
65#define UNPROG_DEVICE 0x1509
66
67const struct dev_entry nics_intel_ee[] = {
68 {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"},
69 {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"},
70 {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"},
71 {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"},
72 {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"},
73 {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"},
74 {0},
75};
76
77static int nicintel_ee_probe(struct flashctx *flash)
78{
79 if (nicintel_pci->device_id == UNPROG_DEVICE)
80 flash->chip->total_size = 16; /* Fall back to minimum supported size. */
81 else {
82 uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC);
83 tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK);
84 switch (tmp) {
85 case 7:
86 flash->chip->total_size = 16;
87 break;
88 case 8:
89 flash->chip->total_size = 32;
90 break;
91 default:
92 msg_cerr("Unsupported chip size 0x%x\n", tmp);
93 return 0;
94 }
95 }
96
Stefan Tauner8d21ff12015-01-10 09:33:06 +000097 flash->chip->page_size = EE_PAGE_MASK + 1;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000098 flash->chip->tested = TEST_OK_PREW;
99 flash->chip->gran = write_gran_1byte_implicit_erase;
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000100 flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1);
101 flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1);
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000102
103 return 1;
104}
105
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000106static int nicintel_ee_read_word(unsigned int addr, uint16_t *data)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000107{
108 uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR);
109 pci_mmio_writel(tmp, nicintel_eebar + EERD);
110
111 /* Poll done flag. 10.000.000 cycles seem to be enough. */
112 uint32_t i;
113 for (i = 0; i < 10000000; i++) {
114 tmp = pci_mmio_readl(nicintel_eebar + EERD);
115 if (tmp & BIT(EERD_DONE)) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000116 *data = (tmp >> EERD_DATA) & 0xffff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000117 return 0;
118 }
119 }
120
121 return -1;
122}
123
124static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len)
125{
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000126 uint16_t data;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000127
128 /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address
129 * explicitly at the start (and also at the end in the loop below). */
130 if (addr & 1) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000131 if (nicintel_ee_read_word(addr / 2, &data))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000132 return -1;
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000133 *buf++ = data & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000134 addr++;
135 len--;
136 }
137
138 while (len > 0) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000139 if (nicintel_ee_read_word(addr / 2, &data))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000140 return -1;
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000141 *buf++ = data & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000142 addr++;
143 len--;
144 if (len > 0) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000145 *buf++ = (data >> 8) & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000146 addr++;
147 len--;
148 }
149 }
150
151 return 0;
152}
153
154static int nicintel_ee_bitset(int reg, int bit, bool val)
155{
156 uint32_t tmp;
157
158 tmp = pci_mmio_readl(nicintel_eebar + reg);
159 if (val)
160 tmp |= BIT(bit);
161 else
162 tmp &= ~BIT(bit);
163 pci_mmio_writel(tmp, nicintel_eebar + reg);
164
165 return -1;
166}
167
168/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */
169static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso)
170{
171 uint8_t out = 0x0;
172
173 int i;
174 for (i = 7; i >= 0; i--) {
175 nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i));
176 nicintel_ee_bitset(EEC, EE_SCK, 1);
177 if (miso != NULL) {
178 uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC);
179 if (tmp & BIT(EE_SO))
180 out |= BIT(i);
181 }
182 nicintel_ee_bitset(EEC, EE_SCK, 0);
183 }
184
185 if (miso != NULL)
186 *miso = out;
187
188 return 0;
189}
190
191/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */
192static int nicintel_ee_ready(void)
193{
194 unsigned int i;
195 for (i = 0; i < 1000; i++) {
196 nicintel_ee_bitset(EEC, EE_CS, 0);
197
198 nicintel_ee_bitbang(JEDEC_RDSR, NULL);
199 uint8_t rdsr;
200 nicintel_ee_bitbang(0x00, &rdsr);
201
202 nicintel_ee_bitset(EEC, EE_CS, 1);
203 programmer_delay(1);
204 if (!(rdsr & SPI_SR_WIP)) {
205 return 0;
206 }
207 }
208 return -1;
209}
210
211/* Requests direct access to the SPI pins. */
212static int nicintel_ee_req(void)
213{
214 uint32_t tmp;
215 nicintel_ee_bitset(EEC, EE_REQ, 1);
216
217 tmp = pci_mmio_readl(nicintel_eebar + EEC);
218 if (!(tmp & BIT(EE_GNT))) {
219 msg_perr("Enabling eeprom access failed.\n");
220 return 1;
221 }
222
223 nicintel_ee_bitset(EEC, EE_SCK, 0);
224 return 0;
225}
226
227static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
228{
229 if (nicintel_ee_req())
230 return -1;
231
232 int ret = -1;
233 if (nicintel_ee_ready())
234 goto out;
235
236 while (len > 0) {
237 /* WREN */
238 nicintel_ee_bitset(EEC, EE_CS, 0);
239 nicintel_ee_bitbang(JEDEC_WREN, NULL);
240 nicintel_ee_bitset(EEC, EE_CS, 1);
241 programmer_delay(1);
242
243 /* data */
244 nicintel_ee_bitset(EEC, EE_CS, 0);
245 nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL);
246 nicintel_ee_bitbang((addr >> 8) & 0xff, NULL);
247 nicintel_ee_bitbang(addr & 0xff, NULL);
248 while (len > 0) {
249 nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL);
250 len--;
251 addr++;
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000252 if (!(addr & EE_PAGE_MASK))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000253 break;
254 }
255 nicintel_ee_bitset(EEC, EE_CS, 1);
256 programmer_delay(1);
257 if (nicintel_ee_ready())
258 goto out;
259 }
260 ret = 0;
261out:
262 nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */
263 return ret;
264}
265
266static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len)
267{
268 return nicintel_ee_write(flash, NULL, addr, len);
269}
270
271static const struct opaque_master opaque_master_nicintel_ee = {
272 .probe = nicintel_ee_probe,
273 .read = nicintel_ee_read,
274 .write = nicintel_ee_write,
275 .erase = nicintel_ee_erase,
276};
277
278static int nicintel_spi_shutdown(void *eecp)
279{
280 uint32_t old_eec = *(uint32_t *)eecp;
281 /* Request bitbanging and unselect the chip first to be safe. */
282 if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1))
283 return -1;
284
285 /* Try to restore individual bits we care about. */
286 int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK));
287 ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI));
288 ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS));
289 /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */
290 ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ));
291
292 free(eecp);
293 return ret;
294}
295
296int nicintel_ee_init(void)
297{
298 if (rget_io_perms())
299 return 1;
300
301 struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0);
302 if (!dev)
303 return 1;
304
305 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
306 if (!io_base_addr)
307 return 1;
308
309 nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE);
310 nicintel_pci = dev;
311 if (dev->device_id != UNPROG_DEVICE) {
312 uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC);
313
314 /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition),
315 * and 3.3.1.7 for possible recovery. */
316 if (!(eec & BIT(EE_PRES))) {
317 msg_perr("Controller reports no EEPROM is present.\n");
318 return 1;
319 }
320
321 uint32_t *eecp = malloc(sizeof(uint32_t));
322 if (eecp == NULL)
323 return 1;
324 *eecp = eec;
325
326 if (register_shutdown(nicintel_spi_shutdown, eecp))
327 return 1;
328 }
329
330 return register_opaque_master(&opaque_master_nicintel_ee);
331}