Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the common SPI chip driver functions |
| 23 | */ |
| 24 | |
| 25 | #include <string.h> |
| 26 | #include "flash.h" |
| 27 | #include "flashchips.h" |
| 28 | #include "chipdrivers.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 29 | #include "programmer.h" |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 30 | #include "spi.h" |
| 31 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 32 | static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 33 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 34 | static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 35 | int ret; |
| 36 | int i; |
| 37 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 38 | ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 39 | if (ret) |
| 40 | return ret; |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 41 | msg_cspew("RDID returned"); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 42 | for (i = 0; i < bytes; i++) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 43 | msg_cspew(" 0x%02x", readarr[i]); |
| 44 | msg_cspew(". "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 45 | return 0; |
| 46 | } |
| 47 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 48 | static int spi_rems(struct flashctx *flash, unsigned char *readarr) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 49 | { |
| 50 | unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; |
| 51 | uint32_t readaddr; |
| 52 | int ret; |
| 53 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 54 | ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, |
| 55 | readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 56 | if (ret == SPI_INVALID_ADDRESS) { |
| 57 | /* Find the lowest even address allowed for reads. */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 58 | readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 59 | cmd[1] = (readaddr >> 16) & 0xff, |
| 60 | cmd[2] = (readaddr >> 8) & 0xff, |
| 61 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 62 | ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, |
| 63 | cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 64 | } |
| 65 | if (ret) |
| 66 | return ret; |
Cristian Măgherușan-Stanciu | 9932c7b | 2011-07-07 19:56:58 +0000 | [diff] [blame] | 67 | msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 68 | return 0; |
| 69 | } |
| 70 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 71 | static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 72 | { |
| 73 | unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; |
| 74 | uint32_t readaddr; |
| 75 | int ret; |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 76 | int i; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 77 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 78 | ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 79 | if (ret == SPI_INVALID_ADDRESS) { |
| 80 | /* Find the lowest even address allowed for reads. */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 81 | readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 82 | cmd[1] = (readaddr >> 16) & 0xff, |
| 83 | cmd[2] = (readaddr >> 8) & 0xff, |
| 84 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 85 | ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 86 | } |
| 87 | if (ret) |
| 88 | return ret; |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 89 | msg_cspew("RES returned"); |
| 90 | for (i = 0; i < bytes; i++) |
| 91 | msg_cspew(" 0x%02x", readarr[i]); |
| 92 | msg_cspew(". "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 93 | return 0; |
| 94 | } |
| 95 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 96 | int spi_write_enable(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 97 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 98 | static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 99 | int result; |
| 100 | |
| 101 | /* Send WREN (Write Enable) */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 102 | result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 103 | |
| 104 | if (result) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 105 | msg_cerr("%s failed\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 106 | |
| 107 | return result; |
| 108 | } |
| 109 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 110 | int spi_write_disable(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 111 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 112 | static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 113 | |
| 114 | /* Send WRDI (Write Disable) */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 115 | return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 118 | static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 119 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 120 | const struct flashchip *chip = flash->chip; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 121 | unsigned char readarr[4]; |
| 122 | uint32_t id1; |
| 123 | uint32_t id2; |
| 124 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 125 | if (spi_rdid(flash, readarr, bytes)) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 126 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 127 | } |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 128 | |
| 129 | if (!oddparity(readarr[0])) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 130 | msg_cdbg("RDID byte 0 parity violation. "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 131 | |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 132 | /* Check if this is a continuation vendor ID. |
| 133 | * FIXME: Handle continuation device IDs. |
| 134 | */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 135 | if (readarr[0] == 0x7f) { |
| 136 | if (!oddparity(readarr[1])) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 137 | msg_cdbg("RDID byte 1 parity violation. "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 138 | id1 = (readarr[0] << 8) | readarr[1]; |
| 139 | id2 = readarr[2]; |
| 140 | if (bytes > 3) { |
| 141 | id2 <<= 8; |
| 142 | id2 |= readarr[3]; |
| 143 | } |
| 144 | } else { |
| 145 | id1 = readarr[0]; |
| 146 | id2 = (readarr[1] << 8) | readarr[2]; |
| 147 | } |
| 148 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 149 | msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 150 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 151 | if (id1 == chip->manufacture_id && id2 == chip->model_id) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 152 | /* Print the status register to tell the |
| 153 | * user about possible write protection. |
| 154 | */ |
| 155 | spi_prettyprint_status_register(flash); |
| 156 | |
| 157 | return 1; |
| 158 | } |
| 159 | |
| 160 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 161 | if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 162 | return 1; |
| 163 | |
| 164 | /* Test if there is any vendor ID. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 165 | if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 166 | return 1; |
| 167 | |
| 168 | return 0; |
| 169 | } |
| 170 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 171 | int probe_spi_rdid(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 172 | { |
| 173 | return probe_spi_rdid_generic(flash, 3); |
| 174 | } |
| 175 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 176 | int probe_spi_rdid4(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 177 | { |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 178 | /* Some SPI controllers do not support commands with writecnt=1 and |
| 179 | * readcnt=4. |
| 180 | */ |
Carl-Daniel Hailfinger | c40cff7 | 2011-12-20 00:19:29 +0000 | [diff] [blame] | 181 | switch (flash->pgm->spi.type) { |
Carl-Daniel Hailfinger | 7112772 | 2010-05-31 15:27:27 +0000 | [diff] [blame] | 182 | #if CONFIG_INTERNAL == 1 |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 183 | #if defined(__i386__) || defined(__x86_64__) |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 184 | case SPI_CONTROLLER_IT87XX: |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 185 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 186 | msg_cinfo("4 byte RDID not supported on this SPI controller\n"); |
| 187 | return 0; |
| 188 | break; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 189 | #endif |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 190 | #endif |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 191 | default: |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 192 | return probe_spi_rdid_generic(flash, 4); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | return 0; |
| 196 | } |
| 197 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 198 | int probe_spi_rems(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 199 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 200 | const struct flashchip *chip = flash->chip; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 201 | unsigned char readarr[JEDEC_REMS_INSIZE]; |
| 202 | uint32_t id1, id2; |
| 203 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 204 | if (spi_rems(flash, readarr)) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 205 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 206 | } |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 207 | |
| 208 | id1 = readarr[0]; |
| 209 | id2 = readarr[1]; |
| 210 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 211 | msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 212 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 213 | if (id1 == chip->manufacture_id && id2 == chip->model_id) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 214 | /* Print the status register to tell the |
| 215 | * user about possible write protection. |
| 216 | */ |
| 217 | spi_prettyprint_status_register(flash); |
| 218 | |
| 219 | return 1; |
| 220 | } |
| 221 | |
| 222 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 223 | if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 224 | return 1; |
| 225 | |
| 226 | /* Test if there is any vendor ID. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 227 | if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 228 | return 1; |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 233 | int probe_spi_res1(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 234 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 235 | static const unsigned char allff[] = {0xff, 0xff, 0xff}; |
| 236 | static const unsigned char all00[] = {0x00, 0x00, 0x00}; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 237 | unsigned char readarr[3]; |
| 238 | uint32_t id2; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 239 | |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 240 | /* We only want one-byte RES if RDID and REMS are unusable. */ |
| 241 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 242 | /* Check if RDID is usable and does not return 0xff 0xff 0xff or |
| 243 | * 0x00 0x00 0x00. In that case, RES is pointless. |
| 244 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 245 | if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) && |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 246 | memcmp(readarr, all00, 3)) { |
| 247 | msg_cdbg("Ignoring RES in favour of RDID.\n"); |
| 248 | return 0; |
| 249 | } |
| 250 | /* Check if REMS is usable and does not return 0xff 0xff or |
| 251 | * 0x00 0x00. In that case, RES is pointless. |
| 252 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 253 | if (!spi_rems(flash, readarr) && |
| 254 | memcmp(readarr, allff, JEDEC_REMS_INSIZE) && |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 255 | memcmp(readarr, all00, JEDEC_REMS_INSIZE)) { |
| 256 | msg_cdbg("Ignoring RES in favour of REMS.\n"); |
| 257 | return 0; |
| 258 | } |
| 259 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 260 | if (spi_res(flash, readarr, 1)) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 261 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 262 | } |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 263 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 264 | id2 = readarr[0]; |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 265 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 266 | msg_cdbg("%s: id 0x%x\n", __func__, id2); |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 267 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 268 | if (id2 != flash->chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 269 | return 0; |
| 270 | |
| 271 | /* Print the status register to tell the |
| 272 | * user about possible write protection. |
| 273 | */ |
| 274 | spi_prettyprint_status_register(flash); |
| 275 | return 1; |
| 276 | } |
| 277 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 278 | int probe_spi_res2(struct flashctx *flash) |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 279 | { |
| 280 | unsigned char readarr[2]; |
| 281 | uint32_t id1, id2; |
| 282 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 283 | if (spi_res(flash, readarr, 2)) { |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 284 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 285 | } |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 286 | |
| 287 | id1 = readarr[0]; |
| 288 | id2 = readarr[1]; |
| 289 | |
| 290 | msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); |
| 291 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 292 | if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 293 | return 0; |
| 294 | |
| 295 | /* Print the status register to tell the |
| 296 | * user about possible write protection. |
| 297 | */ |
| 298 | spi_prettyprint_status_register(flash); |
| 299 | return 1; |
| 300 | } |
| 301 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 302 | uint8_t spi_read_status_register(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 303 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 304 | static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 305 | /* FIXME: No workarounds for driver/hardware bugs in generic code. */ |
| 306 | unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ |
| 307 | int ret; |
| 308 | |
| 309 | /* Read Status Register */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 310 | ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, |
| 311 | readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 312 | if (ret) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 313 | msg_cerr("RDSR failed!\n"); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 314 | |
| 315 | return readarr[0]; |
| 316 | } |
| 317 | |
| 318 | /* Prettyprint the status register. Common definitions. */ |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 319 | void spi_prettyprint_status_register_welwip(uint8_t status) |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 320 | { |
| 321 | msg_cdbg("Chip status register: Write Enable Latch (WEL) is " |
| 322 | "%sset\n", (status & (1 << 1)) ? "" : "not "); |
| 323 | msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is " |
| 324 | "%sset\n", (status & (1 << 0)) ? "" : "not "); |
| 325 | } |
| 326 | |
| 327 | /* Prettyprint the status register. Common definitions. */ |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 328 | void spi_prettyprint_status_register_bp(uint8_t status, int bp) |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 329 | { |
| 330 | switch (bp) { |
| 331 | /* Fall through. */ |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 332 | case 4: |
| 333 | msg_cdbg("Chip status register: Block Protect 4 (BP4) " |
| 334 | "is %sset\n", (status & (1 << 5)) ? "" : "not "); |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 335 | case 3: |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 336 | msg_cdbg("Chip status register: Block Protect 3 (BP3) " |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 337 | "is %sset\n", (status & (1 << 5)) ? "" : "not "); |
| 338 | case 2: |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 339 | msg_cdbg("Chip status register: Block Protect 2 (BP2) " |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 340 | "is %sset\n", (status & (1 << 4)) ? "" : "not "); |
| 341 | case 1: |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 342 | msg_cdbg("Chip status register: Block Protect 1 (BP1) " |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 343 | "is %sset\n", (status & (1 << 3)) ? "" : "not "); |
| 344 | case 0: |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 345 | msg_cdbg("Chip status register: Block Protect 0 (BP0) " |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 346 | "is %sset\n", (status & (1 << 2)) ? "" : "not "); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | /* Prettyprint the status register. Unnamed bits. */ |
| 351 | void spi_prettyprint_status_register_bit(uint8_t status, int bit) |
| 352 | { |
| 353 | msg_cdbg("Chip status register: Bit %i " |
| 354 | "is %sset\n", bit, (status & (1 << bit)) ? "" : "not "); |
| 355 | } |
| 356 | |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 357 | static void spi_prettyprint_status_register_common(uint8_t status) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 358 | { |
Stefan Tauner | 1ba08f6 | 2012-08-02 23:51:28 +0000 | [diff] [blame] | 359 | spi_prettyprint_status_register_bp(status, 3); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 360 | spi_prettyprint_status_register_welwip(status); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | /* Prettyprint the status register. Works for |
| 364 | * ST M25P series |
| 365 | * MX MX25L series |
| 366 | */ |
| 367 | void spi_prettyprint_status_register_st_m25p(uint8_t status) |
| 368 | { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 369 | msg_cdbg("Chip status register: Status Register Write Disable " |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 370 | "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 371 | msg_cdbg("Chip status register: Bit 6 is " |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 372 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
| 373 | spi_prettyprint_status_register_common(status); |
| 374 | } |
| 375 | |
| 376 | void spi_prettyprint_status_register_sst25(uint8_t status) |
| 377 | { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 378 | msg_cdbg("Chip status register: Block Protect Write Disable " |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 379 | "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 380 | msg_cdbg("Chip status register: Auto Address Increment Programming " |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 381 | "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); |
| 382 | spi_prettyprint_status_register_common(status); |
| 383 | } |
| 384 | |
| 385 | /* Prettyprint the status register. Works for |
| 386 | * SST 25VF016 |
| 387 | */ |
| 388 | void spi_prettyprint_status_register_sst25vf016(uint8_t status) |
| 389 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 390 | static const char *const bpt[] = { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 391 | "none", |
| 392 | "1F0000H-1FFFFFH", |
| 393 | "1E0000H-1FFFFFH", |
| 394 | "1C0000H-1FFFFFH", |
| 395 | "180000H-1FFFFFH", |
| 396 | "100000H-1FFFFFH", |
| 397 | "all", "all" |
| 398 | }; |
| 399 | spi_prettyprint_status_register_sst25(status); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 400 | msg_cdbg("Resulting block protection : %s\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 401 | bpt[(status & 0x1c) >> 2]); |
| 402 | } |
| 403 | |
| 404 | void spi_prettyprint_status_register_sst25vf040b(uint8_t status) |
| 405 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 406 | static const char *const bpt[] = { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 407 | "none", |
| 408 | "0x70000-0x7ffff", |
| 409 | "0x60000-0x7ffff", |
| 410 | "0x40000-0x7ffff", |
| 411 | "all blocks", "all blocks", "all blocks", "all blocks" |
| 412 | }; |
| 413 | spi_prettyprint_status_register_sst25(status); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 414 | msg_cdbg("Resulting block protection : %s\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 415 | bpt[(status & 0x1c) >> 2]); |
| 416 | } |
| 417 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 418 | int spi_prettyprint_status_register(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 419 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 420 | const struct flashchip *chip = flash->chip; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 421 | uint8_t status; |
| 422 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 423 | status = spi_read_status_register(flash); |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 424 | msg_cdbg("Chip status register is %02x\n", status); |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 425 | switch (chip->manufacture_id) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 426 | case ST_ID: |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 427 | if (((chip->model_id & 0xff00) == 0x2000) || |
| 428 | ((chip->model_id & 0xff00) == 0x2500)) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 429 | spi_prettyprint_status_register_st_m25p(status); |
| 430 | break; |
Mattias Mattsson | 6eabe28 | 2010-09-15 23:31:03 +0000 | [diff] [blame] | 431 | case MACRONIX_ID: |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 432 | if ((chip->model_id & 0xff00) == 0x2000) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 433 | spi_prettyprint_status_register_st_m25p(status); |
| 434 | break; |
| 435 | case SST_ID: |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 436 | switch (chip->model_id) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 437 | case 0x2541: |
| 438 | spi_prettyprint_status_register_sst25vf016(status); |
| 439 | break; |
| 440 | case 0x8d: |
| 441 | case 0x258d: |
| 442 | spi_prettyprint_status_register_sst25vf040b(status); |
| 443 | break; |
| 444 | default: |
| 445 | spi_prettyprint_status_register_sst25(status); |
| 446 | break; |
| 447 | } |
| 448 | break; |
| 449 | } |
Carl-Daniel Hailfinger | 7a3bd8f | 2011-05-19 00:06:06 +0000 | [diff] [blame] | 450 | return 0; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 451 | } |
| 452 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 453 | int spi_chip_erase_60(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 454 | { |
| 455 | int result; |
| 456 | struct spi_command cmds[] = { |
| 457 | { |
| 458 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 459 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 460 | .readcnt = 0, |
| 461 | .readarr = NULL, |
| 462 | }, { |
| 463 | .writecnt = JEDEC_CE_60_OUTSIZE, |
| 464 | .writearr = (const unsigned char[]){ JEDEC_CE_60 }, |
| 465 | .readcnt = 0, |
| 466 | .readarr = NULL, |
| 467 | }, { |
| 468 | .writecnt = 0, |
| 469 | .writearr = NULL, |
| 470 | .readcnt = 0, |
| 471 | .readarr = NULL, |
| 472 | }}; |
| 473 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 474 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 475 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 476 | msg_cerr("%s failed during command execution\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 477 | __func__); |
| 478 | return result; |
| 479 | } |
| 480 | /* Wait until the Write-In-Progress bit is cleared. |
| 481 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 482 | */ |
| 483 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 484 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 485 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 486 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 487 | return 0; |
| 488 | } |
| 489 | |
Stefan Tauner | 3c0fcd0 | 2012-09-21 12:46:56 +0000 | [diff] [blame] | 490 | int spi_chip_erase_62(struct flashctx *flash) |
| 491 | { |
| 492 | int result; |
| 493 | struct spi_command cmds[] = { |
| 494 | { |
| 495 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 496 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 497 | .readcnt = 0, |
| 498 | .readarr = NULL, |
| 499 | }, { |
| 500 | .writecnt = JEDEC_CE_62_OUTSIZE, |
| 501 | .writearr = (const unsigned char[]){ JEDEC_CE_62 }, |
| 502 | .readcnt = 0, |
| 503 | .readarr = NULL, |
| 504 | }, { |
| 505 | .writecnt = 0, |
| 506 | .writearr = NULL, |
| 507 | .readcnt = 0, |
| 508 | .readarr = NULL, |
| 509 | }}; |
| 510 | |
| 511 | result = spi_send_multicommand(flash, cmds); |
| 512 | if (result) { |
| 513 | msg_cerr("%s failed during command execution\n", |
| 514 | __func__); |
| 515 | return result; |
| 516 | } |
| 517 | /* Wait until the Write-In-Progress bit is cleared. |
| 518 | * This usually takes 2-5 s, so wait in 100 ms steps. |
| 519 | */ |
| 520 | /* FIXME: We assume spi_read_status_register will never fail. */ |
| 521 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
| 522 | programmer_delay(100 * 1000); |
| 523 | /* FIXME: Check the status register for errors. */ |
| 524 | return 0; |
| 525 | } |
| 526 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 527 | int spi_chip_erase_c7(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 528 | { |
| 529 | int result; |
| 530 | struct spi_command cmds[] = { |
| 531 | { |
| 532 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 533 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 534 | .readcnt = 0, |
| 535 | .readarr = NULL, |
| 536 | }, { |
| 537 | .writecnt = JEDEC_CE_C7_OUTSIZE, |
| 538 | .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, |
| 539 | .readcnt = 0, |
| 540 | .readarr = NULL, |
| 541 | }, { |
| 542 | .writecnt = 0, |
| 543 | .writearr = NULL, |
| 544 | .readcnt = 0, |
| 545 | .readarr = NULL, |
| 546 | }}; |
| 547 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 548 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 549 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 550 | msg_cerr("%s failed during command execution\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 551 | return result; |
| 552 | } |
| 553 | /* Wait until the Write-In-Progress bit is cleared. |
| 554 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 555 | */ |
| 556 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 557 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 558 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 559 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 560 | return 0; |
| 561 | } |
| 562 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 563 | int spi_block_erase_52(struct flashctx *flash, unsigned int addr, |
| 564 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 565 | { |
| 566 | int result; |
| 567 | struct spi_command cmds[] = { |
| 568 | { |
| 569 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 570 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 571 | .readcnt = 0, |
| 572 | .readarr = NULL, |
| 573 | }, { |
| 574 | .writecnt = JEDEC_BE_52_OUTSIZE, |
| 575 | .writearr = (const unsigned char[]){ |
| 576 | JEDEC_BE_52, |
| 577 | (addr >> 16) & 0xff, |
| 578 | (addr >> 8) & 0xff, |
| 579 | (addr & 0xff) |
| 580 | }, |
| 581 | .readcnt = 0, |
| 582 | .readarr = NULL, |
| 583 | }, { |
| 584 | .writecnt = 0, |
| 585 | .writearr = NULL, |
| 586 | .readcnt = 0, |
| 587 | .readarr = NULL, |
| 588 | }}; |
| 589 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 590 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 591 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 592 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 593 | __func__, addr); |
| 594 | return result; |
| 595 | } |
| 596 | /* Wait until the Write-In-Progress bit is cleared. |
| 597 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 598 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 599 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 600 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 601 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | /* Block size is usually |
| 606 | * 64k for Macronix |
| 607 | * 32k for SST |
| 608 | * 4-32k non-uniform for EON |
| 609 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 610 | int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, |
| 611 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 612 | { |
| 613 | int result; |
| 614 | struct spi_command cmds[] = { |
| 615 | { |
| 616 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 617 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 618 | .readcnt = 0, |
| 619 | .readarr = NULL, |
| 620 | }, { |
| 621 | .writecnt = JEDEC_BE_D8_OUTSIZE, |
| 622 | .writearr = (const unsigned char[]){ |
| 623 | JEDEC_BE_D8, |
| 624 | (addr >> 16) & 0xff, |
| 625 | (addr >> 8) & 0xff, |
| 626 | (addr & 0xff) |
| 627 | }, |
| 628 | .readcnt = 0, |
| 629 | .readarr = NULL, |
| 630 | }, { |
| 631 | .writecnt = 0, |
| 632 | .writearr = NULL, |
| 633 | .readcnt = 0, |
| 634 | .readarr = NULL, |
| 635 | }}; |
| 636 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 637 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 638 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 639 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 640 | __func__, addr); |
| 641 | return result; |
| 642 | } |
| 643 | /* Wait until the Write-In-Progress bit is cleared. |
| 644 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 645 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 646 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 647 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 648 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | /* Block size is usually |
| 653 | * 4k for PMC |
| 654 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 655 | int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, |
| 656 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 657 | { |
| 658 | int result; |
| 659 | struct spi_command cmds[] = { |
| 660 | { |
| 661 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 662 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 663 | .readcnt = 0, |
| 664 | .readarr = NULL, |
| 665 | }, { |
| 666 | .writecnt = JEDEC_BE_D7_OUTSIZE, |
| 667 | .writearr = (const unsigned char[]){ |
| 668 | JEDEC_BE_D7, |
| 669 | (addr >> 16) & 0xff, |
| 670 | (addr >> 8) & 0xff, |
| 671 | (addr & 0xff) |
| 672 | }, |
| 673 | .readcnt = 0, |
| 674 | .readarr = NULL, |
| 675 | }, { |
| 676 | .writecnt = 0, |
| 677 | .writearr = NULL, |
| 678 | .readcnt = 0, |
| 679 | .readarr = NULL, |
| 680 | }}; |
| 681 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 682 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 683 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 684 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 685 | __func__, addr); |
| 686 | return result; |
| 687 | } |
| 688 | /* Wait until the Write-In-Progress bit is cleared. |
| 689 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 690 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 691 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 692 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 693 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 694 | return 0; |
| 695 | } |
| 696 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 697 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 698 | int spi_block_erase_20(struct flashctx *flash, unsigned int addr, |
| 699 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 700 | { |
| 701 | int result; |
| 702 | struct spi_command cmds[] = { |
| 703 | { |
| 704 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 705 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 706 | .readcnt = 0, |
| 707 | .readarr = NULL, |
| 708 | }, { |
| 709 | .writecnt = JEDEC_SE_OUTSIZE, |
| 710 | .writearr = (const unsigned char[]){ |
| 711 | JEDEC_SE, |
| 712 | (addr >> 16) & 0xff, |
| 713 | (addr >> 8) & 0xff, |
| 714 | (addr & 0xff) |
| 715 | }, |
| 716 | .readcnt = 0, |
| 717 | .readarr = NULL, |
| 718 | }, { |
| 719 | .writecnt = 0, |
| 720 | .writearr = NULL, |
| 721 | .readcnt = 0, |
| 722 | .readarr = NULL, |
| 723 | }}; |
| 724 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 725 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 726 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 727 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 728 | __func__, addr); |
| 729 | return result; |
| 730 | } |
| 731 | /* Wait until the Write-In-Progress bit is cleared. |
| 732 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 733 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 734 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 735 | programmer_delay(10 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 736 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 737 | return 0; |
| 738 | } |
| 739 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 740 | int spi_block_erase_60(struct flashctx *flash, unsigned int addr, |
| 741 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 742 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 743 | if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 744 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 745 | __func__); |
| 746 | return -1; |
| 747 | } |
| 748 | return spi_chip_erase_60(flash); |
| 749 | } |
| 750 | |
Stefan Tauner | 3c0fcd0 | 2012-09-21 12:46:56 +0000 | [diff] [blame] | 751 | int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen) |
| 752 | { |
| 753 | if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) { |
| 754 | msg_cerr("%s called with incorrect arguments\n", |
| 755 | __func__); |
| 756 | return -1; |
| 757 | } |
| 758 | return spi_chip_erase_62(flash); |
| 759 | } |
| 760 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 761 | int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, |
| 762 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 763 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 764 | if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 765 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 766 | __func__); |
| 767 | return -1; |
| 768 | } |
| 769 | return spi_chip_erase_c7(flash); |
| 770 | } |
| 771 | |
Stefan Tauner | ac1b4c8 | 2012-02-17 14:51:04 +0000 | [diff] [blame] | 772 | erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) |
| 773 | { |
| 774 | switch(opcode){ |
| 775 | case 0xff: |
| 776 | case 0x00: |
| 777 | /* Not specified, assuming "not supported". */ |
| 778 | return NULL; |
| 779 | case 0x20: |
| 780 | return &spi_block_erase_20; |
| 781 | case 0x52: |
| 782 | return &spi_block_erase_52; |
| 783 | case 0x60: |
| 784 | return &spi_block_erase_60; |
| 785 | case 0xc7: |
| 786 | return &spi_block_erase_c7; |
| 787 | case 0xd7: |
| 788 | return &spi_block_erase_d7; |
| 789 | case 0xd8: |
| 790 | return &spi_block_erase_d8; |
| 791 | default: |
| 792 | msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " |
| 793 | "this at flashrom@flashrom.org\n", __func__, opcode); |
| 794 | return NULL; |
| 795 | } |
| 796 | } |
| 797 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 798 | int spi_write_status_enable(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 799 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 800 | static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 801 | int result; |
| 802 | |
| 803 | /* Send EWSR (Enable Write Status Register). */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 804 | result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 805 | |
| 806 | if (result) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 807 | msg_cerr("%s failed\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 808 | |
| 809 | return result; |
| 810 | } |
| 811 | |
| 812 | /* |
| 813 | * This is according the SST25VF016 datasheet, who knows it is more |
| 814 | * generic that this... |
| 815 | */ |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 816 | static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 817 | { |
| 818 | int result; |
Carl-Daniel Hailfinger | 174f55b | 2010-10-08 00:37:55 +0000 | [diff] [blame] | 819 | int i = 0; |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 820 | /* |
| 821 | * WRSR requires either EWSR or WREN depending on chip type. |
| 822 | * The code below relies on the fact hat EWSR and WREN have the same |
| 823 | * INSIZE and OUTSIZE. |
Carl-Daniel Hailfinger | 174f55b | 2010-10-08 00:37:55 +0000 | [diff] [blame] | 824 | */ |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 825 | struct spi_command cmds[] = { |
| 826 | { |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 827 | .writecnt = JEDEC_WREN_OUTSIZE, |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 828 | .writearr = (const unsigned char[]){ enable_opcode }, |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 829 | .readcnt = 0, |
| 830 | .readarr = NULL, |
| 831 | }, { |
| 832 | .writecnt = JEDEC_WRSR_OUTSIZE, |
| 833 | .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, |
| 834 | .readcnt = 0, |
| 835 | .readarr = NULL, |
| 836 | }, { |
| 837 | .writecnt = 0, |
| 838 | .writearr = NULL, |
| 839 | .readcnt = 0, |
| 840 | .readarr = NULL, |
| 841 | }}; |
| 842 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 843 | result = spi_send_multicommand(flash, cmds); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 844 | if (result) { |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 845 | msg_cerr("%s failed during command execution\n", __func__); |
Carl-Daniel Hailfinger | 174f55b | 2010-10-08 00:37:55 +0000 | [diff] [blame] | 846 | /* No point in waiting for the command to complete if execution |
| 847 | * failed. |
| 848 | */ |
| 849 | return result; |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 850 | } |
Carl-Daniel Hailfinger | 174f55b | 2010-10-08 00:37:55 +0000 | [diff] [blame] | 851 | /* WRSR performs a self-timed erase before the changes take effect. |
| 852 | * This may take 50-85 ms in most cases, and some chips apparently |
| 853 | * allow running RDSR only once. Therefore pick an initial delay of |
| 854 | * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. |
| 855 | */ |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 856 | programmer_delay(100 * 1000); |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 857 | while (spi_read_status_register(flash) & SPI_SR_WIP) { |
Carl-Daniel Hailfinger | 174f55b | 2010-10-08 00:37:55 +0000 | [diff] [blame] | 858 | if (++i > 490) { |
| 859 | msg_cerr("Error: WIP bit after WRSR never cleared\n"); |
| 860 | return TIMEOUT_ERROR; |
| 861 | } |
| 862 | programmer_delay(10 * 1000); |
| 863 | } |
| 864 | return 0; |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 865 | } |
| 866 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 867 | int spi_write_status_register(struct flashctx *flash, int status) |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 868 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 869 | int feature_bits = flash->chip->feature_bits; |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 870 | int ret = 1; |
| 871 | |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 872 | if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) { |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 873 | msg_cdbg("Missing status register write definition, assuming " |
| 874 | "EWSR is needed\n"); |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 875 | feature_bits |= FEATURE_WRSR_EWSR; |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 876 | } |
Stefan Tauner | 96c2dfc | 2012-05-02 20:08:01 +0000 | [diff] [blame] | 877 | if (feature_bits & FEATURE_WRSR_WREN) |
| 878 | ret = spi_write_status_register_flag(flash, status, JEDEC_WREN); |
| 879 | if (ret && (feature_bits & FEATURE_WRSR_EWSR)) |
| 880 | ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 881 | return ret; |
| 882 | } |
| 883 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 884 | int spi_byte_program(struct flashctx *flash, unsigned int addr, |
| 885 | uint8_t databyte) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 886 | { |
| 887 | int result; |
| 888 | struct spi_command cmds[] = { |
| 889 | { |
| 890 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 891 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 892 | .readcnt = 0, |
| 893 | .readarr = NULL, |
| 894 | }, { |
| 895 | .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, |
| 896 | .writearr = (const unsigned char[]){ |
| 897 | JEDEC_BYTE_PROGRAM, |
| 898 | (addr >> 16) & 0xff, |
| 899 | (addr >> 8) & 0xff, |
| 900 | (addr & 0xff), |
| 901 | databyte |
| 902 | }, |
| 903 | .readcnt = 0, |
| 904 | .readarr = NULL, |
| 905 | }, { |
| 906 | .writecnt = 0, |
| 907 | .writearr = NULL, |
| 908 | .readcnt = 0, |
| 909 | .readarr = NULL, |
| 910 | }}; |
| 911 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 912 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 913 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 914 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 915 | __func__, addr); |
| 916 | } |
| 917 | return result; |
| 918 | } |
| 919 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 920 | int spi_nbyte_program(struct flashctx *flash, unsigned int addr, uint8_t *bytes, |
| 921 | unsigned int len) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 922 | { |
| 923 | int result; |
| 924 | /* FIXME: Switch to malloc based on len unless that kills speed. */ |
| 925 | unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { |
| 926 | JEDEC_BYTE_PROGRAM, |
| 927 | (addr >> 16) & 0xff, |
| 928 | (addr >> 8) & 0xff, |
| 929 | (addr >> 0) & 0xff, |
| 930 | }; |
| 931 | struct spi_command cmds[] = { |
| 932 | { |
| 933 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 934 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 935 | .readcnt = 0, |
| 936 | .readarr = NULL, |
| 937 | }, { |
| 938 | .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, |
| 939 | .writearr = cmd, |
| 940 | .readcnt = 0, |
| 941 | .readarr = NULL, |
| 942 | }, { |
| 943 | .writecnt = 0, |
| 944 | .writearr = NULL, |
| 945 | .readcnt = 0, |
| 946 | .readarr = NULL, |
| 947 | }}; |
| 948 | |
| 949 | if (!len) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 950 | msg_cerr("%s called for zero-length write\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 951 | return 1; |
| 952 | } |
| 953 | if (len > 256) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 954 | msg_cerr("%s called for too long a write\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 955 | return 1; |
| 956 | } |
| 957 | |
| 958 | memcpy(&cmd[4], bytes, len); |
| 959 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 960 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 961 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 962 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 963 | __func__, addr); |
| 964 | } |
| 965 | return result; |
| 966 | } |
| 967 | |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 968 | /* A generic brute-force block protection disable works like this: |
| 969 | * Write 0x00 to the status register. Check if any locks are still set (that |
| 970 | * part is chip specific). Repeat once. |
| 971 | */ |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 972 | int spi_disable_blockprotect(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 973 | { |
| 974 | uint8_t status; |
| 975 | int result; |
| 976 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 977 | status = spi_read_status_register(flash); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 978 | /* If block protection is disabled, stop here. */ |
| 979 | if ((status & 0x3c) == 0) |
| 980 | return 0; |
| 981 | |
Stefan Tauner | 87fbb77 | 2012-08-02 23:56:49 +0000 | [diff] [blame] | 982 | msg_cdbg("Some block protection in effect, disabling... "); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 983 | result = spi_write_status_register(flash, status & ~0x3c); |
| 984 | if (result) { |
Stefan Tauner | 87fbb77 | 2012-08-02 23:56:49 +0000 | [diff] [blame] | 985 | msg_cerr("spi_write_status_register failed.\n"); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 986 | return result; |
| 987 | } |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 988 | status = spi_read_status_register(flash); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 989 | if ((status & 0x3c) != 0) { |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 990 | msg_cerr("Block protection could not be disabled!\n"); |
| 991 | return 1; |
| 992 | } |
Stefan Tauner | 87fbb77 | 2012-08-02 23:56:49 +0000 | [diff] [blame] | 993 | msg_cdbg("done.\n"); |
Carl-Daniel Hailfinger | fd7075a | 2010-07-29 13:09:18 +0000 | [diff] [blame] | 994 | return 0; |
| 995 | } |
| 996 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 997 | int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, |
| 998 | unsigned int len) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 999 | { |
| 1000 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = { |
| 1001 | JEDEC_READ, |
| 1002 | (address >> 16) & 0xff, |
| 1003 | (address >> 8) & 0xff, |
| 1004 | (address >> 0) & 0xff, |
| 1005 | }; |
| 1006 | |
| 1007 | /* Send Read */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1008 | return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1009 | } |
| 1010 | |
| 1011 | /* |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1012 | * Read a part of the flash chip. |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1013 | * FIXME: Use the chunk code from Michael Karcher instead. |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1014 | * Each page is read separately in chunks with a maximum size of chunksize. |
| 1015 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1016 | int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 1017 | unsigned int len, unsigned int chunksize) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1018 | { |
| 1019 | int rc = 0; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 1020 | unsigned int i, j, starthere, lenhere, toread; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1021 | unsigned int page_size = flash->chip->page_size; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1022 | |
| 1023 | /* Warning: This loop has a very unusual condition and body. |
| 1024 | * The loop needs to go through each page with at least one affected |
| 1025 | * byte. The lowest page number is (start / page_size) since that |
| 1026 | * division rounds down. The highest page number we want is the page |
| 1027 | * where the last byte of the range lives. That last byte has the |
| 1028 | * address (start + len - 1), thus the highest page number is |
| 1029 | * (start + len - 1) / page_size. Since we want to include that last |
| 1030 | * page as well, the loop condition uses <=. |
| 1031 | */ |
| 1032 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 1033 | /* Byte position of the first byte in the range in this page. */ |
| 1034 | /* starthere is an offset to the base address of the chip. */ |
| 1035 | starthere = max(start, i * page_size); |
| 1036 | /* Length of bytes in the range in this page. */ |
| 1037 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
| 1038 | for (j = 0; j < lenhere; j += chunksize) { |
| 1039 | toread = min(chunksize, lenhere - j); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1040 | rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1041 | if (rc) |
| 1042 | break; |
| 1043 | } |
| 1044 | if (rc) |
| 1045 | break; |
| 1046 | } |
| 1047 | |
| 1048 | return rc; |
| 1049 | } |
| 1050 | |
| 1051 | /* |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1052 | * Write a part of the flash chip. |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1053 | * FIXME: Use the chunk code from Michael Karcher instead. |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1054 | * Each page is written separately in chunks with a maximum size of chunksize. |
| 1055 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1056 | int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 1057 | unsigned int len, unsigned int chunksize) |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1058 | { |
| 1059 | int rc = 0; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 1060 | unsigned int i, j, starthere, lenhere, towrite; |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1061 | /* FIXME: page_size is the wrong variable. We need max_writechunk_size |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 1062 | * in struct flashctx to do this properly. All chips using |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1063 | * spi_chip_write_256 have page_size set to max_writechunk_size, so |
| 1064 | * we're OK for now. |
| 1065 | */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1066 | unsigned int page_size = flash->chip->page_size; |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1067 | |
| 1068 | /* Warning: This loop has a very unusual condition and body. |
| 1069 | * The loop needs to go through each page with at least one affected |
| 1070 | * byte. The lowest page number is (start / page_size) since that |
| 1071 | * division rounds down. The highest page number we want is the page |
| 1072 | * where the last byte of the range lives. That last byte has the |
| 1073 | * address (start + len - 1), thus the highest page number is |
| 1074 | * (start + len - 1) / page_size. Since we want to include that last |
| 1075 | * page as well, the loop condition uses <=. |
| 1076 | */ |
| 1077 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 1078 | /* Byte position of the first byte in the range in this page. */ |
| 1079 | /* starthere is an offset to the base address of the chip. */ |
| 1080 | starthere = max(start, i * page_size); |
| 1081 | /* Length of bytes in the range in this page. */ |
| 1082 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
| 1083 | for (j = 0; j < lenhere; j += chunksize) { |
| 1084 | towrite = min(chunksize, lenhere - j); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1085 | rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1086 | if (rc) |
| 1087 | break; |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 1088 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 1089 | programmer_delay(10); |
| 1090 | } |
| 1091 | if (rc) |
| 1092 | break; |
| 1093 | } |
| 1094 | |
| 1095 | return rc; |
| 1096 | } |
| 1097 | |
| 1098 | /* |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1099 | * Program chip using byte programming. (SLOW!) |
| 1100 | * This is for chips which can only handle one byte writes |
| 1101 | * and for chips where memory mapped programming is impossible |
| 1102 | * (e.g. due to size constraints in IT87* for over 512 kB) |
| 1103 | */ |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1104 | /* real chunksize is 1, logical chunksize is 1 */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1105 | int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 1106 | unsigned int len) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1107 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 1108 | unsigned int i; |
| 1109 | int result = 0; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1110 | |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1111 | for (i = start; i < start + len; i++) { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1112 | result = spi_byte_program(flash, i, buf[i - start]); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1113 | if (result) |
| 1114 | return 1; |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 1115 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1116 | programmer_delay(10); |
| 1117 | } |
| 1118 | |
| 1119 | return 0; |
| 1120 | } |
| 1121 | |
Nico Huber | 7bca126 | 2012-06-15 22:28:12 +0000 | [diff] [blame] | 1122 | int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1123 | { |
| 1124 | uint32_t pos = start; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1125 | int result; |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1126 | unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { |
| 1127 | JEDEC_AAI_WORD_PROGRAM, |
| 1128 | }; |
| 1129 | struct spi_command cmds[] = { |
| 1130 | { |
| 1131 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 1132 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 1133 | .readcnt = 0, |
| 1134 | .readarr = NULL, |
| 1135 | }, { |
| 1136 | .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, |
| 1137 | .writearr = (const unsigned char[]){ |
| 1138 | JEDEC_AAI_WORD_PROGRAM, |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1139 | (start >> 16) & 0xff, |
| 1140 | (start >> 8) & 0xff, |
| 1141 | (start & 0xff), |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1142 | buf[0], |
| 1143 | buf[1] |
| 1144 | }, |
| 1145 | .readcnt = 0, |
| 1146 | .readarr = NULL, |
| 1147 | }, { |
| 1148 | .writecnt = 0, |
| 1149 | .writearr = NULL, |
| 1150 | .readcnt = 0, |
| 1151 | .readarr = NULL, |
| 1152 | }}; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1153 | |
Carl-Daniel Hailfinger | c40cff7 | 2011-12-20 00:19:29 +0000 | [diff] [blame] | 1154 | switch (flash->pgm->spi.type) { |
Carl-Daniel Hailfinger | 7112772 | 2010-05-31 15:27:27 +0000 | [diff] [blame] | 1155 | #if CONFIG_INTERNAL == 1 |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1156 | #if defined(__i386__) || defined(__x86_64__) |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1157 | case SPI_CONTROLLER_IT87XX: |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1158 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1159 | msg_perr("%s: impossible with this SPI controller," |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1160 | " degrading to byte program\n", __func__); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1161 | return spi_chip_write_1(flash, buf, start, len); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1162 | #endif |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1163 | #endif |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1164 | default: |
| 1165 | break; |
| 1166 | } |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1167 | |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1168 | /* The even start address and even length requirements can be either |
| 1169 | * honored outside this function, or we can call spi_byte_program |
| 1170 | * for the first and/or last byte and use AAI for the rest. |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1171 | * FIXME: Move this to generic code. |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1172 | */ |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1173 | /* The data sheet requires a start address with the low bit cleared. */ |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1174 | if (start % 2) { |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1175 | msg_cerr("%s: start address not even! Please report a bug at " |
| 1176 | "flashrom@flashrom.org\n", __func__); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1177 | if (spi_chip_write_1(flash, buf, start, start % 2)) |
| 1178 | return SPI_GENERIC_ERROR; |
| 1179 | pos += start % 2; |
Carl-Daniel Hailfinger | ccfe0ac | 2010-10-27 22:07:11 +0000 | [diff] [blame] | 1180 | cmds[1].writearr = (const unsigned char[]){ |
| 1181 | JEDEC_AAI_WORD_PROGRAM, |
| 1182 | (pos >> 16) & 0xff, |
| 1183 | (pos >> 8) & 0xff, |
| 1184 | (pos & 0xff), |
| 1185 | buf[pos - start], |
| 1186 | buf[pos - start + 1] |
| 1187 | }; |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1188 | /* Do not return an error for now. */ |
| 1189 | //return SPI_GENERIC_ERROR; |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1190 | } |
| 1191 | /* The data sheet requires total AAI write length to be even. */ |
| 1192 | if (len % 2) { |
| 1193 | msg_cerr("%s: total write length not even! Please report a " |
| 1194 | "bug at flashrom@flashrom.org\n", __func__); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1195 | /* Do not return an error for now. */ |
| 1196 | //return SPI_GENERIC_ERROR; |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1197 | } |
| 1198 | |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1199 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1200 | result = spi_send_multicommand(flash, cmds); |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1201 | if (result) { |
| 1202 | msg_cerr("%s failed during start command execution\n", |
| 1203 | __func__); |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 1204 | /* FIXME: Should we send WRDI here as well to make sure the chip |
| 1205 | * is not in AAI mode? |
| 1206 | */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1207 | return result; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1208 | } |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 1209 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1210 | programmer_delay(10); |
| 1211 | |
| 1212 | /* We already wrote 2 bytes in the multicommand step. */ |
| 1213 | pos += 2; |
| 1214 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1215 | /* Are there at least two more bytes to write? */ |
| 1216 | while (pos < start + len - 1) { |
Carl-Daniel Hailfinger | ccfe0ac | 2010-10-27 22:07:11 +0000 | [diff] [blame] | 1217 | cmd[1] = buf[pos++ - start]; |
| 1218 | cmd[2] = buf[pos++ - start]; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1219 | spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, |
| 1220 | cmd, NULL); |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 1221 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1222 | programmer_delay(10); |
| 1223 | } |
| 1224 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1225 | /* Use WRDI to exit AAI mode. This needs to be done before issuing any |
| 1226 | * other non-AAI command. |
| 1227 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1228 | spi_write_disable(flash); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1229 | |
| 1230 | /* Write remaining byte (if any). */ |
| 1231 | if (pos < start + len) { |
Carl-Daniel Hailfinger | ccfe0ac | 2010-10-27 22:07:11 +0000 | [diff] [blame] | 1232 | if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2)) |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1233 | return SPI_GENERIC_ERROR; |
| 1234 | pos += pos % 2; |
| 1235 | } |
| 1236 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1237 | return 0; |
| 1238 | } |