blob: 640769522a38367b2cafd7f6ec7427a2276f2457 [file] [log] [blame]
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __PROGRAMMER_H__
25#define __PROGRAMMER_H__ 1
26
27enum programmer {
28#if CONFIG_INTERNAL == 1
29 PROGRAMMER_INTERNAL,
30#endif
31#if CONFIG_DUMMY == 1
32 PROGRAMMER_DUMMY,
33#endif
34#if CONFIG_NIC3COM == 1
35 PROGRAMMER_NIC3COM,
36#endif
37#if CONFIG_NICREALTEK == 1
38 PROGRAMMER_NICREALTEK,
39 PROGRAMMER_NICREALTEK2,
Idwer Vollering004f4b72010-09-03 18:21:21 +000040#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000041#if CONFIG_NICNATSEMI == 1
42 PROGRAMMER_NICNATSEMI,
Idwer Vollering004f4b72010-09-03 18:21:21 +000043#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000044#if CONFIG_GFXNVIDIA == 1
45 PROGRAMMER_GFXNVIDIA,
46#endif
47#if CONFIG_DRKAISER == 1
48 PROGRAMMER_DRKAISER,
49#endif
50#if CONFIG_SATASII == 1
51 PROGRAMMER_SATASII,
52#endif
53#if CONFIG_ATAHPT == 1
54 PROGRAMMER_ATAHPT,
55#endif
56#if CONFIG_INTERNAL == 1
57#if defined(__i386__) || defined(__x86_64__)
58 PROGRAMMER_IT87SPI,
59#endif
60#endif
61#if CONFIG_FT2232_SPI == 1
62 PROGRAMMER_FT2232_SPI,
63#endif
64#if CONFIG_SERPROG == 1
65 PROGRAMMER_SERPROG,
66#endif
67#if CONFIG_BUSPIRATE_SPI == 1
68 PROGRAMMER_BUSPIRATE_SPI,
69#endif
70#if CONFIG_DEDIPROG == 1
71 PROGRAMMER_DEDIPROG,
72#endif
73#if CONFIG_RAYER_SPI == 1
74 PROGRAMMER_RAYER_SPI,
75#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +000076#if CONFIG_NICINTEL_SPI == 1
77 PROGRAMMER_NICINTEL_SPI,
78#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000079 PROGRAMMER_INVALID /* This must always be the last entry. */
80};
81
82extern enum programmer programmer;
83
84struct programmer_entry {
85 const char *vendor;
86 const char *name;
87
88 int (*init) (void);
89 int (*shutdown) (void);
90
91 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,
92 size_t len);
93 void (*unmap_flash_region) (void *virt_addr, size_t len);
94
95 void (*chip_writeb) (uint8_t val, chipaddr addr);
96 void (*chip_writew) (uint16_t val, chipaddr addr);
97 void (*chip_writel) (uint32_t val, chipaddr addr);
98 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
99 uint8_t (*chip_readb) (const chipaddr addr);
100 uint16_t (*chip_readw) (const chipaddr addr);
101 uint32_t (*chip_readl) (const chipaddr addr);
102 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
103 void (*delay) (int usecs);
104};
105
106extern const struct programmer_entry programmer_table[];
107
108int programmer_init(char *param);
109int programmer_shutdown(void);
110
111enum bitbang_spi_master_type {
112 BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */
113#if CONFIG_RAYER_SPI == 1
114 BITBANG_SPI_MASTER_RAYER,
115#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000116#if CONFIG_NICINTEL_SPI == 1
117 BITBANG_SPI_MASTER_NICINTEL,
118#endif
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000119#if CONFIG_INTERNAL == 1
120#if defined(__i386__) || defined(__x86_64__)
121 BITBANG_SPI_MASTER_MCP,
122#endif
123#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000124};
125
126struct bitbang_spi_master {
127 enum bitbang_spi_master_type type;
128
129 /* Note that CS# is active low, so val=0 means the chip is active. */
130 void (*set_cs) (int val);
131 void (*set_sck) (int val);
132 void (*set_mosi) (int val);
133 int (*get_miso) (void);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000134 void (*request_bus) (void);
135 void (*release_bus) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000136};
137
138#if CONFIG_INTERNAL == 1
139struct penable {
140 uint16_t vendor_id;
141 uint16_t device_id;
142 int status;
143 const char *vendor_name;
144 const char *device_name;
145 int (*doit) (struct pci_dev *dev, const char *name);
146};
147
148extern const struct penable chipset_enables[];
149
150struct board_pciid_enable {
151 /* Any device, but make it sensible, like the ISA bridge. */
152 uint16_t first_vendor;
153 uint16_t first_device;
154 uint16_t first_card_vendor;
155 uint16_t first_card_device;
156
157 /* Any device, but make it sensible, like
158 * the host bridge. May be NULL.
159 */
160 uint16_t second_vendor;
161 uint16_t second_device;
162 uint16_t second_card_vendor;
163 uint16_t second_card_device;
164
165 /* Pattern to match DMI entries */
166 const char *dmi_pattern;
167
168 /* The vendor / part name from the coreboot table. */
169 const char *lb_vendor;
170 const char *lb_part;
171
172 const char *vendor_name;
173 const char *board_name;
174
175 int max_rom_decode_parallel;
176 int status;
177 int (*enable) (void);
178};
179
180extern const struct board_pciid_enable board_pciid_enables[];
181
182struct board_info {
183 const char *vendor;
184 const char *name;
185 const int working;
186#ifdef CONFIG_PRINT_WIKI
187 const char *url;
188 const char *note;
189#endif
190};
191
192extern const struct board_info boards_known[];
193extern const struct board_info laptops_known[];
194#endif
195
196/* udelay.c */
197void myusec_delay(int usecs);
198void myusec_calibrate_delay(void);
199void internal_delay(int usecs);
200
201#if NEED_PCI == 1
202/* pcidev.c */
203extern uint32_t io_base_addr;
204extern struct pci_access *pacc;
205extern struct pci_dev *pcidev_dev;
206struct pcidev_status {
207 uint16_t vendor_id;
208 uint16_t device_id;
209 int status;
210 const char *vendor_name;
211 const char *device_name;
212};
213uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs);
214uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs);
215#endif
216
217/* print.c */
Idwer Vollering004f4b72010-09-03 18:21:21 +0000218#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI >= 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000219void print_supported_pcidevs(const struct pcidev_status *devs);
220#endif
221
222/* board_enable.c */
223void w836xx_ext_enter(uint16_t port);
224void w836xx_ext_leave(uint16_t port);
225int it8705f_write_enable(uint8_t port);
226uint8_t sio_read(uint16_t port, uint8_t reg);
227void sio_write(uint16_t port, uint8_t reg, uint8_t data);
228void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
229int board_flash_enable(const char *vendor, const char *part);
230
231/* chipset_enable.c */
232int chipset_flash_enable(void);
233
234/* processor_enable.c */
235int processor_flash_enable(void);
236
237/* physmap.c */
238void *physmap(const char *descr, unsigned long phys_addr, size_t len);
239void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);
240void physunmap(void *virt_addr, size_t len);
241int setup_cpu_msr(int cpu);
242void cleanup_cpu_msr(void);
243
244/* cbtable.c */
245void lb_vendor_dev_from_string(char *boardstring);
246int coreboot_init(void);
247extern char *lb_part, *lb_vendor;
248extern int partvendor_from_cbtable;
249
250/* dmi.c */
251extern int has_dmi_support;
252void dmi_init(void);
253int dmi_match(const char *pattern);
254
255/* internal.c */
256#if NEED_PCI == 1
257struct superio {
258 uint16_t vendor;
259 uint16_t port;
260 uint16_t model;
261};
262extern struct superio superio;
263#define SUPERIO_VENDOR_NONE 0x0
264#define SUPERIO_VENDOR_ITE 0x1
265struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
266struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class);
267struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
268struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
269 uint16_t card_vendor, uint16_t card_device);
270#endif
271void get_io_perms(void);
272void release_io_perms(void);
273#if CONFIG_INTERNAL == 1
274extern int is_laptop;
275extern int force_boardenable;
276extern int force_boardmismatch;
277void probe_superio(void);
278int internal_init(void);
279int internal_shutdown(void);
280void internal_chip_writeb(uint8_t val, chipaddr addr);
281void internal_chip_writew(uint16_t val, chipaddr addr);
282void internal_chip_writel(uint32_t val, chipaddr addr);
283uint8_t internal_chip_readb(const chipaddr addr);
284uint16_t internal_chip_readw(const chipaddr addr);
285uint32_t internal_chip_readl(const chipaddr addr);
286void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
287#endif
288
289/* hwaccess.c */
290void mmio_writeb(uint8_t val, void *addr);
291void mmio_writew(uint16_t val, void *addr);
292void mmio_writel(uint32_t val, void *addr);
293uint8_t mmio_readb(void *addr);
294uint16_t mmio_readw(void *addr);
295uint32_t mmio_readl(void *addr);
296void mmio_le_writeb(uint8_t val, void *addr);
297void mmio_le_writew(uint16_t val, void *addr);
298void mmio_le_writel(uint32_t val, void *addr);
299uint8_t mmio_le_readb(void *addr);
300uint16_t mmio_le_readw(void *addr);
301uint32_t mmio_le_readl(void *addr);
302#define pci_mmio_writeb mmio_le_writeb
303#define pci_mmio_writew mmio_le_writew
304#define pci_mmio_writel mmio_le_writel
305#define pci_mmio_readb mmio_le_readb
306#define pci_mmio_readw mmio_le_readw
307#define pci_mmio_readl mmio_le_readl
308
309/* programmer.c */
310int noop_shutdown(void);
311void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);
312void fallback_unmap(void *virt_addr, size_t len);
313uint8_t noop_chip_readb(const chipaddr addr);
314void noop_chip_writeb(uint8_t val, chipaddr addr);
315void fallback_chip_writew(uint16_t val, chipaddr addr);
316void fallback_chip_writel(uint32_t val, chipaddr addr);
317void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
318uint16_t fallback_chip_readw(const chipaddr addr);
319uint32_t fallback_chip_readl(const chipaddr addr);
320void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
321
322/* dummyflasher.c */
323#if CONFIG_DUMMY == 1
324int dummy_init(void);
325int dummy_shutdown(void);
326void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);
327void dummy_unmap(void *virt_addr, size_t len);
328void dummy_chip_writeb(uint8_t val, chipaddr addr);
329void dummy_chip_writew(uint16_t val, chipaddr addr);
330void dummy_chip_writel(uint32_t val, chipaddr addr);
331void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
332uint8_t dummy_chip_readb(const chipaddr addr);
333uint16_t dummy_chip_readw(const chipaddr addr);
334uint32_t dummy_chip_readl(const chipaddr addr);
335void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
336int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
337 const unsigned char *writearr, unsigned char *readarr);
338int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
339int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
340#endif
341
342/* nic3com.c */
343#if CONFIG_NIC3COM == 1
344int nic3com_init(void);
345int nic3com_shutdown(void);
346void nic3com_chip_writeb(uint8_t val, chipaddr addr);
347uint8_t nic3com_chip_readb(const chipaddr addr);
348extern const struct pcidev_status nics_3com[];
349#endif
350
351/* gfxnvidia.c */
352#if CONFIG_GFXNVIDIA == 1
353int gfxnvidia_init(void);
354int gfxnvidia_shutdown(void);
355void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr);
356uint8_t gfxnvidia_chip_readb(const chipaddr addr);
357extern const struct pcidev_status gfx_nvidia[];
358#endif
359
360/* drkaiser.c */
361#if CONFIG_DRKAISER == 1
362int drkaiser_init(void);
363int drkaiser_shutdown(void);
364void drkaiser_chip_writeb(uint8_t val, chipaddr addr);
365uint8_t drkaiser_chip_readb(const chipaddr addr);
366extern const struct pcidev_status drkaiser_pcidev[];
367#endif
368
369/* nicrealtek.c */
370#if CONFIG_NICREALTEK == 1
371int nicrealtek_init(void);
372int nicsmc1211_init(void);
373int nicrealtek_shutdown(void);
374void nicrealtek_chip_writeb(uint8_t val, chipaddr addr);
375uint8_t nicrealtek_chip_readb(const chipaddr addr);
376extern const struct pcidev_status nics_realtek[];
377extern const struct pcidev_status nics_realteksmc1211[];
378#endif
379
380/* nicnatsemi.c */
381#if CONFIG_NICNATSEMI == 1
382int nicnatsemi_init(void);
383int nicnatsemi_shutdown(void);
384void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr);
385uint8_t nicnatsemi_chip_readb(const chipaddr addr);
386extern const struct pcidev_status nics_natsemi[];
387#endif
388
Idwer Vollering004f4b72010-09-03 18:21:21 +0000389/* nicintel_spi.c */
390#if CONFIG_NICINTEL_SPI == 1
391int nicintel_spi_init(void);
392int nicintel_spi_shutdown(void);
393int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt,
394 const unsigned char *writearr, unsigned char *readarr);
395void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr);
396extern const struct pcidev_status nics_intel_spi[];
397#endif
398
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000399/* satasii.c */
400#if CONFIG_SATASII == 1
401int satasii_init(void);
402int satasii_shutdown(void);
403void satasii_chip_writeb(uint8_t val, chipaddr addr);
404uint8_t satasii_chip_readb(const chipaddr addr);
405extern const struct pcidev_status satas_sii[];
406#endif
407
408/* atahpt.c */
409#if CONFIG_ATAHPT == 1
410int atahpt_init(void);
411int atahpt_shutdown(void);
412void atahpt_chip_writeb(uint8_t val, chipaddr addr);
413uint8_t atahpt_chip_readb(const chipaddr addr);
414extern const struct pcidev_status ata_hpt[];
415#endif
416
417/* ft2232_spi.c */
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000418#if CONFIG_FT2232_SPI == 1
419struct usbdev_status {
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000420 uint16_t vendor_id;
421 uint16_t device_id;
422 int status;
423 const char *vendor_name;
424 const char *device_name;
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000425};
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000426int ft2232_spi_init(void);
427int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
428int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
429int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000430extern const struct usbdev_status devs_ft2232spi[];
431void print_supported_usbdevs(const struct usbdev_status *devs);
432#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000433
434/* rayer_spi.c */
435#if CONFIG_RAYER_SPI == 1
436int rayer_spi_init(void);
437#endif
438
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000439/* mcp6x_spi.c */
440#if CONFIG_INTERNAL == 1
441#if defined(__i386__) || defined(__x86_64__)
442int mcp6x_spi_init(int want_spi);
443#endif
444#endif
445
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000446/* bitbang_spi.c */
447int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000448int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000449int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
450int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
451int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
452
453/* buspirate_spi.c */
454struct buspirate_spispeeds {
455 const char *name;
456 const int speed;
457};
458int buspirate_spi_init(void);
459int buspirate_spi_shutdown(void);
460int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
461int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
462int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
463
464/* dediprog.c */
465int dediprog_init(void);
466int dediprog_shutdown(void);
467int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
468int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
469
470/* flashrom.c */
471struct decode_sizes {
472 uint32_t parallel;
473 uint32_t lpc;
474 uint32_t fwh;
475 uint32_t spi;
476};
477extern struct decode_sizes max_rom_decode;
478extern int programmer_may_write;
479extern unsigned long flashbase;
480void check_chip_supported(struct flashchip *flash);
481int check_max_decode(enum chipbustype buses, uint32_t size);
482char *extract_programmer_param(char *param_name);
483
484/* layout.c */
485int show_id(uint8_t *bios, int size, int force);
486
487/* spi.c */
488enum spi_controller {
489 SPI_CONTROLLER_NONE,
490#if CONFIG_INTERNAL == 1
491#if defined(__i386__) || defined(__x86_64__)
492 SPI_CONTROLLER_ICH7,
493 SPI_CONTROLLER_ICH9,
494 SPI_CONTROLLER_IT87XX,
495 SPI_CONTROLLER_SB600,
496 SPI_CONTROLLER_VIA,
497 SPI_CONTROLLER_WBSIO,
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000498 SPI_CONTROLLER_MCP6X_BITBANG,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000499#endif
500#endif
501#if CONFIG_FT2232_SPI == 1
502 SPI_CONTROLLER_FT2232,
503#endif
504#if CONFIG_DUMMY == 1
505 SPI_CONTROLLER_DUMMY,
506#endif
507#if CONFIG_BUSPIRATE_SPI == 1
508 SPI_CONTROLLER_BUSPIRATE,
509#endif
510#if CONFIG_DEDIPROG == 1
511 SPI_CONTROLLER_DEDIPROG,
512#endif
513#if CONFIG_RAYER_SPI == 1
514 SPI_CONTROLLER_RAYER,
515#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000516#if CONFIG_NICINTEL_SPI == 1
517 SPI_CONTROLLER_NICINTEL,
518#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000519 SPI_CONTROLLER_INVALID /* This must always be the last entry. */
520};
521extern const int spi_programmer_count;
522struct spi_programmer {
523 int (*command)(unsigned int writecnt, unsigned int readcnt,
524 const unsigned char *writearr, unsigned char *readarr);
525 int (*multicommand)(struct spi_command *cmds);
526
527 /* Optimized functions for this programmer */
528 int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len);
529 int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);
530};
531
532extern enum spi_controller spi_controller;
533extern const struct spi_programmer spi_programmer[];
534int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
535 const unsigned char *writearr, unsigned char *readarr);
536int default_spi_send_multicommand(struct spi_command *cmds);
537
538/* ichspi.c */
539#if CONFIG_INTERNAL == 1
540extern uint32_t ichspi_bbar;
541int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
542 int ich_generation);
543int via_init_spi(struct pci_dev *dev);
544int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
545 const unsigned char *writearr, unsigned char *readarr);
546int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
547int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len);
548int ich_spi_send_multicommand(struct spi_command *cmds);
549#endif
550
551/* it87spi.c */
552void enter_conf_mode_ite(uint16_t port);
553void exit_conf_mode_ite(uint16_t port);
554struct superio probe_superio_ite(void);
555int init_superio_ite(void);
556int it87spi_init(void);
557int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
558 const unsigned char *writearr, unsigned char *readarr);
559int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len);
560int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
561
562/* sb600spi.c */
563#if CONFIG_INTERNAL == 1
564int sb600_probe_spi(struct pci_dev *dev);
565int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
566 const unsigned char *writearr, unsigned char *readarr);
567int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
568int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
569#endif
570
571/* wbsio_spi.c */
572#if CONFIG_INTERNAL == 1
573int wbsio_check_for_spi(void);
574int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
575 const unsigned char *writearr, unsigned char *readarr);
576int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
577#endif
578
579/* serprog.c */
580int serprog_init(void);
581int serprog_shutdown(void);
582void serprog_chip_writeb(uint8_t val, chipaddr addr);
583uint8_t serprog_chip_readb(const chipaddr addr);
584void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
585void serprog_delay(int delay);
586
587/* serial.c */
588#if _WIN32
589typedef HANDLE fdtype;
590#else
591typedef int fdtype;
592#endif
593
594void sp_flush_incoming(void);
595fdtype sp_openserport(char *dev, unsigned int baud);
596void __attribute__((noreturn)) sp_die(char *msg);
597extern fdtype sp_fd;
598int serialport_shutdown(void);
599int serialport_write(unsigned char *buf, unsigned int writecnt);
600int serialport_read(unsigned char *buf, unsigned int readcnt);
601
602#endif /* !__PROGRAMMER_H__ */