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Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Peter Lemenkov62829662012-12-29 19:26:55 +000021#define IS_X86 (defined(__i386__) || defined(__x86_64__) || defined(__amd64__))
22#define IS_MIPS (defined (__mips) || defined (__mips__) || defined (__MIPS__) || defined (mips))
23#define IS_PPC (defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__))
24#define IS_ARM (defined (__arm__) || defined (_ARM))
25#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM)
26#error Unknown architecture
27#endif
28
Peter Lemenkov62829662012-12-29 19:26:55 +000029#define IS_LINUX (defined(__gnu_linux__) || defined(__linux__))
Stefan Taunere038e902013-02-04 04:38:42 +000030#define IS_MACOSX (defined(__APPLE__) && defined(__MACH__))
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000031#if !(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun))
Peter Lemenkov62829662012-12-29 19:26:55 +000032#error "Unknown operating system"
33#endif
34
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000035#include <stdint.h>
36#include <string.h>
37#include <stdlib.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000038#include <sys/types.h>
Patrick Georgia9095a92010-09-30 17:03:32 +000039#if !defined (__DJGPP__) && !defined(__LIBPAYLOAD__)
Carl-Daniel Hailfinger831e8f42010-05-30 22:24:40 +000040#include <unistd.h>
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000041#include <fcntl.h>
Patrick Georgia9095a92010-09-30 17:03:32 +000042#endif
43#if !defined (__DJGPP__)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000044#include <errno.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000045#endif
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000046#include "flash.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000047#include "hwaccess.h"
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000048
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000049#define USE_IOPL (IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__))
50#define USE_DEV_IO (defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__))
51
52#if IS_X86 && USE_DEV_IO
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000053int io_fd;
54#endif
55
Peter Lemenkov62829662012-12-29 19:26:55 +000056/* Prevent reordering and/or merging of reads/writes to hardware.
57 * Such reordering and/or merging would break device accesses which depend on the exact access order.
58 */
59static inline void sync_primitive(void)
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000060{
Peter Lemenkov62829662012-12-29 19:26:55 +000061/* This is needed only on PowerPC because...
62 * - x86 uses uncached accesses which have a strongly ordered memory model and
63 * - MIPS uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model
64 * - ARM uses a strongly ordered memory model for device memories.
65 */
66#if IS_PPC
67 asm("eieio" : : : "memory");
68#endif
69}
70
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +000071#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
Peter Lemenkov62829662012-12-29 19:26:55 +000072static int release_io_perms(void *p)
73{
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +000074#if defined (__sun)
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000075 sysi86(SI86V86, V86SC_IOPL, 0);
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000076#elif USE_DEV_IO
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000077 close(io_fd);
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000078#elif USE_IOPL
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000079 iopl(0);
80#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000081 return 0;
82}
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +000083#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000084
85/* Get I/O permissions with automatic permission release on shutdown. */
86int rget_io_perms(void)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000087{
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +000088#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
89#if defined (__sun)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000090 if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000091#elif USE_DEV_IO
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000092 if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000093#elif USE_IOPL
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000094 if (iopl(3) != 0) {
95#endif
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000096 msg_perr("ERROR: Could not get I/O privileges (%s).\n", strerror(errno));
97 msg_perr("You need to be root.\n");
Carl-Daniel Hailfingerb63b0672010-07-02 17:12:50 +000098#if defined (__OpenBSD__)
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000099 msg_perr("If you are root already please set securelevel=-1 in /etc/rc.securelevel and\n"
100 "reboot, or reboot into single user mode.\n");
101#elif defined(__NetBSD__)
102 msg_perr("If you are root already please reboot into single user mode or make sure\n"
103 "that your kernel configuration has the option INSECURE enabled.\n");
Carl-Daniel Hailfingerb63b0672010-07-02 17:12:50 +0000104#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000105 return 1;
106 } else {
107 register_shutdown(release_io_perms, NULL);
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000108 }
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000109#else
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +0000110 /* DJGPP and libpayload environments have full PCI port I/O permissions by default. */
111 /* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000112#endif
Peter Lemenkov62829662012-12-29 19:26:55 +0000113 return 0;
114}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000115
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000116void mmio_writeb(uint8_t val, void *addr)
117{
118 *(volatile uint8_t *) addr = val;
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000119 sync_primitive();
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000120}
121
122void mmio_writew(uint16_t val, void *addr)
123{
124 *(volatile uint16_t *) addr = val;
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000125 sync_primitive();
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000126}
127
128void mmio_writel(uint32_t val, void *addr)
129{
130 *(volatile uint32_t *) addr = val;
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000131 sync_primitive();
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000132}
133
134uint8_t mmio_readb(void *addr)
135{
136 return *(volatile uint8_t *) addr;
137}
138
139uint16_t mmio_readw(void *addr)
140{
141 return *(volatile uint16_t *) addr;
142}
143
144uint32_t mmio_readl(void *addr)
145{
146 return *(volatile uint32_t *) addr;
147}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000148
Carl-Daniel Hailfingerccd71c22012-03-01 22:38:27 +0000149void mmio_readn(void *addr, uint8_t *buf, size_t len)
150{
151 memcpy(buf, addr, len);
152 return;
153}
154
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000155void mmio_le_writeb(uint8_t val, void *addr)
156{
157 mmio_writeb(cpu_to_le8(val), addr);
158}
159
160void mmio_le_writew(uint16_t val, void *addr)
161{
162 mmio_writew(cpu_to_le16(val), addr);
163}
164
165void mmio_le_writel(uint32_t val, void *addr)
166{
167 mmio_writel(cpu_to_le32(val), addr);
168}
169
170uint8_t mmio_le_readb(void *addr)
171{
172 return le_to_cpu8(mmio_readb(addr));
173}
174
175uint16_t mmio_le_readw(void *addr)
176{
177 return le_to_cpu16(mmio_readw(addr));
178}
179
180uint32_t mmio_le_readl(void *addr)
181{
182 return le_to_cpu32(mmio_readl(addr));
183}
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000184
185enum mmio_write_type {
186 mmio_write_type_b,
187 mmio_write_type_w,
188 mmio_write_type_l,
189};
190
191struct undo_mmio_write_data {
192 void *addr;
193 int reg;
194 enum mmio_write_type type;
195 union {
196 uint8_t bdata;
197 uint16_t wdata;
198 uint32_t ldata;
199 };
200};
201
David Hendricks8bb20212011-06-14 01:35:36 +0000202int undo_mmio_write(void *p)
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000203{
204 struct undo_mmio_write_data *data = p;
205 msg_pdbg("Restoring MMIO space at %p\n", data->addr);
206 switch (data->type) {
207 case mmio_write_type_b:
208 mmio_writeb(data->bdata, data->addr);
209 break;
210 case mmio_write_type_w:
211 mmio_writew(data->wdata, data->addr);
212 break;
213 case mmio_write_type_l:
214 mmio_writel(data->ldata, data->addr);
215 break;
216 }
217 /* p was allocated in register_undo_mmio_write. */
218 free(p);
David Hendricks8bb20212011-06-14 01:35:36 +0000219 return 0;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000220}
221
222#define register_undo_mmio_write(a, c) \
223{ \
224 struct undo_mmio_write_data *undo_mmio_write_data; \
225 undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \
Stefan Tauner269de352011-07-12 22:35:21 +0000226 if (!undo_mmio_write_data) { \
227 msg_gerr("Out of memory!\n"); \
228 exit(1); \
229 } \
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000230 undo_mmio_write_data->addr = a; \
231 undo_mmio_write_data->type = mmio_write_type_##c; \
232 undo_mmio_write_data->c##data = mmio_read##c(a); \
233 register_shutdown(undo_mmio_write, undo_mmio_write_data); \
234}
235
236#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b)
237#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w)
238#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l)
239
240void rmmio_writeb(uint8_t val, void *addr)
241{
242 register_undo_mmio_writeb(addr);
243 mmio_writeb(val, addr);
244}
245
246void rmmio_writew(uint16_t val, void *addr)
247{
248 register_undo_mmio_writew(addr);
249 mmio_writew(val, addr);
250}
251
252void rmmio_writel(uint32_t val, void *addr)
253{
254 register_undo_mmio_writel(addr);
255 mmio_writel(val, addr);
256}
257
258void rmmio_le_writeb(uint8_t val, void *addr)
259{
260 register_undo_mmio_writeb(addr);
261 mmio_le_writeb(val, addr);
262}
263
264void rmmio_le_writew(uint16_t val, void *addr)
265{
266 register_undo_mmio_writew(addr);
267 mmio_le_writew(val, addr);
268}
269
270void rmmio_le_writel(uint32_t val, void *addr)
271{
272 register_undo_mmio_writel(addr);
273 mmio_le_writel(val, addr);
274}
275
276void rmmio_valb(void *addr)
277{
278 register_undo_mmio_writeb(addr);
279}
280
281void rmmio_valw(void *addr)
282{
283 register_undo_mmio_writew(addr);
284}
285
286void rmmio_vall(void *addr)
287{
288 register_undo_mmio_writel(addr);
289}