tree cdb49567c3d7c2291fa33221989516afb1b03abf
parent 3f3c1f3238dcede30d0d15d36da6326b428b8b12
author Nico Huber <nico.h@gmx.de> 1653740766 +0200
committer Nico Huber <nico.h@gmx.de> 1672359411 +0100

flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L

These chips seem to be rather regular, supporting 2.7V..3.6V, the
common erase block sizes 4KiB, 32KiB, 64KiB and the usual block-
protection bits.

Status/configuration register naming differs from other vendors,
though. These chips have 2 status registers plus 3 configuration
registers. Configuration registers 1 & 2 match status registers
2 & 3 of what we are used from other vendors. Read opcodes match
too, however writes are always done through the WRSR instruction
which can write up to 4 bytes (SR1, CR1, CR2, CR3).

S25FL256L supports native 4BA commands and entering a 4BA mode.
However, it uses an unusual opcode (0x53) for the 32KiB 4BA block
erase.

Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>