flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L
These chips seem to be rather regular, supporting 2.7V..3.6V, the
common erase block sizes 4KiB, 32KiB, 64KiB and the usual block-
protection bits.
Status/configuration register naming differs from other vendors,
though. These chips have 2 status registers plus 3 configuration
registers. Configuration registers 1 & 2 match status registers
2 & 3 of what we are used from other vendors. Read opcodes match
too, however writes are always done through the WRSR instruction
which can write up to 4 bytes (SR1, CR1, CR2, CR3).
S25FL256L supports native 4BA commands and entering a 4BA mode.
However, it uses an unusual opcode (0x53) for the 32KiB 4BA block
erase.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70989
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/chipdrivers.h b/chipdrivers.h
index 776c8c3..149620a 100644
--- a/chipdrivers.h
+++ b/chipdrivers.h
@@ -41,6 +41,7 @@
int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
+int spi_block_erase_53(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
diff --git a/flashchips.c b/flashchips.c
index 5cb71a8..535b79c 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -16146,6 +16146,63 @@
{
.vendor = "Spansion",
+ .name = "S25FL128L",
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL128L,
+ .total_size = 16384,
+ .page_size = 256,
+ /* 4 x 256B Security Region (OTP) */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 4096} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 512} },
+ .block_erase = spi_block_erase_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {16384 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { {16384 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp2_srwd,
+ .unlock = spi_disable_blockprotect_bp2_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ /*
+ * Note: This chip has a read-only Status Register 2 that is not
+ * counted here. Registers are mapped as follows:
+ * STATUS1 ... Status Register 1
+ * STATUS2 ... Configuration Register 1
+ * STATUS3 ... Configuration Register 2
+ */
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW},
+ .sec = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
+ .wps = {STATUS3, 2, RW},
+ },
+ .decode_range = decode_range_spi25,
+ },
+
+ {
+ .vendor = "Spansion",
.name = "S25FL128P......0", /* uniform 64 kB sectors */
.bustype = BUS_SPI,
.manufacture_id = SPANSION_ID,
@@ -16511,6 +16568,72 @@
{
.vendor = "Spansion",
+ .name = "S25FL256L",
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL256L,
+ .total_size = 32768,
+ .page_size = 256,
+ /* 4 x 256B Security Region (OTP) */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP |
+ FEATURE_4BA_ENTER | FEATURE_4BA_NATIVE,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = spi_block_erase_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = spi_block_erase_53,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = spi_block_erase_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = spi_block_erase_dc,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {32768 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { {32768 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp3_srwd,
+ .unlock = spi_disable_blockprotect_bp3_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ /*
+ * Note: This chip has a read-only Status Register 2 that is not
+ * counted here. Registers are mapped as follows:
+ * STATUS1 ... Status Register 1
+ * STATUS2 ... Configuration Register 1
+ * STATUS3 ... Configuration Register 2
+ */
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
+ .wps = {STATUS3, 2, RW},
+ },
+ .decode_range = decode_range_spi25,
+ },
+
+ {
+ .vendor = "Spansion",
.name = "S25FL256S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */
.bustype = BUS_SPI,
.manufacture_id = SPANSION_ID,
diff --git a/flashchips.h b/flashchips.h
index 9b89355..724a275 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -666,6 +666,8 @@
#define SPANSION_S25FL216 0x4015 /* Same as S25FL216K, but the latter supports OTP, 3 status regs, quad I/O, SFDP etc. */
#define SPANSION_S25FL132K 0x4016
#define SPANSION_S25FL164K 0x4017
+#define SPANSION_S25FL128L 0x6018
+#define SPANSION_S25FL256L 0x6019
/* Spansion 29GL families got a suffix indicating the process technology but share the same 3-Byte IDs. They can
* however be differentiated by CFI byte 45h. Some versions exist which have special top or bottom boot sectors
diff --git a/spi25.c b/spi25.c
index c5832fb..60ddb96 100644
--- a/spi25.c
+++ b/spi25.c
@@ -569,6 +569,13 @@
}
/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
+int spi_block_erase_53(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
+{
+ /* This usually takes 100-4000ms, so wait in 100ms steps. */
+ return spi_write_cmd(flash, 0x53, true, addr, NULL, 0, 100 * 1000);
+}
+
+/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
{
/* This usually takes 100-4000ms, so wait in 100ms steps. */
@@ -597,6 +604,8 @@
return &spi_block_erase_50;
case 0x52:
return &spi_block_erase_52;
+ case 0x53:
+ return &spi_block_erase_53;
case 0x5c:
return &spi_block_erase_5c;
case 0x60: