diff --git a/flash.h b/flash.h
index 81fdbd7..700b3f4 100644
--- a/flash.h
+++ b/flash.h
@@ -83,6 +83,7 @@
 #define FEATURE_LONG_RESET	(0 << 4)
 #define FEATURE_SHORT_RESET	(1 << 4)
 #define FEATURE_EITHER_RESET	FEATURE_LONG_RESET
+#define FEATURE_RESET_MASK	(FEATURE_LONG_RESET | FEATURE_SHORT_RESET)
 #define FEATURE_ADDR_FULL	(0 << 2)
 #define FEATURE_ADDR_MASK	(3 << 2)
 #define FEATURE_ADDR_2AA	(1 << 2)
diff --git a/jedec.c b/jedec.c
index 4f042f2..199c64d 100644
--- a/jedec.c
+++ b/jedec.c
@@ -142,6 +142,26 @@
 		return 0;
 	}
 
+	/* Earlier probes might have been too fast for the chip to enter ID
+	 * mode completely. Allow the chip to finish this before seeing a
+	 * reset command.
+	 */
+	if (probe_timing_enter)
+		programmer_delay(probe_timing_enter);
+	/* Reset chip to a clean slate */
+	if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
+	{
+		chip_writeb(0xAA, bios + (0x5555 & mask));
+		if (probe_timing_exit)
+			programmer_delay(10);
+		chip_writeb(0x55, bios + (0x2AAA & mask));
+		if (probe_timing_exit)
+			programmer_delay(10);
+	}
+	chip_writeb(0xF0, bios + (0x5555 & mask));
+	if (probe_timing_exit)
+		programmer_delay(probe_timing_exit);
+
 	/* Issue JEDEC Product ID Entry command */
 	chip_writeb(0xAA, bios + (0x5555 & mask));
 	if (probe_timing_enter)
@@ -172,7 +192,7 @@
 	}
 
 	/* Issue JEDEC Product ID Exit command */
-	if ((flash->feature_bits & FEATURE_SHORT_RESET) == FEATURE_LONG_RESET)
+	if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
 	{
 		chip_writeb(0xAA, bios + (0x5555 & mask));
 		if (probe_timing_exit)