)]}'
{
  "commit": "f522691658c55c2c45ec3cd08c6cf600b40f7d30",
  "tree": "dd9e90360b3c5c167e4bd6fb6a54131f89f1123f",
  "parents": [
    "b87f23b163cba1012479250d48200ee4a42c93bb"
  ],
  "author": {
    "name": "Luc Verhaegen",
    "email": "libv@skynet.be",
    "time": "Mon Dec 14 10:41:58 2009 +0000"
  },
  "committer": {
    "name": "Luc Verhaegen",
    "email": "libv@skynet.be",
    "time": "Mon Dec 14 10:41:58 2009 +0000"
  },
  "message": "Boards: Formalize intel piix4 gpo setting\n\nThe function intel_piix4_gpo_set includes proper gpo pin checking, and\ngpo pin enables when necessary.\n\nThis is a leftover from soyo SY-6BA+III code that turned out to be\nunnecessary, but still used for the epox ep-bx3 board enable which it\ncleans up and clarifies.\n\nDifference to old code:\n* typical bios delay io port 0xEB now never gets touched.\n* pci config byte 0xB0 was not altered before.\n\nCorresponding to flashrom svn r803.\n\nSigned-off-by: Luc Verhaegen \u003clibv@skynet.be\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b64f906b0861bb458e3a6cf960cbf20250ed8b8c",
      "old_mode": 33188,
      "old_path": "board_enable.c",
      "new_id": "35972aba9e2c7da46b88221b63399d717fe52425",
      "new_mode": 33188,
      "new_path": "board_enable.c"
    }
  ]
}