diff --git a/chipset_enable.c b/chipset_enable.c
index a7c09e9..3e19ab8 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -709,6 +709,7 @@
 	case CHIPSET_METEOR_LAKE:
 	case CHIPSET_LUNAR_LAKE:
 	case CHIPSET_ARROW_LAKE:
+	case CHIPSET_PANTHER_LAKE:
 		boot_straps = boot_straps_apl;
 		break;
 	case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1046,6 +1047,12 @@
 	return enable_flash_pch_spidev(spi_dev, name, CHIPSET_ARROW_LAKE);
 }
 
+static int enable_flash_ptl(struct flashprog_programmer *const prog,
+			    struct pci_dev *const spi_dev, const char *const name)
+{
+	return enable_flash_pch_spidev(spi_dev, name, CHIPSET_PANTHER_LAKE);
+}
+
 /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
  * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
  *
@@ -2309,6 +2316,8 @@
 	{0x8086, 0x7723,   ANY_REV, B_S,    NT,  "Intel", "Arrow Lake-H",		enable_flash_mtl},
 	{0x8086, 0xa823,   ANY_REV, B_S,    NT,  "Intel", "Lunar Lake",			enable_flash_lnl},
 	{0x8086, 0xae23,   ANY_REV, B_S,    NT,  "Intel", "Arrow Lake-S/HX",		enable_flash_arl},
+	{0x8086, 0xe323,   ANY_REV, B_S,    NT,  "Intel", "Panther Lake 404/H12Xe",	enable_flash_ptl},
+	{0x8086, 0xe423,   ANY_REV, B_S,    NT,  "Intel", "Panther Lake H",		enable_flash_ptl},
 #endif
 	{0},
 };
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 7d9c469..932ab49 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -52,6 +52,7 @@
 	case CHIPSET_METEOR_LAKE:
 	case CHIPSET_LUNAR_LAKE:
 	case CHIPSET_ARROW_LAKE:
+	case CHIPSET_PANTHER_LAKE:
 		return 16;
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 		return 10;
@@ -82,6 +83,7 @@
 	case CHIPSET_ARROW_LAKE:
 		return 6;
 	case CHIPSET_LUNAR_LAKE:
+	case CHIPSET_PANTHER_LAKE:
 		return 7;
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
@@ -138,7 +140,7 @@
 		"C620 series Lewisburg", "300/400 series Cannon/Comet Point",
 		"500/600 series Tiger/Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
 		"C740 series Emmitsburg", "Snow Ridge", "Meteor Lake", "Lunar Lake",
-		"800 series Arrow Lake",
+		"800 series Arrow Lake", "Panther Lake",
 	};
 	if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
 		cs = 0;
@@ -270,7 +272,7 @@
 		"25 MHz",
 		"reserved",
 		"14 MHz",
-		"reserved"
+		"80 MHz"
 	}, {
 		"reserved",
 		"50 MHz",
@@ -320,6 +322,7 @@
 	case CHIPSET_METEOR_LAKE:
 	case CHIPSET_LUNAR_LAKE:
 	case CHIPSET_ARROW_LAKE:
+	case CHIPSET_PANTHER_LAKE:
 		return freq_str[3][value];
 	case CHIPSET_ELKHART_LAKE:
 		return freq_str[4][value];
@@ -364,6 +367,7 @@
 	case CHIPSET_METEOR_LAKE:
 	case CHIPSET_LUNAR_LAKE:
 	case CHIPSET_ARROW_LAKE:
+	case CHIPSET_PANTHER_LAKE:
 		msg_pdbg2("Read Clock Frequency:           %s\n", "reserved");
 		return;
 	default:
@@ -395,6 +399,9 @@
 	case CHIPSET_ARROW_LAKE:
 		msg_pdbg2("Voltage Select:                 %sV\n", volt_sel[desc->component.modes.volt_sel]);
 		break;
+	case CHIPSET_PANTHER_LAKE:
+		msg_pdbg2("Voltage Select:                 %sV\n", volt_sel[1]);
+		break;
 	default:
 		break;
 	}
@@ -583,7 +590,7 @@
 				"Reg15", NULL
 			};
 			prettyprint_pch100_masters(desc, nm, masters, nr, regions);
-		} else if (cs == CHIPSET_LUNAR_LAKE) {
+		} else if (cs == CHIPSET_LUNAR_LAKE || cs == CHIPSET_PANTHER_LAKE) {
 			const char *const masters[] = {
 				"BIOS", "CSME", "GbE", "rsvd.", "EC", "PSE", "SSE", NULL
 			};
@@ -1115,6 +1122,11 @@
 		if (content->CSSL == 0x03) {
 			if (content->CSSO == 0x58) {
 				return CHIPSET_ELKHART_LAKE;
+			} else if (content->CSSO == 0x60) {
+				if (content->ISL == 0x9a)
+					return CHIPSET_PANTHER_LAKE;
+				warn_peculiar_desc("Panther Lake");
+				return CHIPSET_PANTHER_LAKE;
 			} else if (content->CSSO == 0x6c) { /* backwards compatible Jasper Lake */
 				return CHIPSET_300_SERIES_CANNON_POINT;
 			} else if (content->CSSO == 0x70) {
diff --git a/include/programmer.h b/include/programmer.h
index 43f7023..b19049e 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -371,6 +371,7 @@
 	CHIPSET_METEOR_LAKE,
 	CHIPSET_LUNAR_LAKE,
 	CHIPSET_ARROW_LAKE,
+	CHIPSET_PANTHER_LAKE,
 };
 
 /* ichspi.c */
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index 89e0cd3..97fadb1 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -141,6 +141,7 @@
 "\t- \"600\" or \"alder\" for Intel's 600 series chipsets.\n"
 "\t- \"meteor\" for Intel's Meteor Lake SoC.\n"
 "\t- \"lunar\" for Intel's Lunar Lake SoC.\n"
+"\t- \"ptl\" for Intel's Panther Lake SoC.\n"
 "\t- \"800\" or \"arrow\" for Intel's 800 series chipsets.\n"
 "\t- \"c620\" or \"lewis\" for Intel's C620 series aka. Lewisburg chipsets.\n"
 "\t- \"c740\" or \"emmits\" for Intel's C740 series chipsets.\n"
@@ -251,6 +252,8 @@
 		else if ((strcmp(csn, "800") == 0) ||
 			 (strcmp(csn, "arrow") == 0))
 			cs = CHIPSET_ARROW_LAKE;
+		else if (strcmp(csn, "ptl") == 0)
+			cs = CHIPSET_PANTHER_LAKE;
 		else if (strcmp(csn, "apollo") == 0)
 			cs = CHIPSET_APOLLO_LAKE;
 		else if (strcmp(csn, "gemini") == 0)