ichspi: Add Intel Panther Lake support
PTL looks much like Lunar Lake. The only noticed differences so far are
a reserved frequency value that means 80MHz now, and that only 1.8V are
supported.
Tested `ich_descriptors_tool' output for the BIOS of an MSI Prestige 14
Flip AI+ (D3MTG).
Documents used:
* Intel® Core™ Ultra Processors (Series 3) Datasheet, Volume 1 of 2
* Panther Lake H External Design Specification (EDS) Volume 2 of 2
* Panther Lake-H Client Platform
SPI Programming Guide
Change-Id: Ifec90975cefc26bb7109d69fcdabcfe480516732
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/397
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 7d9c469..932ab49 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -52,6 +52,7 @@
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
case CHIPSET_ARROW_LAKE:
+ case CHIPSET_PANTHER_LAKE:
return 16;
case CHIPSET_100_SERIES_SUNRISE_POINT:
return 10;
@@ -82,6 +83,7 @@
case CHIPSET_ARROW_LAKE:
return 6;
case CHIPSET_LUNAR_LAKE:
+ case CHIPSET_PANTHER_LAKE:
return 7;
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
@@ -138,7 +140,7 @@
"C620 series Lewisburg", "300/400 series Cannon/Comet Point",
"500/600 series Tiger/Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
"C740 series Emmitsburg", "Snow Ridge", "Meteor Lake", "Lunar Lake",
- "800 series Arrow Lake",
+ "800 series Arrow Lake", "Panther Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -270,7 +272,7 @@
"25 MHz",
"reserved",
"14 MHz",
- "reserved"
+ "80 MHz"
}, {
"reserved",
"50 MHz",
@@ -320,6 +322,7 @@
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
case CHIPSET_ARROW_LAKE:
+ case CHIPSET_PANTHER_LAKE:
return freq_str[3][value];
case CHIPSET_ELKHART_LAKE:
return freq_str[4][value];
@@ -364,6 +367,7 @@
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
case CHIPSET_ARROW_LAKE:
+ case CHIPSET_PANTHER_LAKE:
msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
return;
default:
@@ -395,6 +399,9 @@
case CHIPSET_ARROW_LAKE:
msg_pdbg2("Voltage Select: %sV\n", volt_sel[desc->component.modes.volt_sel]);
break;
+ case CHIPSET_PANTHER_LAKE:
+ msg_pdbg2("Voltage Select: %sV\n", volt_sel[1]);
+ break;
default:
break;
}
@@ -583,7 +590,7 @@
"Reg15", NULL
};
prettyprint_pch100_masters(desc, nm, masters, nr, regions);
- } else if (cs == CHIPSET_LUNAR_LAKE) {
+ } else if (cs == CHIPSET_LUNAR_LAKE || cs == CHIPSET_PANTHER_LAKE) {
const char *const masters[] = {
"BIOS", "CSME", "GbE", "rsvd.", "EC", "PSE", "SSE", NULL
};
@@ -1115,6 +1122,11 @@
if (content->CSSL == 0x03) {
if (content->CSSO == 0x58) {
return CHIPSET_ELKHART_LAKE;
+ } else if (content->CSSO == 0x60) {
+ if (content->ISL == 0x9a)
+ return CHIPSET_PANTHER_LAKE;
+ warn_peculiar_desc("Panther Lake");
+ return CHIPSET_PANTHER_LAKE;
} else if (content->CSSO == 0x6c) { /* backwards compatible Jasper Lake */
return CHIPSET_300_SERIES_CANNON_POINT;
} else if (content->CSSO == 0x70) {