)]}'
{
  "commit": "f38431a5b23e578cff1299b8d69e7d650c060b60",
  "tree": "293fe367a94034d5b17d622c33e0365ec1a9b871",
  "parents": [
    "c04ee22c7006d6e006086c40651b8761cea0fbfc"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Sat Sep 05 02:30:58 2009 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Sat Sep 05 02:30:58 2009 +0000"
  },
  "message": "Store block sizes and corresponding erase functions in struct flashchip\n\nI decided to fill in the info for a\nfew chips to illustrate how this works both for uniform and non-uniform\nsector sizes.\n\nstruct eraseblock{\nint size; /* Eraseblock size */\nint count; /* Number of contiguous blocks with that size */\n};\n\nstruct eraseblock doesn\u0027t correspond with a single erase block, but with\na group of contiguous erase blocks having the same size.\nGiven a (top boot block) flash chip with the following weird, but\nreal-life structure:\n\ntop\n16384\n8192\n8192\n32768\n65536\n65536\n65536\n65536\n65536\n65536\n65536\nbottom\n\nwe get the following encoding:\n{65536,7},{32768,1},{8192,2},{16384,1}\n\nAlthough the number of blocks is bigger than 4, the number of block\ngroups is only 4. If you ever add some flash chips with more than 4\ncontiguous block groups, the definition will not fit into the 4-member\narray anymore and gcc will recognize that and error out. No undetected\noverflow possible. In that case, you simply increase array size a bit.\nFor modern flash chips with uniform erase block size, you only need one\narray member anyway.\n\nOf course data types will need to be changed if you ever get flash chips\nwith more than 2^30 erase blocks, but even with the lowest known erase\ngranularity of 256 bytes, these flash chips will have to have a size of\na quarter Terabyte. I\u0027m pretty confident we won\u0027t see such big EEPROMs\nin the near future (or at least not attached in a way that makes\nflashrom usable). For SPI chips, we even have a guaranteed safety factor\nof 4096 over the maximum SPI chip size (which is 2^24). And if such a\nbig flash chip has uniform erase block size, you could even split it\namong the 4 array members. If you change int count to unsigned int\ncount, the storable size doubles. So with a split and a slight change of\ndata type, the maximum ROM chip size is 2 Terabytes.\n\nSince many chips have multiple block erase functions where the\neraseblock layout depends on the block erase function, this patch\ncouples the block erase functions with their eraseblock layouts.\nstruct block_eraser {\n  struct eraseblock{\n    unsigned int size; /* Eraseblock size */\n    unsigned int count; /* Number of contiguous blocks with that size */\n  } eraseblocks[NUM_ERASEREGIONS];\n  int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen);\n} block_erasers[NUM_ERASEFUNCTIONS];\n\nCorresponding to flashrom svn r719.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstepan@coresystems.de\u003e\n",
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