Various ichspi.c refinements
* add a generic preop-opcode-pair table.
* rename ich_check_opcodes to ich_init_opcodes.
* let ich_init_opcodes do not need to access flashchip structure:
. move the definition of struct preop_opcode_pair to a better place
. remove preop_opcode_pairs from 'struct flashchip'
. modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure
* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.
* fix a coding style mistake.
Corresponding to flashrom svn r367 and coreboot v2 svn r3814.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
diff --git a/flash.h b/flash.h
index 7161a4e..06156dc 100644
--- a/flash.h
+++ b/flash.h
@@ -51,12 +51,6 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-/* for pairing opcodes with their required preop */
-struct preop_opcode_pair {
- uint8_t preop;
- uint8_t opcode;
-};
-
struct flashchip {
const char *vendor;
const char *name;
@@ -82,8 +76,6 @@
int (*write) (struct flashchip *flash, uint8_t *buf);
int (*read) (struct flashchip *flash, uint8_t *buf);
- struct preop_opcode_pair *preop_opcode_pairs;
-
/* Some flash devices have an additional register space. */
volatile uint8_t *virtual_memory;
volatile uint8_t *virtual_registers;
@@ -537,6 +529,7 @@
int write_en29f002a(struct flashchip *flash, uint8_t *buf);
/* ichspi.c */
+int ich_init_opcodes();
int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr);
int ich_spi_read(struct flashchip *flash, uint8_t * buf);