)]}'
{
  "commit": "ef88423928abf61fa894d2798a9d265fd001cd26",
  "tree": "8ceb8aa058cf63a0f39e4a9c8114733b0914af1c",
  "parents": [
    "e0e8b2b8f99030962994b876353e3a69cb68af80"
  ],
  "author": {
    "name": "luke he",
    "email": "sixuerain@qq.com",
    "time": "Mon Dec 28 18:22:21 2020 +0800"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Dec 30 01:16:37 2022 +0100"
  },
  "message": "flashchips.c: Add support for XMC new SPI flash types\n\nAdds initial support for the follow SPI flash chips:\n\n XM25QU64C\n XM25QU128C\n XM25QU256C\n XM25QH64C\n XM25QH128C\n XM25QH256C\n\nflashrom-stable:\n* Added missing 4BA flags / erasers\n* Dropped wrong, superfluous comments\n* Sorted\n\nSigned-off-by: Luke He \u003csixuerain@qq.com\u003e\nChange-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70942\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "22e8a10fee3ff6c6bcaf281c5deaaeff85284607",
      "old_mode": 33188,
      "old_path": "flashchips.c",
      "new_id": "de91efc9422af16e2573c21cccf1cccb2ecd9b3a",
      "new_mode": 33188,
      "new_path": "flashchips.c"
    },
    {
      "type": "modify",
      "old_id": "e9c0432894251c418d7c542c9148241b60f4de8b",
      "old_mode": 33188,
      "old_path": "flashchips.h",
      "new_id": "1bc26a5d261b33ec0849c23327192bab80e1eea8",
      "new_mode": 33188,
      "new_path": "flashchips.h"
    }
  ]
}