)]}'
{
  "commit": "ec489e4ec65ec416a6c41ded6d5eae0b6ebd7103",
  "tree": "096c8eb5101ada5ba8b098baf30060a20f471512",
  "parents": [
    "9a87c5d6ad41f7c1512ad9f2a2f0ee60213fbef0"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed Sep 15 00:13:02 2010 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed Sep 15 00:13:02 2010 +0000"
  },
  "message": "Honor ICH SPI address window for reads\n\nICH SPI has the ability to restrict SPI read/write accesses to a given\naddress range. The low end of the range is configurable by the BIOS (and\nby flashrom if the BIOS didn\u0027t lock down the flash interface), the high\nend of the range is 0xffffff (2^24-1).\nThis patch checks for an address range restriction and uses the low end\nof the allowed range as base for SPI reads. A similar workaround for\nREMS/RES opcodes has been committed in r500.\n\nThis fixes read on the Intel D945GCLF mainboard where the stock BIOS\nenforces a restricted address range.\nPlease note that writes need the same fix, but for architectural reasons\nthat fix will be merged once partial write is available.\n\nCorresponding to flashrom svn r1170.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n\nTested by David Hendricks on the Intel D945GCLF mainboard, results at\nhttp://paste.flashrom.org/view.php?id\u003d79\n\nAcked-by: David Hendricks \u003cdhendrix@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e892e7418a3f00bc3d035824851fd30bc58e20d3",
      "old_mode": 33188,
      "old_path": "spi.c",
      "new_id": "e52ea7ab12fc8b451b48226c108b6f5cd05f44f3",
      "new_mode": 33188,
      "new_path": "spi.c"
    }
  ]
}