diff --git a/chipset_enable.c b/chipset_enable.c
index 0dfe267..5195b95 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1002,6 +1002,8 @@
 	uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
 	msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
 	void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
+	if (spibar == ERROR_PTR)
+		return ERROR_FATAL;
 
 	/* Enable Flash Writes.
 	 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).