tree ac6215697b2854550f7f0590294b8f8cbdd3f6da
parent 97bc95ce2be4e17db150a83098673cedf5b50b40
author Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 1300320625 +0000
committer Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 1300320625 +0000

Proper error handling for ICH/VIA SPI

Use 16-bit values for bit masks in 16-bit registers.
Check for SPI Cycle In Progress and wait up to 60 ms.
Do not touch reserved bits.
Reduce SPI cycle timeout from 60 s to 60 ms.
Clear transaction errors caused by our own SPI accesses.
Add better debugging in case the hardware misbehaves.

Corresponding to flashrom svn r1281.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>