)]}'
{
  "commit": "eacbd1634d70d2516b793d8470f18cd6514cf3b1",
  "tree": "ac6215697b2854550f7f0590294b8f8cbdd3f6da",
  "parents": [
    "97bc95ce2be4e17db150a83098673cedf5b50b40"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Thu Mar 17 00:10:25 2011 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Thu Mar 17 00:10:25 2011 +0000"
  },
  "message": "Proper error handling for ICH/VIA SPI\n\nUse 16-bit values for bit masks in 16-bit registers.\nCheck for SPI Cycle In Progress and wait up to 60 ms.\nDo not touch reserved bits.\nReduce SPI cycle timeout from 60 s to 60 ms.\nClear transaction errors caused by our own SPI accesses.\nAdd better debugging in case the hardware misbehaves.\n\nCorresponding to flashrom svn r1281.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Stefan Reinauer \u003cstefan.reinauer@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "66c8d51cbf1ee9674450148e9df2fc1f9ee5e678",
      "old_mode": 33188,
      "old_path": "ichspi.c",
      "new_id": "ed9289356e23bfcb425c959478756c4eff83b902",
      "new_mode": 33188,
      "new_path": "ichspi.c"
    }
  ]
}