)]}'
{
  "commit": "e5dd6e6cd5591bbfa52aca05edf5fcff8dbd4f7b",
  "tree": "557e93fbe3dc0c5f83be8c9b33e9ae8be35a6799",
  "parents": [
    "d7b5bf3f1234200c8fd19c03e72cd65ba3db13f8"
  ],
  "author": {
    "name": "Harald Gutmann",
    "email": "harald.gutmann@gmx.net",
    "time": "Tue Jan 22 16:03:19 2008 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Tue Jan 22 16:03:19 2008 +0000"
  },
  "message": "Here is just a little and simple patch to get the MX25L3205D working\n\nI\u0027ve tested and verified the chip myself, and it seems to work\neverything like supposted, since Carl-Daniel has patched flashrom to\nuse the read funktion on verifying. \n\n\"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb\nCalibrating delay loop... OK.\nNo coreboot table found.\nFound chipset \"NVIDIA MCP55\", enabling flash write... OK.\nFound board \"GIGABYTE GA-M57SLI-S4\": enabling flash write... \nSerial flash segment 0xfffe0000-0xffffffff enabled\nSerial flash segment 0x000e0000-0x000fffff enabled\nSerial flash segment 0xffee0000-0xffefffff disabled\nSerial flash segment 0xfff80000-0xfffeffff enabled\nLPC write to serial flash enabled\nserial flash pin 29\nOK.\nMX25L3205 found at physical address 0xffc00000.\nFlash part is MX25L3205 (4096 KB).\nFlash image seems to be a legacy BIOS. Disabling checks.\nVerifying flash... VERIFIED.\nbenchvice flashrom # ls -l test.4mb\n-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb\n\nCorresponding to flashrom svn r186 and coreboot v2 svn r3072.\n\nSigned-off-by: Harald Gutmann \u003charald.gutmann@gmx.net\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f4a53910df4773be54fd5342eefa2aa5aeeed756",
      "old_mode": 33188,
      "old_path": "flashchips.c",
      "new_id": "99bc08646cc72246c4d4120c7f3e13fc702ad95c",
      "new_mode": 33188,
      "new_path": "flashchips.c"
    }
  ]
}