diff --git a/chipset_enable.c b/chipset_enable.c
index 7728cb9..8210a9c 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1435,6 +1435,13 @@
 		return ERROR_FATAL;
 	}
 
+	/* RomRange2 is supposed to be used for the mapping directly below 4G. */
+	const uint32_t rom_range2 = pci_read_long(lpc, 0x6c);
+	const uint32_t rom_range_end = rom_range2 | 0xffff;
+	const uint32_t rom_range_start = (rom_range2 & 0xffff) << 16;
+	const size_t mapped_len = rom_range_end > rom_range_start ? rom_range_end - rom_range_start + 1 : 0;
+	msg_pdbg("ROM Range 2: 0x%08x..0x%08x (%zu kB)\n", rom_range_start, rom_range_end, mapped_len / KiB);
+
 	const uint32_t spibar = pci_read_long(lpc, 0xa0);
 	msg_pdbg("AltSpiCSEnable=%u, SpiRomEnable=%u", spibar >> 0 & 1, spibar >> 1 & 1);
 	msg_pdbg(", AbortEnable=%u, RouteTpm2Spi=%u", spibar >> 2 & 1, spibar >> 3 & 1);
@@ -1460,7 +1467,14 @@
 	if (virt_spibar == ERROR_PTR)
 		return ERROR_FATAL;
 
-	return amd_spi100_probe(virt_spibar);
+	void *memory_mapping = NULL;
+	if (spirom_enable && mapped_len) {
+		memory_mapping = rphysmap("SPI100 memory mapping", rom_range_start, mapped_len);
+		if (memory_mapping == ERROR_PTR)
+			memory_mapping = NULL;
+	}
+
+	return amd_spi100_probe(virt_spibar, memory_mapping, memory_mapping ? mapped_len : 0);
 }
 
 /* sets bit 0 in 0x6d */