)]}'
{
  "commit": "e2ff4e90125680a48623a2a908bff38d5b91e44e",
  "tree": "20d7cec6607c5ffd1d64d57a88148275d02a715f",
  "parents": [
    "0cea753aff33b78051febadf8786df83144b5ee7"
  ],
  "author": {
    "name": "Thomas Heijligen",
    "email": "thomas.heijligen@secunet.com",
    "time": "Mon Sep 19 23:31:08 2022 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Feb 19 13:50:18 2023 +0000"
  },
  "message": "spi25.c: Move spi_get_opcode_from_erasefn() to spi.c\n\nSplit spi_get_opcode_from_erasefn() out into spi.c to add support for\nnon spi25 flashes next.\n\nChange-Id: Id654e998d0af2d3f5845336bb98b38d724519038\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67715\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72540\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "78698cebee82e3385ad70f8e86bbac44b7828649",
      "old_mode": 33188,
      "old_path": "spi.c",
      "new_id": "ef28928d2f2d176a46b6683368d1111ae96224c8",
      "new_mode": 33188,
      "new_path": "spi.c"
    },
    {
      "type": "modify",
      "old_id": "17de949a729556dd328f8f8f70340c04d51ced2b",
      "old_mode": 33188,
      "old_path": "spi25.c",
      "new_id": "be612c60c70d84cc5fa9e0e79eeba81e60521042",
      "new_mode": 33188,
      "new_path": "spi25.c"
    }
  ]
}