)]}'
{
  "commit": "e0b92e0c8e88b19ed53c28ec71e3dd585f4b96dc",
  "tree": "41f402c9e215ab1731e58dc9451aa10190b436f0",
  "parents": [
    "12d5eb9d2047cc15b7a4b1f46514e1151342dfa6"
  ],
  "author": {
    "name": "Jan Samek",
    "email": "jan.samek@siemens.com",
    "time": "Tue Dec 06 16:42:56 2022 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Mar 14 23:59:16 2023 +0000"
  },
  "message": "chipset_enable.c: add PCI ID for TGL-UP3\n\nAdd PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.\n\nChange-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407\nSigned-off-by: Jan Samek \u003cjan.samek@siemens.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388\nOriginal-Reviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73485\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "53df730eeabe170747f6540ae08c6d5357be04c0",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "6531a63b9df1919d842cc1aac2f20a1261343a49",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}