chipset_enable.c: add PCI ID for TGL-UP3
Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.
Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73485
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/chipset_enable.c b/chipset_enable.c
index 53df730..6531a63 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2121,6 +2121,7 @@
{0x8086, 0xa083, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP3 Base", enable_flash_pch500},
{0x8086, 0xa086, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP4 Super", enable_flash_pch500},
{0x8086, 0xa087, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP4 Premium", enable_flash_pch500},
+ {0x8086, 0xa088, ANY_REV, B_S, DEP, "Intel", "Tiger Lake UP3", enable_flash_pch500},
{0x8086, 0xa141, ANY_REV, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, ANY_REV, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, ANY_REV, B_S, DEP, "Intel", "H110", enable_flash_pch100},