)]}'
{
  "commit": "dac4239136fcbfdd29e5f71cfe8d570d5be26494",
  "tree": "4068869ae91e978984a79e8eab8b0202aa716293",
  "parents": [
    "56d236bda45dfe9069fd29773965aa269506e0a9"
  ],
  "author": {
    "name": "Nicholas Chin",
    "email": "nic.c3.14@gmail.com",
    "time": "Tue Jul 30 20:01:59 2024 -0600"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Mon Aug 19 10:58:13 2024 +0000"
  },
  "message": "ch347_spi: Add \u0027spimode\u0027 parameter\n\nThis allows the SPI mode (clock polarity and phase) of the CH347 to be\nselected. By default mode 0 is used, as most flash chips are compatible\nwith this mode. I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/244\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2b42077a78f638395b19a0ef10142fb168379ce8",
      "old_mode": 33188,
      "old_path": "ch347_spi.c",
      "new_id": "7772fe099c9a672e99d56542a5bb71bbc98fc870",
      "new_mode": 33188,
      "new_path": "ch347_spi.c"
    },
    {
      "type": "modify",
      "old_id": "c8f35d7c266d7c2f38cefce4c80c8ac43fa598ac",
      "old_mode": 33188,
      "old_path": "flashprog.8.tmpl",
      "new_id": "0598b8482938603ea73411e216fe2d1c20c2886c",
      "new_mode": 33188,
      "new_path": "flashprog.8.tmpl"
    }
  ]
}