commit d5ba24c1a0870c9b1e3142ffa122851b22acf0da
author Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Mon Jul 25 00:28:35 2022 +0300
committer Nico Huber <nico.h@gmx.de> Fri Dec 30 01:16:56 2022 +0100
tree 8208daddbf73ed9733b183524519d1c8b5206601
parent b1fb3f7a21d6654a2c31a2f68235c1ae9ddb1b86

flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E

Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

flashchips.c

diff --git a/flashchips.c b/flashchips.c
index 2d6ef94..59907fc 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -11220,6 +11220,17 @@
 		.write		= spi_chip_write_256, /* Multi I/O supported */
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {1700, 2000},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= decode_range_spi25,
 	},
 
 	{
@@ -11254,6 +11265,17 @@
 		.write		= spi_chip_write_256, /* Multi I/O supported */
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= decode_range_spi25,
 	},
 
 	{
@@ -11288,6 +11310,17 @@
 		.write		= spi_chip_write_256, /* Multi I/O supported */
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {1700, 2000},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= decode_range_spi25,
 	},
 
 	{
@@ -11322,6 +11355,17 @@
 		.write		= spi_chip_write_256, /* Multi I/O supported */
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= decode_range_spi25,
 	},
 
 	{
@@ -11961,6 +12005,13 @@
 		.write		= spi_chip_write_256, /* Multi I/O supported */
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= decode_range_spi25,
 	},
 
 	{