diff --git a/chipset_enable.c b/chipset_enable.c
index 29032fb..bb6b034 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -707,6 +707,7 @@
 	case CHIPSET_ELKHART_LAKE:
 	case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
 	case CHIPSET_METEOR_LAKE:
+	case CHIPSET_LUNAR_LAKE:
 		boot_straps = boot_straps_apl;
 		break;
 	case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1032,6 +1033,12 @@
 	return enable_flash_pch_spidev(spi_dev, name, CHIPSET_METEOR_LAKE);
 }
 
+static int enable_flash_lnl(struct flashprog_programmer *const prog,
+			    struct pci_dev *const spi_dev, const char *const name)
+{
+	return enable_flash_pch_spidev(spi_dev, name, CHIPSET_LUNAR_LAKE);
+}
+
 /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
  * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
  *
@@ -2234,6 +2241,7 @@
 	{0x8086, 0x7aa4,   ANY_REV, B_S,    NT,  "Intel", "Alder Lake-S",		enable_flash_pch500},
 	{0x8086, 0x18e0,   ANY_REV, B_S,    NT,  "Intel", "Snow Ridge",			enable_flash_snowridge},
 	{0x8086, 0x7e23,   ANY_REV, B_S,    DEP, "Intel", "Meteor Lake",		enable_flash_mtl},
+	{0x8086, 0xa823,   ANY_REV, B_S,    NT,  "Intel", "Lunar Lake",			enable_flash_lnl},
 #endif
 	{0},
 };