ichspi: Add Intel Lunar Lake support
Hardware looks much the same as Meteor Lake. The descriptor, however,
knows 7 masters and regions are named a bit differently. Hence, add a
new enum entry for Lunar Lake.
Tested `ich_descriptors_tool' output for an MSI Prestige 13 A2VMG BIOS.
Documents used:
* Intel® Core™ Ultra 200V Series Processors Datasheet, Volumes 1 and 2
* Lunar Lake Client Platform
SPI Programming Guide
Change-Id: Ia377872cba56a3db6d853b7ce1bd495e5a03a868
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/271
diff --git a/chipset_enable.c b/chipset_enable.c
index 29032fb..bb6b034 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -707,6 +707,7 @@
case CHIPSET_ELKHART_LAKE:
case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
case CHIPSET_METEOR_LAKE:
+ case CHIPSET_LUNAR_LAKE:
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1032,6 +1033,12 @@
return enable_flash_pch_spidev(spi_dev, name, CHIPSET_METEOR_LAKE);
}
+static int enable_flash_lnl(struct flashprog_programmer *const prog,
+ struct pci_dev *const spi_dev, const char *const name)
+{
+ return enable_flash_pch_spidev(spi_dev, name, CHIPSET_LUNAR_LAKE);
+}
+
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
@@ -2234,6 +2241,7 @@
{0x8086, 0x7aa4, ANY_REV, B_S, NT, "Intel", "Alder Lake-S", enable_flash_pch500},
{0x8086, 0x18e0, ANY_REV, B_S, NT, "Intel", "Snow Ridge", enable_flash_snowridge},
{0x8086, 0x7e23, ANY_REV, B_S, DEP, "Intel", "Meteor Lake", enable_flash_mtl},
+ {0x8086, 0xa823, ANY_REV, B_S, NT, "Intel", "Lunar Lake", enable_flash_lnl},
#endif
{0},
};
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 0f941b4..6bcbbed 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -50,6 +50,7 @@
case CHIPSET_ELKHART_LAKE:
case CHIPSET_SNOW_RIDGE:
case CHIPSET_METEOR_LAKE:
+ case CHIPSET_LUNAR_LAKE:
return 16;
case CHIPSET_100_SERIES_SUNRISE_POINT:
return 10;
@@ -78,6 +79,8 @@
case CHIPSET_SNOW_RIDGE:
case CHIPSET_METEOR_LAKE:
return 6;
+ case CHIPSET_LUNAR_LAKE:
+ return 7;
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -131,7 +134,7 @@
"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
"C620 series Lewisburg", "300/400 series Cannon/Comet Point",
"500/600 series Tiger/Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
- "C740 series Emmitsburg", "Snow Ridge", "Meteor Lake",
+ "C740 series Emmitsburg", "Snow Ridge", "Meteor Lake", "Lunar Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -311,6 +314,7 @@
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_METEOR_LAKE:
+ case CHIPSET_LUNAR_LAKE:
return freq_str[3][value];
case CHIPSET_ELKHART_LAKE:
return freq_str[4][value];
@@ -353,6 +357,7 @@
return;
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_METEOR_LAKE:
+ case CHIPSET_LUNAR_LAKE:
msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
return;
default:
@@ -557,6 +562,17 @@
"Reg15", NULL
};
prettyprint_pch100_masters(desc, nm, masters, nr, regions);
+ } else if (cs == CHIPSET_LUNAR_LAKE) {
+ const char *const masters[] = {
+ "BIOS", "CSME", "GbE", "rsvd.", "EC", "PSE", "SSE", NULL
+ };
+ const char *const regions[] = {
+ " FD ", "BIOS ", "CSME ", " GbE ", "Pltf.",
+ "Reg5 ", "Reg6 ", "Reg7 ", " EC ", "Reg9 ",
+ " PSE ", "Reg11", "Reg12", "Reg13", "Reg14",
+ "Reg15", NULL
+ };
+ prettyprint_pch100_masters(desc, nm, masters, nr, regions);
} else {
const char *const masters[] = {
"BIOS", "ME", "GbE", "NAC", "EC", "SSE", NULL
@@ -1075,6 +1091,9 @@
} else if (content->CSSO == 0x6c) { /* backwards compatible Jasper Lake */
return CHIPSET_300_SERIES_CANNON_POINT;
} else if (content->CSSO == 0x70) {
+ /* 0x7d from in SPI guide, 0x7e found in the wild */
+ if (content->ISL == 0x7d || content->ISL == 0x7e)
+ return CHIPSET_LUNAR_LAKE;
if (content->ISL == 0x82)
return CHIPSET_METEOR_LAKE;
}
diff --git a/include/programmer.h b/include/programmer.h
index 845e91a..8f83155 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -369,6 +369,7 @@
CHIPSET_C740_SERIES_EMMITSBURG = CHIPSET_HAS_NEW_ACCESS_PERM,
CHIPSET_SNOW_RIDGE,
CHIPSET_METEOR_LAKE,
+ CHIPSET_LUNAR_LAKE,
};
/* ichspi.c */
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index d058988..e5444de 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -140,6 +140,7 @@
"\t- \"500\" or \"tiger\" for Intel's 500 series chipsets.\n"
"\t- \"600\" or \"alder\" for Intel's 600 series chipsets.\n"
"\t- \"meteor\" for Intel's Meteor Lake SoC.\n"
+"\t- \"lunar\" for Intel's Lunar Lake SoC.\n"
"\t- \"c620\" or \"lewis\" for Intel's C620 series aka. Lewisburg chipsets.\n"
"\t- \"c740\" or \"emmits\" for Intel's C740 series chipsets.\n"
"\t- \"snow\" for Intel's Snow Ridge SoC.\n"
@@ -244,6 +245,8 @@
cs = CHIPSET_500_SERIES_TIGER_POINT;
else if (strcmp(csn, "meteor") == 0)
cs = CHIPSET_METEOR_LAKE;
+ else if (strcmp(csn, "lunar") == 0)
+ cs = CHIPSET_LUNAR_LAKE;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
else if (strcmp(csn, "gemini") == 0)