tree 0a7bb8254865783ad1fa1dc958e74e1a57936953
parent 93c306939b732fb05f6d8a692acc3fca78bc0f9f
author Nico Huber <nico.h@gmx.de> 1490309147 +0100
committer Nico Huber <nico.h@gmx.de> 1501244578 +0000

ichspi: Add support for Intel Skylake

The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:

  * Support for more flash regions moved PR* registers
  * Only 4KiB erase blocks are supported by the primary erase command
  * A second erase command for 64KiB pages was added
  * More commands were added for status register access etc.
  * A "Dedicated Lock Bits" register was added

No support for the new commands was added.

The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.

Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:

  commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1
  Author: Ramya Vijaykumar <ramya.vijaykumar@intel.com>

      flashrom: Add Skylake platform support

Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>