)]}'
{
  "commit": "d54e4f467753a247552bfb629f007f8931b0caa7",
  "tree": "0a7bb8254865783ad1fa1dc958e74e1a57936953",
  "parents": [
    "93c306939b732fb05f6d8a692acc3fca78bc0f9f"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Thu Mar 23 23:45:47 2017 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Jul 28 12:22:58 2017 +0000"
  },
  "message": "ichspi: Add support for Intel Skylake\n\nThe Sunrise Point PCH, paired with Skylake, has some minor changes\nin the HW sequencing interface:\n\n  * Support for more flash regions moved PR* registers\n  * Only 4KiB erase blocks are supported by the primary erase command\n  * A second erase command for 64KiB pages was added\n  * More commands were added for status register access etc.\n  * A \"Dedicated Lock Bits\" register was added\n\nNo support for the new commands was added.\n\nThe SW sequencing interface seems to have moved register location and\nis not supported any more officially. It\u0027s also untested.\n\nChanges are loosely based on the Skylake support commit in Chromium OS\nby Ramya Vijaykumar:\n\n  commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1\n  Author: Ramya Vijaykumar \u003cramya.vijaykumar@intel.com\u003e\n\n      flashrom: Add Skylake platform support\n\nChange-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18962\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\n",
  "tree_diff": [
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