tree ada182ab55fe420fa36782479efbae6030c04dce
parent c1fa3418ad546f1c6029174fa2f75c0e6b48e7a2
author Nico Huber <nico.h@gmx.de> 1676414238 +0100
committer Nico Huber <nico.h@gmx.de> 1678838356 +0000

chipset_enable: Add missing Tiger Lake IDs

It is unclear if the SPI controller is never hidden on Tiger Lake,
hence we keep stacking the IDs of the eSPI controller. Tiger Point H
IDs are from [1], the UP3/4 IDs from [2].

[1] Intel(r) 500 Series Chipset Family Platform Controller Hub
    Datasheet, Volume 1 of 2
    Doc. No.: 635218, Rev.: 008
[2] `src/include/device/pci_ids.h` in coreboot

Change-Id: I4e50df6d6511e0ecd1ead96c67247e433fbf271a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>