)]}'
{
  "commit": "d48318c92c88d35e9b90d61796d18df1266f2a82",
  "tree": "ada182ab55fe420fa36782479efbae6030c04dce",
  "parents": [
    "c1fa3418ad546f1c6029174fa2f75c0e6b48e7a2"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Feb 14 23:37:18 2023 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Mar 14 23:59:16 2023 +0000"
  },
  "message": "chipset_enable: Add missing Tiger Lake IDs\n\nIt is unclear if the SPI controller is never hidden on Tiger Lake,\nhence we keep stacking the IDs of the eSPI controller. Tiger Point H\nIDs are from [1], the UP3/4 IDs from [2].\n\n[1] Intel(r) 500 Series Chipset Family Platform Controller Hub\n    Datasheet, Volume 1 of 2\n    Doc. No.: 635218, Rev.: 008\n[2] `src/include/device/pci_ids.h` in coreboot\n\nChange-Id: I4e50df6d6511e0ecd1ead96c67247e433fbf271a\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73483\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1d6ccffaaab96bc4be85e1991cad02240878a077",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "da1768997f33b9f4f6e6097c5fe18852f6c02275",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}