chipset_enable: Add missing Tiger Lake IDs
It is unclear if the SPI controller is never hidden on Tiger Lake,
hence we keep stacking the IDs of the eSPI controller. Tiger Point H
IDs are from [1], the UP3/4 IDs from [2].
[1] Intel(r) 500 Series Chipset Family Platform Controller Hub
Datasheet, Volume 1 of 2
Doc. No.: 635218, Rev.: 008
[2] `src/include/device/pci_ids.h` in coreboot
Change-Id: I4e50df6d6511e0ecd1ead96c67247e433fbf271a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/chipset_enable.c b/chipset_enable.c
index 1d6ccff..da17689 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2116,7 +2116,11 @@
{0x8086, 0x9d84, ANY_REV, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
{0x8086, 0x0284, ANY_REV, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch300},
{0x8086, 0x0285, ANY_REV, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch300},
- {0x8086, 0xa082, ANY_REV, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500},
+ {0x8086, 0xa081, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP3 Super", enable_flash_pch500},
+ {0x8086, 0xa082, ANY_REV, B_S, DEP, "Intel", "Tiger Lake UP3 Premium", enable_flash_pch500},
+ {0x8086, 0xa083, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP3 Base", enable_flash_pch500},
+ {0x8086, 0xa086, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP4 Super", enable_flash_pch500},
+ {0x8086, 0xa087, ANY_REV, B_S, NT, "Intel", "Tiger Lake UP4 Premium", enable_flash_pch500},
{0x8086, 0xa141, ANY_REV, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, ANY_REV, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, ANY_REV, B_S, DEP, "Intel", "H110", enable_flash_pch100},
@@ -2195,11 +2199,16 @@
{0x8086, 0x068e, ANY_REV, B_S, NT, "Intel", "WM490", enable_flash_pch300},
{0x8086, 0x0697, ANY_REV, B_S, NT, "Intel", "W480", enable_flash_pch300},
{0x8086, 0x4da4, ANY_REV, B_S, NT, "Intel", "Jasper Lake", enable_flash_pch300},
+ {0x8086, 0x4381, ANY_REV, B_S, NT, "Intel", "Tiger Point Desktop ES", enable_flash_pch500},
+ {0x8086, 0x4382, ANY_REV, B_S, NT, "Intel", "Tiger Point Mobile ES", enable_flash_pch500},
+ {0x8086, 0x4383, ANY_REV, B_S, NT, "Intel", "Tiger Point Server ES", enable_flash_pch500},
{0x8086, 0x4384, ANY_REV, B_S, NT, "Intel", "Q570", enable_flash_pch500},
{0x8086, 0x4385, ANY_REV, B_S, NT, "Intel", "Z590", enable_flash_pch500},
{0x8086, 0x4386, ANY_REV, B_S, NT, "Intel", "H570", enable_flash_pch500},
{0x8086, 0x4387, ANY_REV, B_S, NT, "Intel", "B560", enable_flash_pch500},
{0x8086, 0x4388, ANY_REV, B_S, NT, "Intel", "H510", enable_flash_pch500},
+ {0x8086, 0x438c, ANY_REV, B_S, NT, "Intel", "C252", enable_flash_pch500},
+ {0x8086, 0x438d, ANY_REV, B_S, NT, "Intel", "C256", enable_flash_pch500},
{0x8086, 0x438f, ANY_REV, B_S, NT, "Intel", "W580", enable_flash_pch500},
{0x8086, 0x4389, ANY_REV, B_S, NT, "Intel", "WM590", enable_flash_pch500},
{0x8086, 0x438a, ANY_REV, B_S, NT, "Intel", "QM580", enable_flash_pch500},