diff --git a/ichspi.c b/ichspi.c
index 15222d8..3e1040d 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1742,6 +1742,7 @@
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		num_pr			= 6;	/* Includes GPR0 */
 		reg_pr0			= PCH100_REG_FPR0;
 		swseq_data.reg_ssfsc	= PCH100_REG_SSFSC;
@@ -1773,6 +1774,7 @@
 		break;
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		num_freg = 16;
 		break;
 	default:
@@ -1868,6 +1870,7 @@
 		case CHIPSET_C620_SERIES_LEWISBURG:
 		case CHIPSET_300_SERIES_CANNON_POINT:
 		case CHIPSET_APOLLO_LAKE:
+		case CHIPSET_GEMINI_LAKE:
 			tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
 			msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
 			prettyprint_pch100_reg_dlock(tmp);
@@ -1942,6 +1945,7 @@
 			case CHIPSET_C620_SERIES_LEWISBURG:
 			case CHIPSET_300_SERIES_CANNON_POINT:
 			case CHIPSET_APOLLO_LAKE:
+			case CHIPSET_GEMINI_LAKE:
 			case CHIPSET_BAYTRAIL:
 				break;
 			default:
@@ -1974,6 +1978,7 @@
 			case CHIPSET_C620_SERIES_LEWISBURG:
 			case CHIPSET_300_SERIES_CANNON_POINT:
 			case CHIPSET_APOLLO_LAKE:
+			case CHIPSET_GEMINI_LAKE:
 				break;
 			default:
 				tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
@@ -2009,8 +2014,10 @@
 			ich_spi_mode = ich_hwseq;
 		}
 
-		if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) {
-			msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n");
+		if (ich_spi_mode == ich_auto &&
+		    (ich_gen == CHIPSET_APOLLO_LAKE ||
+		     ich_gen == CHIPSET_GEMINI_LAKE)) {
+			msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n");
 			ich_spi_mode = ich_hwseq;
 		}