)]}'
{
  "commit": "d0803c8407c459e972cb9912a4a3cbfeebb93d9e",
  "tree": "7c361a17c153b09bf9da9ea685e29b4648118218",
  "parents": [
    "aac81424ebb8234b54cbab8fe47350b562b84fae"
  ],
  "author": {
    "name": "Lubomir Rintel",
    "email": "lkundrak@v3.sk",
    "time": "Mon Oct 30 07:57:53 2017 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Jan 02 20:15:45 2018 +0000"
  },
  "message": "vt_vx: check whether the chipset\u0027s MMIO range is configured\n\nAvoid attempting to read the SPI bases from the location 0x00000000, all\nzeroes mean that the chipset\u0027s MMIO area is not enabled.\n\nChange-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293\nSigned-off-by: Lubomir Rintel \u003clkundrak@v3.sk\u003e\nReviewed-on: https://review.coreboot.org/23029\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a499ba01001fe05191dcfe459d241d6795ed8a31",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "5716ebf88e10ee7439f18fc2d9c7f63f44686acf",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}